mirror of
https://github.com/Klagarge/Cursor.git
synced 2024-11-23 18:03:27 +00:00
5 lines
115 B
VHDL
5 lines
115 B
VHDL
ARCHITECTURE sim OF transUnsignedUlog IS
|
|
BEGIN
|
|
out1 <= std_ulogic_vector(in1) after delay;
|
|
END ARCHITECTURE sim;
|