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19 lines
274 B
VHDL
19 lines
274 B
VHDL
ARCHITECTURE sim OF TFF_pre IS
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signal q_int: std_ulogic;
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BEGIN
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process(clk, pre)
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begin
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if pre = '1' then
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q_int <= '1' after delay;
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elsif rising_edge(clk) then
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q_int <= t xor q_int after delay;
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end if;
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end process;
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q <= q_int;
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END sim;
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