mirror of
https://github.com/Klagarge/Cursor.git
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1876 lines
24 KiB
Plaintext
1876 lines
24 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "ieee"
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unitName "numeric_std"
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)
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]
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libraryRefs [
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"ieee"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
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commonDM (CommonDM
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ldm (LogicalDM
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ordering 1
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suid 2008,0
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usingSuid 1
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emptyRow *1 (LEmptyRow
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)
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uid 309,0
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optionalChildren [
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*2 (LogPort
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port (LogicalPort
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|
m 1
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decl (Decl
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n "wr2"
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t "std_ulogic"
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o 5
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suid 5,0
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)
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)
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uid 310,0
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)
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*3 (LogPort
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port (LogicalPort
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|
decl (Decl
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n "reset"
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t "std_ulogic"
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o 2
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suid 2,0
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)
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)
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uid 311,0
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)
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*4 (LogPort
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port (LogicalPort
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decl (Decl
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|
n "full2"
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t "std_ulogic"
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o 4
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suid 4,0
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)
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)
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|
uid 312,0
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|
)
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*5 (LogPort
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port (LogicalPort
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|
m 1
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|
decl (Decl
|
|
n "rd1"
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t "std_ulogic"
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o 8
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suid 8,0
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)
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)
|
|
uid 313,0
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|
)
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|
*6 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "data1"
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|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
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o 6
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suid 7,0
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)
|
|
)
|
|
uid 314,0
|
|
)
|
|
*7 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
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|
o 1
|
|
suid 1,0
|
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)
|
|
)
|
|
uid 315,0
|
|
)
|
|
*8 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "empty1"
|
|
t "std_ulogic"
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|
o 7
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|
suid 6,0
|
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)
|
|
)
|
|
uid 316,0
|
|
)
|
|
*9 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "data2"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 317,0
|
|
)
|
|
*10 (RefLabelRowHdr
|
|
)
|
|
*11 (TitleRowHdr
|
|
)
|
|
*12 (FilterRowHdr
|
|
)
|
|
*13 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*14 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*15 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*16 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*17 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*18 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*19 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*20 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*21 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
]
|
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)
|
|
pdm (PhysicalDM
|
|
uid 318,0
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|
optionalChildren [
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|
*22 (Sheet
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|
sheetRow (SheetRow
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|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
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|
)
|
|
emptyMRCItem *23 (MRCItem
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|
litem &1
|
|
pos 8
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dimension 20
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)
|
|
uid 245,0
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|
optionalChildren [
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|
*24 (MRCItem
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litem &10
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|
pos 0
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|
dimension 20
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|
uid 248,0
|
|
)
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|
*25 (MRCItem
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|
litem &11
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|
pos 1
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|
dimension 23
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|
uid 250,0
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)
|
|
*26 (MRCItem
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litem &12
|
|
pos 2
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|
hidden 1
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|
dimension 20
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|
uid 252,0
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|
)
|
|
*27 (MRCItem
|
|
litem &2
|
|
pos 4
|
|
dimension 20
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|
uid 271,0
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|
)
|
|
*28 (MRCItem
|
|
litem &3
|
|
pos 1
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|
dimension 20
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|
uid 272,0
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|
)
|
|
*29 (MRCItem
|
|
litem &4
|
|
pos 3
|
|
dimension 20
|
|
uid 273,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &5
|
|
pos 7
|
|
dimension 20
|
|
uid 274,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &6
|
|
pos 5
|
|
dimension 20
|
|
uid 275,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &7
|
|
pos 0
|
|
dimension 20
|
|
uid 276,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &8
|
|
pos 6
|
|
dimension 20
|
|
uid 277,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &9
|
|
pos 2
|
|
dimension 20
|
|
uid 278,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 246,0
|
|
optionalChildren [
|
|
*35 (MRCItem
|
|
litem &13
|
|
pos 0
|
|
dimension 20
|
|
uid 254,0
|
|
)
|
|
*36 (MRCItem
|
|
litem &15
|
|
pos 1
|
|
dimension 50
|
|
uid 258,0
|
|
)
|
|
*37 (MRCItem
|
|
litem &16
|
|
pos 2
|
|
dimension 100
|
|
uid 260,0
|
|
)
|
|
*38 (MRCItem
|
|
litem &17
|
|
pos 3
|
|
dimension 50
|
|
uid 262,0
|
|
)
|
|
*39 (MRCItem
|
|
litem &18
|
|
pos 4
|
|
dimension 100
|
|
uid 264,0
|
|
)
|
|
*40 (MRCItem
|
|
litem &19
|
|
pos 5
|
|
dimension 100
|
|
uid 266,0
|
|
)
|
|
*41 (MRCItem
|
|
litem &20
|
|
pos 6
|
|
dimension 50
|
|
uid 268,0
|
|
)
|
|
*42 (MRCItem
|
|
litem &21
|
|
pos 7
|
|
dimension 80
|
|
uid 270,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 244,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 308,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *43 (LEmptyRow
|
|
)
|
|
uid 320,0
|
|
optionalChildren [
|
|
*44 (RefLabelRowHdr
|
|
)
|
|
*45 (TitleRowHdr
|
|
)
|
|
*46 (FilterRowHdr
|
|
)
|
|
*47 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*48 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*49 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*50 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*51 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*52 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*53 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*54 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*55 (LogGeneric
|
|
generic (GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 304,0
|
|
)
|
|
*56 (LogGeneric
|
|
generic (GiElement
|
|
name "fifoDepth"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
uid 305,0
|
|
)
|
|
*57 (LogGeneric
|
|
generic (GiElement
|
|
name "firstWordFallThrough"
|
|
type "boolean"
|
|
value "false"
|
|
e "first byte written into the FIFO immediately appears on the output"
|
|
)
|
|
uid 370,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 321,0
|
|
optionalChildren [
|
|
*58 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
)
|
|
emptyMRCItem *59 (MRCItem
|
|
litem &43
|
|
pos 3
|
|
dimension 20
|
|
)
|
|
uid 280,0
|
|
optionalChildren [
|
|
*60 (MRCItem
|
|
litem &44
|
|
pos 0
|
|
dimension 20
|
|
uid 283,0
|
|
)
|
|
*61 (MRCItem
|
|
litem &45
|
|
pos 1
|
|
dimension 23
|
|
uid 285,0
|
|
)
|
|
*62 (MRCItem
|
|
litem &46
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 287,0
|
|
)
|
|
*63 (MRCItem
|
|
litem &55
|
|
pos 0
|
|
dimension 20
|
|
uid 306,0
|
|
)
|
|
*64 (MRCItem
|
|
litem &56
|
|
pos 1
|
|
dimension 20
|
|
uid 307,0
|
|
)
|
|
*65 (MRCItem
|
|
litem &57
|
|
pos 2
|
|
dimension 20
|
|
uid 371,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "courier,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 281,0
|
|
optionalChildren [
|
|
*66 (MRCItem
|
|
litem &47
|
|
pos 0
|
|
dimension 20
|
|
uid 289,0
|
|
)
|
|
*67 (MRCItem
|
|
litem &49
|
|
pos 1
|
|
dimension 50
|
|
uid 293,0
|
|
)
|
|
*68 (MRCItem
|
|
litem &50
|
|
pos 2
|
|
dimension 100
|
|
uid 295,0
|
|
)
|
|
*69 (MRCItem
|
|
litem &51
|
|
pos 3
|
|
dimension 100
|
|
uid 297,0
|
|
)
|
|
*70 (MRCItem
|
|
litem &52
|
|
pos 4
|
|
dimension 50
|
|
uid 299,0
|
|
)
|
|
*71 (MRCItem
|
|
litem &53
|
|
pos 5
|
|
dimension 50
|
|
uid 301,0
|
|
)
|
|
*72 (MRCItem
|
|
litem &54
|
|
pos 6
|
|
dimension 80
|
|
uid 303,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 279,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 319,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@rx@to@tx/symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@rx@to@tx/symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@rx@to@tx"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeRxToTx"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "28"
|
|
)
|
|
(vvPair
|
|
variable "designName"
|
|
value "$DESIGN_NAME"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "fifoBridgeRxToTx"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "08/28/19"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "13:45:14"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "Aphelia"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "Memory"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Concatenation"
|
|
value "U:/ELN_Board/Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_Generic_1_file"
|
|
value "D:\\Users\\FCo HEVs\\Projets\\OCT\\Technique\\VHDL\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_HdsLintPlugin"
|
|
value "$HDS_PROJECT_DIR/../Demo/designcheck"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSim"
|
|
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/Libs/Memory/work"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_SpyGlass"
|
|
value "D:\\Users\\FCo HEVs\\Projets\\OCT\\Technique\\VHDL\\Synthesis"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "08"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "fifoBridgeRxToTx"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Aug"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "August"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifo@bridge@rx@to@tx/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory/hds/fifoBridgeRxToTx/symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_HDSPath"
|
|
value "$HDS_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEBinPath"
|
|
value "$ISE_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "$ISE_SCRATCH_WORK_DIR"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "$MODELSIM_HOME"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "13:45:14"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "fifoBridgeRxToTx"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "francois"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "year"
|
|
value "2019"
|
|
)
|
|
(vvPair
|
|
variable "yy"
|
|
value "19"
|
|
)
|
|
]
|
|
)
|
|
LanguageMgr "Vhdl2008LangMgr"
|
|
uid 51,0
|
|
optionalChildren [
|
|
*73 (SymbolBody
|
|
uid 8,0
|
|
optionalChildren [
|
|
*74 (CptPort
|
|
uid 173,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 174,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "34250,21625,35000,22375"
|
|
)
|
|
tg (CPTG
|
|
uid 175,0
|
|
ps "CptPortTextPlaceStrategy"
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|
stg "VerticalLayoutStrategy"
|
|
f (Text
|
|
uid 176,0
|
|
va (VaSet
|
|
font "courier,9,0"
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|
xt "36000,21400,39400,22600"
|
|
st "clock"
|
|
blo "36000,22400"
|
|
tm "CptPortNameMgr"
|
|
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|
|
)
|
|
dt (MLText
|
|
uid 177,0
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va (VaSet
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font "courier,8,0"
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|
)
|
|
xt "2000,7800,17000,8700"
|
|
st "clock : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "clock"
|
|
t "std_ulogic"
|
|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
)
|
|
*75 (CptPort
|
|
uid 178,0
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ps "OnEdgeStrategy"
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shape (Triangle
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uid 179,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
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fg "0,65535,0"
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|
)
|
|
xt "34250,23625,35000,24375"
|
|
)
|
|
tg (CPTG
|
|
uid 180,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 181,0
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va (VaSet
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font "courier,9,0"
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xt "36000,23400,39300,24600"
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st "reset"
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|
blo "36000,24400"
|
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tm "CptPortNameMgr"
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dt (MLText
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uid 182,0
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va (VaSet
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font "courier,8,0"
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)
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xt "2000,8700,17000,9600"
|
|
st "reset : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "reset"
|
|
t "std_ulogic"
|
|
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|
|
suid 2,0
|
|
)
|
|
)
|
|
)
|
|
*76 (CptPort
|
|
uid 188,0
|
|
ps "OnEdgeStrategy"
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shape (Triangle
|
|
uid 322,0
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va (VaSet
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|
vasetType 1
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fg "0,65535,0"
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|
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xt "51000,13625,51750,14375"
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tg (CPTG
|
|
uid 190,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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|
uid 191,0
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va (VaSet
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font "courier,9,0"
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)
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xt "46400,13400,50000,14600"
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|
st "data2"
|
|
ju 2
|
|
blo "50000,14400"
|
|
tm "CptPortNameMgr"
|
|
)
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|
)
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dt (MLText
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|
uid 192,0
|
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va (VaSet
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font "courier,8,0"
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|
)
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xt "2000,9600,31500,10500"
|
|
st "data2 : OUT std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "data2"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 3
|
|
suid 3,0
|
|
)
|
|
)
|
|
)
|
|
*77 (CptPort
|
|
uid 198,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 241,0
|
|
ro 270
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,15625,51750,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 200,0
|
|
ps "CptPortTextPlaceStrategy"
|
|
stg "RightVerticalLayoutStrategy"
|
|
f (Text
|
|
uid 201,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "47100,15400,50000,16600"
|
|
st "full2"
|
|
ju 2
|
|
blo "50000,16400"
|
|
tm "CptPortNameMgr"
|
|
)
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)
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|
dt (MLText
|
|
uid 202,0
|
|
va (VaSet
|
|
font "courier,8,0"
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)
|
|
xt "2000,10500,17000,11400"
|
|
st "full2 : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "full2"
|
|
t "std_ulogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
)
|
|
*78 (CptPort
|
|
uid 208,0
|
|
ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 243,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
)
|
|
xt "51000,17625,51750,18375"
|
|
)
|
|
tg (CPTG
|
|
uid 210,0
|
|
ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
|
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f (Text
|
|
uid 211,0
|
|
va (VaSet
|
|
font "courier,9,0"
|
|
)
|
|
xt "47500,17400,50000,18600"
|
|
st "wr2"
|
|
ju 2
|
|
blo "50000,18400"
|
|
tm "CptPortNameMgr"
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|
)
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)
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dt (MLText
|
|
uid 212,0
|
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va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,11400,17000,12300"
|
|
st "wr2 : OUT std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "wr2"
|
|
t "std_ulogic"
|
|
o 5
|
|
suid 5,0
|
|
)
|
|
)
|
|
)
|
|
*79 (CptPort
|
|
uid 215,0
|
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ps "OnEdgeStrategy"
|
|
shape (Triangle
|
|
uid 216,0
|
|
ro 90
|
|
va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
|
|
)
|
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xt "34250,15625,35000,16375"
|
|
)
|
|
tg (CPTG
|
|
uid 217,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 218,0
|
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va (VaSet
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font "courier,9,0"
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)
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st "empty1"
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blo "36000,16400"
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tm "CptPortNameMgr"
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dt (MLText
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va (VaSet
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font "courier,8,0"
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)
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xt "2000,13200,17000,14100"
|
|
st "empty1 : IN std_ulogic ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "empty1"
|
|
t "std_ulogic"
|
|
o 7
|
|
suid 6,0
|
|
)
|
|
)
|
|
)
|
|
*80 (CptPort
|
|
uid 220,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 323,0
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ro 90
|
|
va (VaSet
|
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vasetType 1
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fg "0,65535,0"
|
|
)
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|
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)
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tg (CPTG
|
|
uid 222,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
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uid 223,0
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va (VaSet
|
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font "courier,9,0"
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)
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xt "36000,13400,39600,14600"
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st "data1"
|
|
blo "36000,14400"
|
|
tm "CptPortNameMgr"
|
|
)
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)
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dt (MLText
|
|
uid 224,0
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va (VaSet
|
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font "courier,8,0"
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)
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|
|
st "data1 : IN std_ulogic_vector (dataBitNb-1 DOWNTO 0) ;"
|
|
)
|
|
thePort (LogicalPort
|
|
decl (Decl
|
|
n "data1"
|
|
t "std_ulogic_vector"
|
|
b "(dataBitNb-1 DOWNTO 0)"
|
|
o 6
|
|
suid 7,0
|
|
)
|
|
)
|
|
)
|
|
*81 (CptPort
|
|
uid 230,0
|
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ps "OnEdgeStrategy"
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shape (Triangle
|
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uid 231,0
|
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ro 270
|
|
va (VaSet
|
|
vasetType 1
|
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fg "0,65535,0"
|
|
)
|
|
xt "34250,17625,35000,18375"
|
|
)
|
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tg (CPTG
|
|
uid 232,0
|
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
|
|
uid 233,0
|
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va (VaSet
|
|
font "courier,9,0"
|
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)
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xt "36000,17400,38400,18600"
|
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st "rd1"
|
|
blo "36000,18400"
|
|
tm "CptPortNameMgr"
|
|
)
|
|
)
|
|
dt (MLText
|
|
uid 234,0
|
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va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "2000,14100,16000,15000"
|
|
st "rd1 : OUT std_ulogic "
|
|
)
|
|
thePort (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "rd1"
|
|
t "std_ulogic"
|
|
o 8
|
|
suid 8,0
|
|
)
|
|
)
|
|
)
|
|
]
|
|
shape (Rectangle
|
|
uid 81,0
|
|
va (VaSet
|
|
vasetType 1
|
|
fg "0,65535,0"
|
|
bg "0,65535,0"
|
|
lineColor "0,32896,0"
|
|
lineWidth 2
|
|
)
|
|
xt "35000,10000,51000,26000"
|
|
)
|
|
oxt "15000,6000,35000,26000"
|
|
biTextGroup (BiTextGroup
|
|
uid 10,0
|
|
ps "CenterOffsetStrategy"
|
|
stg "VerticalLayoutStrategy"
|
|
first (Text
|
|
uid 11,0
|
|
va (VaSet
|
|
font "courier,9,1"
|
|
)
|
|
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|
|
st "Memory"
|
|
blo "35600,26500"
|
|
)
|
|
second (Text
|
|
uid 12,0
|
|
va (VaSet
|
|
font "courier,9,1"
|
|
)
|
|
xt "35600,26700,44100,27600"
|
|
st "fifoBridgeRxToTx"
|
|
blo "35600,27400"
|
|
)
|
|
)
|
|
gi *82 (GenericInterface
|
|
uid 13,0
|
|
ps "CenterOffsetStrategy"
|
|
matrix (Matrix
|
|
uid 14,0
|
|
text (MLText
|
|
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|
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va (VaSet
|
|
font "courier,8,0"
|
|
)
|
|
xt "35000,28800,88000,33300"
|
|
st "Generic Declarations
|
|
|
|
dataBitNb positive 8
|
|
fifoDepth positive 8
|
|
firstWordFallThrough boolean false --first byte written into the FIFO immediately appears on the output "
|
|
)
|
|
header "Generic Declarations"
|
|
showHdrWhenContentsEmpty 1
|
|
)
|
|
elements [
|
|
(GiElement
|
|
name "dataBitNb"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
(GiElement
|
|
name "fifoDepth"
|
|
type "positive"
|
|
value "8"
|
|
)
|
|
(GiElement
|
|
name "firstWordFallThrough"
|
|
type "boolean"
|
|
value "false"
|
|
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|
|
)
|
|
]
|
|
)
|
|
portInstanceVisAsIs 1
|
|
portInstanceVis (PortSigDisplay
|
|
sTC 0
|
|
)
|
|
portVis (PortSigDisplay
|
|
sTC 0
|
|
sF 0
|
|
)
|
|
)
|
|
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|
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|
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|
|
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|
uid 18,0
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|
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|
|
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|
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|
|
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|
|
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|
|
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|
|
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|
|
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|
|
text (MLText
|
|
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va (VaSet
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|
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|
|
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|
|
st "
|
|
by %user on %dd %month %year
|
|
"
|
|
tm "CommentText"
|
|
wrapOption 3
|
|
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|
|
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|
|
)
|
|
position 1
|
|
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|
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|
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|
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|
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|
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