Klagarge/Cursor
1
0
Fork 0
mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-30 12:43:28 +00:00
Code Issues Activity
e6cad3cdbf
Cursor/Libs/Memory_test/hds/flash@controller_tb/struct.bd
Rémi Heredero c7ba678fbb Initial commit
2021-11-24 10:50:51 +01:00

5567 lines
67 KiB
Plaintext
Raw Blame History

DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
)
]
instances [
(Instance
name "I1"
duLibraryName "memory_test"
duName "flashController_tester"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
mwi 0
uid 1774,0
)
(Instance
name "I0"
duLibraryName "memory"
duName "flashController"
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "chipAddressBitNb"
type "positive"
value "addressBitNb"
)
]
mwi 0
uid 7294,0
)
(Instance
name "I2"
duLibraryName "memory_test"
duName "flash_28F128J3A"
elements [
(GiElement
name "fileSpec"
type "string"
value "\"U:\\ELN_board\\Simulation\\flash.srec\""
)
(GiElement
name "T_W13"
type "time"
value "500 ns"
)
(GiElement
name "T_W16_program"
type "time"
value "1 us"
)
(GiElement
name "T_W16_erase"
type "time"
value "1.5 us"
)
(GiElement
name "T_R2"
type "time"
value "120 ns"
)
(GiElement
name "T_R3"
type "time"
value "120 ns"
)
(GiElement
name "T_R7"
type "time"
value "0 ns"
)
(GiElement
name "T_R8"
type "time"
value "55 ns"
)
(GiElement
name "T_R9"
type "time"
value "15 ns"
)
]
mwi 0
uid 7440,0
)
]
embeddedInstances [
(EmbeddedInstance
name "eb1"
number "1"
)
(EmbeddedInstance
name "eb2"
number "2"
)
]
libraryRefs [
"ieee"
]
)
version "31.1"
appVersion "2018.1 (Build 12)"
noEmbeddedEditors 1
model (BlockDiag
VExpander (VariableExpander
vvMap [
(vvPair
variable " "
value " "
)
(vvPair
variable "HDLDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hdl"
)
(vvPair
variable "HDSDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
)
(vvPair
variable "SideDataDesignDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tb/struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tb/struct.bd.user"
)
(vvPair
variable "SourceDir"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds"
)
(vvPair
variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
)
(vvPair
variable "concat_file"
value "concatenated"
)
(vvPair
variable "config"
value "%(unit)_%(view)_config"
)
(vvPair
variable "d"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tb"
)
(vvPair
variable "d_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flashController_tb"
)
(vvPair
variable "date"
value "08/28/19"
)
(vvPair
variable "day"
value "Wed"
)
(vvPair
variable "day_long"
value "Wednesday"
)
(vvPair
variable "dd"
value "28"
)
(vvPair
variable "entity_name"
value "flashController_tb"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
)
(vvPair
variable "f_noext"
value "struct"
)
(vvPair
variable "graphical_source_author"
value "francois"
)
(vvPair
variable "graphical_source_date"
value "08/28/19"
)
(vvPair
variable "graphical_source_group"
value "francois"
)
(vvPair
variable "graphical_source_host"
value "Aphelia"
)
(vvPair
variable "graphical_source_time"
value "13:45:28"
)
(vvPair
variable "group"
value "francois"
)
(vvPair
variable "host"
value "Aphelia"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "Memory_test"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\ELN_labs\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Libs/Memory_test/work"
)
(vvPair
variable "mm"
value "08"
)
(vvPair
variable "module_name"
value "flashController_tb"
)
(vvPair
variable "month"
value "Aug"
)
(vvPair
variable "month_long"
value "August"
)
(vvPair
variable "p"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flash@controller_tb/struct.bd"
)
(vvPair
variable "p_logical"
value "/home/francois/Documents/HEVs/Kart/eln_kart/04-Controller/../Libs/Memory_test/hds/flashController_tb/struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_ISEPath"
value "D:\\Labs\\ElN\\BoardTester\\Board\\ise"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "C:\\EDA\\Modelsim\\win32"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
)
(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
)
(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
)
(vvPair
variable "task_VCSPath"
value "<TBD>"
)
(vvPair
variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
)
(vvPair
variable "this_file_logical"
value "struct"
)
(vvPair
variable "time"
value "13:45:28"
)
(vvPair
variable "unit"
value "flashController_tb"
)
(vvPair
variable "user"
value "francois"
)
(vvPair
variable "version"
value "2018.1 (Build 12)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2019"
)
(vvPair
variable "yy"
value "19"
)
]
)
LanguageMgr "Vhdl2008LangMgr"
uid 198,0
optionalChildren [
*1 (Grouping
uid 1487,0
optionalChildren [
*2 (CommentText
uid 1489,0
shape (Rectangle
uid 1490,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "121000,110000,140000,112000"
)
oxt "45000,22000,64000,24000"
text (MLText
uid 1491,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "121200,110500,136800,111500"
st "
<enter project name here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 18600
)
position 1
ignorePrefs 1
)
*3 (CommentText
uid 1492,0
shape (Rectangle
uid 1493,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,110000,115000,112000"
)
oxt "13000,22000,39000,24000"
text (MLText
uid 1494,0
va (VaSet
fg "32768,0,0"
font "courier,12,1"
)
xt "96750,110350,107250,111650"
st "
<company name>
"
ju 0
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 25600
)
position 1
ignorePrefs 1
)
*4 (CommentText
uid 1495,0
shape (Rectangle
uid 1496,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,116000,115000,118000"
)
oxt "18000,28000,39000,30000"
text (MLText
uid 1497,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,116500,110400,117500"
st "
by %user on %dd %month %year
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*5 (CommentText
uid 1498,0
shape (Rectangle
uid 1499,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "115000,110000,121000,112000"
)
oxt "39000,22000,45000,24000"
text (MLText
uid 1500,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "115200,110500,120000,111500"
st "
Project:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 5600
)
position 1
ignorePrefs 1
)
*6 (CommentText
uid 1501,0
shape (Rectangle
uid 1502,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,112000,115000,114000"
)
oxt "18000,24000,39000,26000"
text (MLText
uid 1503,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,112500,110400,113500"
st "
<enter diagram title here>
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*7 (CommentText
uid 1504,0
shape (Rectangle
uid 1505,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,112000,94000,114000"
)
oxt "13000,24000,18000,26000"
text (MLText
uid 1506,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,112500,92800,113500"
st "
Title:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*8 (CommentText
uid 1507,0
shape (Rectangle
uid 1508,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,114000,94000,116000"
)
oxt "13000,26000,18000,28000"
text (MLText
uid 1509,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,114500,92200,115500"
st "
Path:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
*9 (CommentText
uid 1510,0
shape (Rectangle
uid 1511,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "115000,112000,140000,118000"
)
oxt "39000,24000,64000,30000"
text (MLText
uid 1512,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "115200,112200,128400,113200"
st "
<enter comments here>
"
tm "CommentText"
wrapOption 3
visibleHeight 5600
visibleWidth 24600
)
ignorePrefs 1
)
*10 (CommentText
uid 1513,0
shape (Rectangle
uid 1514,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "94000,114000,115000,116000"
)
oxt "18000,26000,39000,28000"
text (MLText
uid 1515,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "94200,114500,113400,115500"
st "
%library/%unit/%view
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 20600
)
position 1
ignorePrefs 1
)
*11 (CommentText
uid 1516,0
shape (Rectangle
uid 1517,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "89000,116000,94000,118000"
)
oxt "13000,28000,18000,30000"
text (MLText
uid 1518,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "89200,116500,93400,117500"
st "
Edited:
"
tm "CommentText"
wrapOption 3
visibleHeight 1600
visibleWidth 4600
)
position 1
ignorePrefs 1
)
]
shape (GroupingShape
uid 1488,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
lineWidth 1
)
xt "89000,110000,140000,118000"
)
oxt "13000,22000,64000,30000"
)
*12 (Blk
uid 1774,0
shape (Rectangle
uid 1775,0
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "16000,87000,110000,95000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 1776,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*13 (Text
uid 1777,0
va (VaSet
font "courier,12,1"
)
xt "16600,94900,27200,96300"
st "memory_test"
blo "16600,96100"
tm "BdLibraryNameMgr"
)
*14 (Text
uid 1778,0
va (VaSet
font "courier,12,1"
)
xt "16600,96300,33900,97700"
st "flashController_tester"
blo "16600,97500"
tm "BlkNameMgr"
)
*15 (Text
uid 1779,0
va (VaSet
font "courier,12,1"
)
xt "16600,97700,19000,99100"
st "I1"
blo "16600,98900"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1780,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1781,0
text (MLText
uid 1782,0
va (VaSet
font "courier,9,0"
)
xt "16000,99600,39000,101400"
st "addressBitNb = addressBitNb ( positive )
dataBitNb = dataBitNb ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
]
)
)
*16 (Net
uid 5550,0
decl (Decl
n "reset"
t "std_ulogic"
o 23
suid 55,0
)
declText (MLText
uid 5551,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,400,17500,1300"
st "SIGNAL reset : std_ulogic"
)
)
*17 (Net
uid 5558,0
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 56,0
)
declText (MLText
uid 5559,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,400,17500,1300"
st "SIGNAL clock : std_ulogic"
)
)
*18 (Net
uid 5919,0
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 17
suid 66,0
)
declText (MLText
uid 5920,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-14000,6800,18000,7700"
st "SIGNAL memDataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*19 (Net
uid 5927,0
decl (Decl
n "memDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 18
suid 67,0
)
declText (MLText
uid 5928,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-14000,6800,18000,7700"
st "SIGNAL memDataOut : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*20 (Net
uid 6010,0
decl (Decl
n "memWr_n"
t "std_ulogic"
o 22
suid 71,0
)
declText (MLText
uid 6011,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-14000,6800,3500,7700"
st "SIGNAL memWr_n : std_ulogic"
)
)
*21 (Net
uid 6048,0
decl (Decl
n "DQ"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 75,0
)
declText (MLText
uid 6049,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-14000,6800,17500,7700"
st "SIGNAL DQ : std_logic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*22 (HdlText
uid 6058,0
optionalChildren [
*23 (EmbeddedText
uid 6063,0
commentText (CommentText
uid 6064,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 6065,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "94000,58000,110000,66000"
)
oxt "0,0,18000,5000"
text (MLText
uid 6066,0
va (VaSet
font "courier,9,0"
)
xt "94200,58200,110200,65400"
st "
memDataIn <= std_ulogic_vector(DQ);
DQ <= std_logic_vector(memDataOut) when (memWr_n = '0') or (memWrDelayed_n = '0')
else (others => 'Z');
delayMemWr: process(reset, clock)
begin
if reset = '1' then
memWrDelayed_n <= '0';
elsif rising_edge(clock) then
memWrDelayed_n <= memWr_n;
end if;
end process delayMemWr;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 8000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 6059,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "94000,57000,110000,67000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 6060,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*24 (Text
uid 6061,0
va (VaSet
)
xt "94400,67000,95600,68000"
st "eb1"
blo "94400,67800"
tm "HdlTextNameMgr"
)
*25 (Text
uid 6062,0
va (VaSet
)
xt "94400,68000,94800,69000"
st "1"
blo "94400,68800"
tm "HdlTextNumberMgr"
)
]
)
)
*26 (Net
uid 6768,0
decl (Decl
n "flashCE_n"
t "std_ulogic"
o 7
suid 79,0
)
declText (MLText
uid 6769,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-112000,6600,-94500,7500"
st "SIGNAL flashCE_n : std_ulogic"
)
)
*27 (Net
uid 6780,0
decl (Decl
n "memOE_n"
t "std_ulogic"
o 19
suid 81,0
)
declText (MLText
uid 6781,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-112000,6600,-94500,7500"
st "SIGNAL memOE_n : std_ulogic"
)
)
*28 (Net
uid 6798,0
decl (Decl
n "flashSTS"
t "std_ulogic"
o 13
suid 83,0
)
declText (MLText
uid 6799,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-112000,6600,-94500,7500"
st "SIGNAL flashSTS : std_ulogic"
)
)
*29 (Net
uid 6804,0
decl (Decl
n "BYTE_n"
t "std_ulogic"
o 2
suid 84,0
)
declText (MLText
uid 6805,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-112000,6600,-94500,7500"
st "SIGNAL BYTE_n : std_ulogic"
)
)
*30 (Net
uid 6812,0
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 15
suid 85,0
)
declText (MLText
uid 6813,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "-112000,6600,-78500,7500"
st "SIGNAL memAddress : std_ulogic_vector(addressBitNb-1 DOWNTO 0)"
)
)
*31 (HdlText
uid 6818,0
optionalChildren [
*32 (EmbeddedText
uid 6823,0
commentText (CommentText
uid 6824,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 6825,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "54000,34000,70000,44000"
)
oxt "0,0,18000,5000"
text (MLText
uid 6826,0
va (VaSet
font "courier,9,0"
)
xt "54200,34200,67700,38700"
st "
A <= unsigned(memAddress);
CE <= \"00\" & flashCE_n;
BYTE_n <= '1';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 6819,0
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "54000,33000,70000,45000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 6820,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*33 (Text
uid 6821,0
va (VaSet
)
xt "54400,45000,56000,46000"
st "eb2"
blo "54400,45800"
tm "HdlTextNameMgr"
)
*34 (Text
uid 6822,0
va (VaSet
)
xt "54400,46000,55200,47000"
st "2"
blo "54400,46800"
tm "HdlTextNumberMgr"
)
]
)
)
*35 (Net
uid 6843,0
decl (Decl
n "flashEn"
t "std_ulogic"
o 11
suid 86,0
)
declText (MLText
uid 6844,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashEn : std_ulogic"
)
)
*36 (Net
uid 6922,0
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 10
suid 87,0
)
declText (MLText
uid 6923,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashDataValid : std_ulogic"
)
)
*37 (Net
uid 6930,0
decl (Decl
n "flashRd"
t "std_ulogic"
o 12
suid 88,0
)
declText (MLText
uid 6931,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashRd : std_ulogic"
)
)
*38 (Net
uid 6938,0
decl (Decl
n "flashWr"
t "std_ulogic"
o 14
suid 89,0
)
declText (MLText
uid 6939,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL flashWr : std_ulogic"
)
)
*39 (Net
uid 6946,0
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 9
suid 90,0
)
declText (MLText
uid 6947,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,32000,900"
st "SIGNAL flashDataOut : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*40 (Net
uid 6954,0
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 91,0
)
declText (MLText
uid 6955,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,32000,900"
st "SIGNAL flashDataIn : std_ulogic_vector(dataBitNb-1 DOWNTO 0)"
)
)
*41 (Net
uid 6962,0
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 92,0
)
declText (MLText
uid 6963,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,29000,900"
st "SIGNAL flashAddr : unsigned(addressBitNb-1 DOWNTO 0)"
)
)
*42 (Net
uid 6984,0
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 1
suid 93,0
)
declText (MLText
uid 6985,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,23000,900"
st "SIGNAL A : unsigned(23 DOWNTO 0)"
)
)
*43 (Net
uid 6994,0
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 94,0
)
declText (MLText
uid 6995,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,27000,900"
st "SIGNAL CE : std_ulogic_vector(2 DOWNTO 0)"
)
)
*44 (Net
uid 7044,0
decl (Decl
n "memWrDelayed_n"
t "std_ulogic"
o 21
suid 95,0
)
declText (MLText
uid 7045,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memWrDelayed_n : std_ulogic"
)
)
*45 (Net
uid 7125,0
decl (Decl
n "memRst_n"
t "std_ulogic"
o 20
suid 96,0
)
declText (MLText
uid 7126,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memRst_n : std_ulogic"
)
)
*46 (SaComponent
uid 7294,0
optionalChildren [
*47 (CptPort
uid 7222,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7223,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,74625,46000,75375"
)
tg (CPTG
uid 7224,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7225,0
va (VaSet
)
xt "47000,74500,49100,75500"
st "clock"
blo "47000,75300"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 20,0
)
)
)
*48 (CptPort
uid 7226,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7227,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,66625,46000,67375"
)
tg (CPTG
uid 7228,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7229,0
va (VaSet
)
xt "47000,66500,52700,67500"
st "flashDataValid"
blo "47000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 14
suid 21,0
)
)
)
*49 (CptPort
uid 7230,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7231,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,56625,46000,57375"
)
tg (CPTG
uid 7232,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7233,0
va (VaSet
)
xt "47000,56500,50600,57500"
st "flashAddr"
blo "47000,57300"
)
)
thePort (LogicalPort
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 3
suid 22,0
)
)
)
*50 (CptPort
uid 7234,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7235,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,56625,62750,57375"
)
tg (CPTG
uid 7236,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7237,0
va (VaSet
)
xt "55800,56500,61000,57500"
st "memAddress"
ju 2
blo "61000,57300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "( chipAddressBitNb-1 DOWNTO 0 )"
o 10
suid 23,0
)
)
)
*51 (CptPort
uid 7238,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7239,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,60625,46000,61375"
)
tg (CPTG
uid 7240,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7241,0
va (VaSet
)
xt "47000,60500,52200,61500"
st "flashDataOut"
blo "47000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 24,0
)
)
)
*52 (CptPort
uid 7242,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7243,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,58625,62750,59375"
)
tg (CPTG
uid 7244,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7245,0
va (VaSet
)
xt "56800,58500,61000,59500"
st "memDataIn"
ju 2
blo "61000,59300"
)
)
thePort (LogicalPort
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 2
suid 25,0
)
)
)
*53 (CptPort
uid 7246,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7247,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,60625,62750,61375"
)
tg (CPTG
uid 7248,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7249,0
va (VaSet
)
xt "55800,60500,61000,61500"
st "memDataOut"
ju 2
blo "61000,61300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 11
suid 26,0
)
)
)
*54 (CptPort
uid 7250,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7251,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,64625,62750,65375"
)
tg (CPTG
uid 7252,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7253,0
va (VaSet
)
xt "57200,64500,61000,65500"
st "memWr_n"
ju 2
blo "61000,65300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memWr_n"
t "std_ulogic"
o 12
suid 27,0
)
)
)
*55 (CptPort
uid 7254,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7255,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,72625,46000,73375"
)
tg (CPTG
uid 7256,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7257,0
va (VaSet
)
xt "47000,72500,49900,73500"
st "flashEn"
blo "47000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "flashEn"
t "std_ulogic"
o 5
suid 28,0
)
)
)
*56 (CptPort
uid 7258,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7259,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,62625,46000,63375"
)
tg (CPTG
uid 7260,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7261,0
va (VaSet
)
xt "47000,62500,50000,63500"
st "flashRd"
blo "47000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "flashRd"
t "std_ulogic"
o 6
suid 29,0
)
)
)
*57 (CptPort
uid 7262,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7263,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,64625,46000,65375"
)
tg (CPTG
uid 7264,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7265,0
va (VaSet
)
xt "47000,64500,50000,65500"
st "flashWr"
blo "47000,65300"
)
)
thePort (LogicalPort
decl (Decl
n "flashWr"
t "std_ulogic"
o 7
suid 30,0
)
)
)
*58 (CptPort
uid 7266,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7267,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,76625,46000,77375"
)
tg (CPTG
uid 7268,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7269,0
va (VaSet
)
xt "47000,76500,49100,77500"
st "reset"
blo "47000,77300"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 8
suid 31,0
)
)
)
*59 (CptPort
uid 7270,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7271,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,68625,62750,69375"
)
tg (CPTG
uid 7272,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7273,0
va (VaSet
)
xt "57000,68500,61000,69500"
st "memRst_n"
ju 2
blo "61000,69300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memRst_n"
t "std_ulogic"
o 15
suid 33,0
)
)
)
*60 (CptPort
uid 7274,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7275,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,70625,62750,71375"
)
tg (CPTG
uid 7276,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7277,0
va (VaSet
)
xt "57500,70500,61000,71500"
st "flashSTS"
ju 2
blo "61000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "flashSTS"
t "std_ulogic"
o 16
suid 34,0
)
)
)
*61 (CptPort
uid 7278,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7279,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,62625,62750,63375"
)
tg (CPTG
uid 7280,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7281,0
va (VaSet
)
xt "57100,62500,61000,63500"
st "flashCE_n"
ju 2
blo "61000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashCE_n"
t "std_ulogic"
o 9
suid 35,0
)
)
)
*62 (CptPort
uid 7282,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7283,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,66625,62750,67375"
)
tg (CPTG
uid 7284,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7285,0
va (VaSet
)
xt "57100,66500,61000,67500"
st "memOE_n"
ju 2
blo "61000,67300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "memOE_n"
t "std_ulogic"
o 17
suid 36,0
)
)
)
*63 (CptPort
uid 7286,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7287,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,58625,46000,59375"
)
tg (CPTG
uid 7288,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7289,0
va (VaSet
)
xt "47000,58500,51600,59500"
st "flashDataIn"
blo "47000,59300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 13
suid 42,0
)
)
)
*64 (CptPort
uid 7290,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7291,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,70625,46000,71375"
)
tg (CPTG
uid 7292,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7293,0
va (VaSet
)
xt "47000,70500,52400,71500"
st "memBusEn_n"
blo "47000,71300"
)
)
thePort (LogicalPort
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 18
suid 44,0
)
)
)
]
shape (Rectangle
uid 7295,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "46000,53000,62000,79000"
)
oxt "37000,5000,53000,31000"
ttg (MlTextGroup
uid 7296,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*65 (Text
uid 7297,0
va (VaSet
font "courier,8,1"
)
xt "46550,79500,49850,80500"
st "memory"
blo "46550,80300"
tm "BdLibraryNameMgr"
)
*66 (Text
uid 7298,0
va (VaSet
font "courier,8,1"
)
xt "46550,80500,52950,81500"
st "flashController"
blo "46550,81300"
tm "CptNameMgr"
)
*67 (Text
uid 7299,0
va (VaSet
font "courier,8,1"
)
xt "46550,81500,47550,82500"
st "I0"
blo "46550,82300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7300,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7301,0
text (MLText
uid 7302,0
va (VaSet
font "courier,8,0"
)
xt "46000,83200,71000,85900"
st "addressBitNb = addressBitNb ( positive )
dataBitNb = dataBitNb ( positive )
chipAddressBitNb = addressBitNb ( positive ) "
)
header ""
)
elements [
(GiElement
name "addressBitNb"
type "positive"
value "addressBitNb"
)
(GiElement
name "dataBitNb"
type "positive"
value "dataBitNb"
)
(GiElement
name "chipAddressBitNb"
type "positive"
value "addressBitNb"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*68 (Net
uid 7303,0
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 16
suid 97,0
)
declText (MLText
uid 7304,0
va (VaSet
isHidden 1
font "courier,8,0"
)
xt "0,0,17500,900"
st "SIGNAL memBusEn_n : std_ulogic"
)
)
*69 (SaComponent
uid 7440,0
optionalChildren [
*70 (CptPort
uid 7408,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7409,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,60625,78000,61375"
)
tg (CPTG
uid 7410,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7411,0
va (VaSet
)
xt "79000,60500,79900,61500"
st "A"
blo "79000,61300"
)
)
thePort (LogicalPort
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 45
suid 1,0
)
)
)
*71 (CptPort
uid 7412,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7413,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,68625,78000,69375"
)
tg (CPTG
uid 7414,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7415,0
va (VaSet
)
xt "79000,68500,82200,69500"
st "BYTE_n"
blo "79000,69300"
)
)
thePort (LogicalPort
decl (Decl
n "BYTE_n"
t "std_ulogic"
o 48
suid 2,0
)
)
)
*72 (CptPort
uid 7416,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7417,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,62625,78000,63375"
)
tg (CPTG
uid 7418,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7419,0
va (VaSet
)
xt "79000,62500,80500,63500"
st "CE"
blo "79000,63300"
)
)
thePort (LogicalPort
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 45
suid 3,0
)
)
)
*73 (CptPort
uid 7420,0
ps "OnEdgeStrategy"
shape (Diamond
uid 7421,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "86000,60625,86750,61375"
)
tg (CPTG
uid 7422,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7423,0
va (VaSet
)
xt "83400,60500,85000,61500"
st "DQ"
ju 2
blo "85000,61300"
)
)
thePort (LogicalPort
m 2
decl (Decl
n "DQ"
t "std_logic_vector"
b "(15 DOWNTO 0)"
o 45
suid 4,0
)
)
)
*74 (CptPort
uid 7424,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7425,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,66625,78000,67375"
)
tg (CPTG
uid 7426,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7427,0
va (VaSet
)
xt "79000,66500,81300,67500"
st "OE_n"
blo "79000,67300"
)
)
thePort (LogicalPort
decl (Decl
n "OE_n"
t "std_ulogic"
o 48
suid 5,0
)
)
)
*75 (CptPort
uid 7428,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7429,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,72625,78000,73375"
)
tg (CPTG
uid 7430,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7431,0
va (VaSet
)
xt "79000,72500,81300,73500"
st "RP_n"
blo "79000,73300"
)
)
thePort (LogicalPort
decl (Decl
n "RP_n"
t "std_ulogic"
o 48
suid 6,0
)
)
)
*76 (CptPort
uid 7432,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7433,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "86000,62625,86750,63375"
)
tg (CPTG
uid 7434,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 7435,0
va (VaSet
)
xt "83100,62500,85000,63500"
st "STS"
ju 2
blo "85000,63300"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "STS"
t "std_ulogic"
o 48
suid 7,0
)
)
)
*77 (CptPort
uid 7436,0
ps "OnEdgeStrategy"
shape (Triangle
uid 7437,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "77250,64625,78000,65375"
)
tg (CPTG
uid 7438,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 7439,0
va (VaSet
)
xt "79000,64500,81400,65500"
st "WE_n"
blo "79000,65300"
)
)
thePort (LogicalPort
decl (Decl
n "WE_n"
t "std_ulogic"
o 48
suid 8,0
)
)
)
]
shape (Rectangle
uid 7441,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "78000,57000,86000,75000"
)
oxt "35000,13000,43000,31000"
ttg (MlTextGroup
uid 7442,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*78 (Text
uid 7443,0
va (VaSet
font "courier,8,1"
)
xt "77800,75000,83300,76000"
st "memory_test"
blo "77800,75800"
tm "BdLibraryNameMgr"
)
*79 (Text
uid 7444,0
va (VaSet
font "courier,8,1"
)
xt "77800,76000,84600,77000"
st "flash_28F128J3A"
blo "77800,76800"
tm "CptNameMgr"
)
*80 (Text
uid 7445,0
va (VaSet
font "courier,8,1"
)
xt "77800,77000,78800,78000"
st "I2"
blo "77800,77800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 7446,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 7447,0
text (MLText
uid 7448,0
va (VaSet
font "courier,8,0"
)
xt "78000,78600,112500,86700"
st "fileSpec = \"U:\\ELN_board\\Simulation\\flash.srec\" ( string )
T_W13 = 500 ns ( time )
T_W16_program = 1 us ( time )
T_W16_erase = 1.5 us ( time )
T_R2 = 120 ns ( time )
T_R3 = 120 ns ( time )
T_R7 = 0 ns ( time )
T_R8 = 55 ns ( time )
T_R9 = 15 ns ( time ) "
)
header ""
)
elements [
(GiElement
name "fileSpec"
type "string"
value "\"U:\\ELN_board\\Simulation\\flash.srec\""
)
(GiElement
name "T_W13"
type "time"
value "500 ns"
)
(GiElement
name "T_W16_program"
type "time"
value "1 us"
)
(GiElement
name "T_W16_erase"
type "time"
value "1.5 us"
)
(GiElement
name "T_R2"
type "time"
value "120 ns"
)
(GiElement
name "T_R3"
type "time"
value "120 ns"
)
(GiElement
name "T_R7"
type "time"
value "0 ns"
)
(GiElement
name "T_R8"
type "time"
value "55 ns"
)
(GiElement
name "T_R9"
type "time"
value "15 ns"
)
]
)
portVis (PortSigDisplay
sTC 0
sF 0
)
archFileType "UNKNOWN"
)
*81 (Wire
uid 5552,0
shape (OrthoPolyLine
uid 5553,0
va (VaSet
vasetType 3
)
xt "44000,77000,45250,87000"
pts [
"45250,77000"
"44000,77000"
"44000,87000"
]
)
start &58
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5556,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5557,0
va (VaSet
font "courier,12,0"
)
xt "40250,75600,43750,76900"
st "reset"
blo "40250,76600"
tm "WireNameMgr"
)
)
on &16
)
*82 (Wire
uid 5560,0
shape (OrthoPolyLine
uid 5561,0
va (VaSet
vasetType 3
)
xt "42000,75000,45250,87000"
pts [
"45250,75000"
"42000,75000"
"42000,87000"
]
)
start &47
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5564,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5565,0
va (VaSet
font "courier,12,0"
)
xt "40250,73600,43750,74900"
st "clock"
blo "40250,74600"
tm "WireNameMgr"
)
)
on &17
)
*83 (Wire
uid 5568,0
shape (OrthoPolyLine
uid 5569,0
va (VaSet
vasetType 3
)
xt "40000,73000,45250,87000"
pts [
"45250,73000"
"40000,73000"
"40000,87000"
]
)
start &55
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 5572,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5573,0
va (VaSet
font "courier,12,0"
)
xt "39250,71600,44150,72900"
st "flashEn"
blo "39250,72600"
tm "WireNameMgr"
)
)
on &35
)
*84 (Wire
uid 5921,0
shape (OrthoPolyLine
uid 5922,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,59000,66000,59000"
pts [
"62750,59000"
"66000,59000"
]
)
start &52
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5925,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5926,0
va (VaSet
font "courier,12,0"
)
xt "64750,57600,71050,58900"
st "memDataIn"
blo "64750,58600"
tm "WireNameMgr"
)
)
on &18
)
*85 (Wire
uid 5929,0
shape (OrthoPolyLine
uid 5930,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,61000,66000,61000"
pts [
"62750,61000"
"66000,61000"
]
)
start &53
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 5933,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 5934,0
va (VaSet
font "courier,12,0"
)
xt "64750,59600,72450,60900"
st "memDataOut"
blo "64750,60600"
tm "WireNameMgr"
)
)
on &19
)
*86 (Wire
uid 6050,0
shape (OrthoPolyLine
uid 6051,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "86750,61000,94000,61000"
pts [
"86750,61000"
"94000,61000"
]
)
start &73
end &22
sat 32
eat 4
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6054,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6055,0
va (VaSet
font "courier,12,0"
)
xt "88750,59600,90150,60900"
st "DQ"
blo "88750,60600"
tm "WireNameMgr"
)
)
on &21
)
*87 (Wire
uid 6114,0
shape (OrthoPolyLine
uid 6115,0
va (VaSet
vasetType 3
)
xt "90000,63000,94000,63000"
pts [
"90000,63000"
"94000,63000"
]
)
end &22
sat 16
eat 1
stc 0
st 0
si 0
tg (WTG
uid 6120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6121,0
va (VaSet
font "courier,12,0"
)
xt "87000,61600,91900,62900"
st "memWr_n"
blo "87000,62600"
tm "WireNameMgr"
)
)
on &20
)
*88 (Wire
uid 6122,0
shape (OrthoPolyLine
uid 6123,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,61000,114000,61000"
pts [
"110000,61000"
"114000,61000"
]
)
start &22
sat 2
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6128,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6129,0
va (VaSet
font "courier,12,0"
)
xt "112750,59600,119050,60900"
st "memDataIn"
blo "112750,60600"
tm "WireNameMgr"
)
)
on &18
)
*89 (Wire
uid 6130,0
shape (OrthoPolyLine
uid 6131,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "110000,63000,114000,63000"
pts [
"110000,63000"
"114000,63000"
]
)
start &22
sat 1
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6137,0
va (VaSet
font "courier,12,0"
)
xt "112750,61600,120450,62900"
st "memDataOut"
blo "112750,62600"
tm "WireNameMgr"
)
)
on &19
)
*90 (Wire
uid 6770,0
shape (OrthoPolyLine
uid 6771,0
va (VaSet
vasetType 3
)
xt "62750,63000,66000,63000"
pts [
"62750,63000"
"66000,63000"
]
)
start &61
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6772,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6773,0
va (VaSet
font "courier,12,0"
)
xt "64750,61600,71050,62900"
st "flashCE_n"
blo "64750,62600"
tm "WireNameMgr"
)
)
on &26
)
*91 (Wire
uid 6776,0
shape (OrthoPolyLine
uid 6777,0
va (VaSet
vasetType 3
)
xt "62750,65000,77250,65000"
pts [
"62750,65000"
"77250,65000"
]
)
start &54
end &77
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6778,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6779,0
va (VaSet
font "courier,12,0"
)
xt "64750,63600,69650,64900"
st "memWr_n"
blo "64750,64600"
tm "WireNameMgr"
)
)
on &20
)
*92 (Wire
uid 6782,0
shape (OrthoPolyLine
uid 6783,0
va (VaSet
vasetType 3
)
xt "62750,67000,77250,67000"
pts [
"62750,67000"
"77250,67000"
]
)
start &62
end &74
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6784,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6785,0
va (VaSet
font "courier,12,0"
)
xt "64750,65600,69650,66900"
st "memOE_n"
blo "64750,66600"
tm "WireNameMgr"
)
)
on &27
)
*93 (Wire
uid 6794,0
shape (OrthoPolyLine
uid 6795,0
va (VaSet
vasetType 3
)
xt "62750,69000,77250,73000"
pts [
"62750,69000"
"70000,69000"
"70000,73000"
"77250,73000"
]
)
start &59
end &75
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6796,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6797,0
va (VaSet
font "courier,12,0"
)
xt "64750,67600,70350,68900"
st "memRst_n"
blo "64750,68600"
tm "WireNameMgr"
)
)
on &45
)
*94 (Wire
uid 6800,0
shape (OrthoPolyLine
uid 6801,0
va (VaSet
vasetType 3
)
xt "62750,63000,88000,79000"
pts [
"62750,71000"
"68000,71000"
"68000,79000"
"88000,79000"
"88000,63000"
"86750,63000"
]
)
start &60
end &76
sat 32
eat 32
stc 0
st 0
si 0
tg (WTG
uid 6802,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6803,0
va (VaSet
font "courier,12,0"
)
xt "64750,69600,70350,70900"
st "flashSTS"
blo "64750,70600"
tm "WireNameMgr"
)
)
on &28
)
*95 (Wire
uid 6806,0
shape (OrthoPolyLine
uid 6807,0
va (VaSet
vasetType 3
)
xt "74000,69000,77250,69000"
pts [
"77250,69000"
"74000,69000"
]
)
start &71
sat 32
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6810,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6811,0
va (VaSet
font "courier,12,0"
)
xt "72000,67600,76200,68900"
st "BYTE_n"
blo "72000,68600"
tm "WireNameMgr"
)
)
on &29
)
*96 (Wire
uid 6814,0
shape (OrthoPolyLine
uid 6815,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "62750,57000,66000,57000"
pts [
"62750,57000"
"66000,57000"
]
)
start &50
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6816,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6817,0
va (VaSet
font "courier,12,0"
)
xt "64750,55600,72450,56900"
st "memAddress"
blo "64750,56600"
tm "WireNameMgr"
)
)
on &30
)
*97 (Wire
uid 6827,0
shape (OrthoPolyLine
uid 6828,0
va (VaSet
vasetType 3
)
xt "70000,41000,74000,41000"
pts [
"70000,41000"
"74000,41000"
]
)
start &31
sat 2
eat 16
stc 0
st 0
si 0
tg (WTG
uid 6833,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6834,0
va (VaSet
font "courier,12,0"
)
xt "72000,39600,76200,40900"
st "BYTE_n"
blo "72000,40600"
tm "WireNameMgr"
)
)
on &29
)
*98 (Wire
uid 6924,0
shape (OrthoPolyLine
uid 6925,0
va (VaSet
vasetType 3
)
xt "34000,67000,45250,87000"
pts [
"45250,67000"
"34000,67000"
"34000,87000"
]
)
start &48
end &12
sat 32
eat 1
stc 0
st 0
si 0
tg (WTG
uid 6928,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6929,0
va (VaSet
font "courier,12,0"
)
xt "34000,65600,44500,66900"
st "flashDataValid"
blo "34000,66600"
tm "WireNameMgr"
)
)
on &36
)
*99 (Wire
uid 6932,0
shape (OrthoPolyLine
uid 6933,0
va (VaSet
vasetType 3
)
xt "30000,63000,45250,87000"
pts [
"45250,63000"
"30000,63000"
"30000,87000"
]
)
start &56
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 6936,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6937,0
va (VaSet
font "courier,12,0"
)
xt "38000,61600,42900,62900"
st "flashRd"
blo "38000,62600"
tm "WireNameMgr"
)
)
on &37
)
*100 (Wire
uid 6940,0
shape (OrthoPolyLine
uid 6941,0
va (VaSet
vasetType 3
)
xt "32000,65000,45250,87000"
pts [
"45250,65000"
"32000,65000"
"32000,87000"
]
)
start &57
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 6944,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6945,0
va (VaSet
font "courier,12,0"
)
xt "38250,63600,43150,64900"
st "flashWr"
blo "38250,64600"
tm "WireNameMgr"
)
)
on &38
)
*101 (Wire
uid 6948,0
shape (OrthoPolyLine
uid 6949,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "28000,61000,45250,87000"
pts [
"45250,61000"
"28000,61000"
"28000,87000"
]
)
start &51
end &12
sat 32
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6952,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6953,0
va (VaSet
font "courier,12,0"
)
xt "34250,59600,43350,60900"
st "flashDataOut"
blo "34250,60600"
tm "WireNameMgr"
)
)
on &39
)
*102 (Wire
uid 6956,0
shape (OrthoPolyLine
uid 6957,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "26000,59000,45250,87000"
pts [
"45250,59000"
"26000,59000"
"26000,87000"
]
)
start &63
end &12
sat 32
eat 1
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6960,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6961,0
va (VaSet
font "courier,12,0"
)
xt "35250,57600,43650,58900"
st "flashDataIn"
blo "35250,58600"
tm "WireNameMgr"
)
)
on &40
)
*103 (Wire
uid 6964,0
shape (OrthoPolyLine
uid 6965,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "24000,57000,45250,87000"
pts [
"45250,57000"
"24000,57000"
"24000,87000"
]
)
start &49
end &12
sat 32
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6968,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6969,0
va (VaSet
font "courier,12,0"
)
xt "37250,55600,43550,56900"
st "flashAddr"
blo "37250,56600"
tm "WireNameMgr"
)
)
on &41
)
*104 (Wire
uid 6986,0
shape (OrthoPolyLine
uid 6987,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "74000,61000,77250,61000"
pts [
"77250,61000"
"74000,61000"
]
)
start &70
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 6990,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 6991,0
va (VaSet
font "courier,12,0"
)
xt "74250,59600,74950,60900"
st "A"
blo "74250,60600"
tm "WireNameMgr"
)
)
on &42
)
*105 (Wire
uid 6996,0
shape (OrthoPolyLine
uid 6997,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "74000,63000,77250,63000"
pts [
"77250,63000"
"74000,63000"
]
)
start &72
sat 32
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7000,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7001,0
va (VaSet
font "courier,12,0"
)
xt "73250,61600,74650,62900"
st "CE"
blo "73250,62600"
tm "WireNameMgr"
)
)
on &43
)
*106 (Wire
uid 7002,0
shape (OrthoPolyLine
uid 7003,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "50000,37000,54000,37000"
pts [
"54000,37000"
"50000,37000"
]
)
start &31
sat 1
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7008,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7009,0
va (VaSet
font "courier,12,0"
)
xt "45000,35600,52700,36900"
st "memAddress"
blo "45000,36600"
tm "WireNameMgr"
)
)
on &30
)
*107 (Wire
uid 7010,0
shape (OrthoPolyLine
uid 7011,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,37000,74250,37000"
pts [
"74250,37000"
"70000,37000"
]
)
end &31
sat 16
eat 2
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7016,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7017,0
va (VaSet
font "courier,12,0"
)
xt "72000,35600,72700,36900"
st "A"
blo "72000,36600"
tm "WireNameMgr"
)
)
on &42
)
*108 (Wire
uid 7018,0
shape (OrthoPolyLine
uid 7019,0
va (VaSet
vasetType 3
)
xt "50000,39000,54000,39000"
pts [
"54000,39000"
"50000,39000"
]
)
start &31
sat 1
eat 16
stc 0
st 0
si 0
tg (WTG
uid 7024,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7025,0
va (VaSet
font "courier,12,0"
)
xt "47000,37600,53300,38900"
st "flashCE_n"
blo "47000,38600"
tm "WireNameMgr"
)
)
on &26
)
*109 (Wire
uid 7026,0
shape (OrthoPolyLine
uid 7027,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "70000,39000,74000,39000"
pts [
"70000,39000"
"74000,39000"
]
)
start &31
sat 2
eat 16
sty 1
stc 0
st 0
si 0
tg (WTG
uid 7032,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7033,0
va (VaSet
font "courier,12,0"
)
xt "72000,37600,73400,38900"
st "CE"
blo "72000,38600"
tm "WireNameMgr"
)
)
on &43
)
*110 (Wire
uid 7036,0
shape (OrthoPolyLine
uid 7037,0
va (VaSet
vasetType 3
)
xt "102000,67000,102000,69000"
pts [
"102000,69000"
"102000,67000"
]
)
end &22
sat 16
eat 4
stc 0
st 0
si 0
tg (WTG
uid 7042,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7043,0
va (VaSet
font "courier,12,0"
)
xt "99000,67600,109500,68900"
st "memWrDelayed_n"
blo "99000,68600"
tm "WireNameMgr"
)
)
on &44
)
*111 (Wire
uid 7305,0
shape (OrthoPolyLine
uid 7306,0
va (VaSet
vasetType 3
)
xt "38000,71000,45250,87000"
pts [
"45250,71000"
"38000,71000"
"38000,87000"
]
)
start &64
end &12
sat 32
eat 2
stc 0
st 0
si 0
tg (WTG
uid 7309,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 7310,0
va (VaSet
font "courier,12,0"
)
xt "36000,69600,43700,70900"
st "memBusEn_n"
blo "36000,70600"
tm "WireNameMgr"
)
)
on &68
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "32768,32768,32768"
)
packageList *112 (PackageList
uid 187,0
stg "VerticalLayoutStrategy"
textVec [
*113 (Text
uid 1297,0
va (VaSet
font "courier,12,0"
)
xt "-7000,19600,2500,21000"
st "Package List"
blo "-7000,20800"
)
*114 (MLText
uid 1298,0
va (VaSet
)
xt "-7000,21000,11600,24000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 190,0
stg "VerticalLayoutStrategy"
textVec [
*115 (Text
uid 191,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,0,31000,1200"
st "Compiler Directives"
blo "20000,1000"
)
*116 (Text
uid 192,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,1400,33000,2600"
st "Pre-module directives:"
blo "20000,2400"
)
*117 (MLText
uid 193,0
va (VaSet
isHidden 1
)
xt "20000,2800,32000,4800"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*118 (Text
uid 194,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,5600,33500,6800"
st "Post-module directives:"
blo "20000,6600"
)
*119 (MLText
uid 195,0
va (VaSet
isHidden 1
)
xt "20000,7000,20000,7000"
tm "BdCompilerDirectivesTextMgr"
)
*120 (Text
uid 196,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "20000,7200,33200,8400"
st "End-module directives:"
blo "20000,8200"
)
*121 (MLText
uid 197,0
va (VaSet
isHidden 1
)
xt "20000,1200,20000,1200"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "7,31,1388,937"
viewArea "-9065,17500,147962,124527"
cachedDiagramExtent "-112000,0,140000,118000"
pageSetupInfo (PageSetupInfo
ptrCmd "\\\\SUN\\PREA309_HPLJ3005DN.PRINTERS.SYSTEM.SION.HEVs,winspool,"
fileName "\\\\EIV\\a309_hplj4050.electro.eiv"
toPrinter 1
xMargin 48
yMargin 48
windowsPaperWidth 761
windowsPaperHeight 1077
paperType "Letter (8.5\" x 11\")"
windowsPaperName "A4"
windowsPaperType 9
scale 50
titlesVisible 0
exportedDirectories [
"$HDS_PROJECT_DIR/HTMLExport"
]
boundaryWidth 0
)
hasePageBreakOrigin 1
pageBreakOrigin "-7000,19000"
lastUid 7638,0
defaultCommentText (CommentText
shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
lineColor "0,0,32768"
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "200,200,2600,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
font "courier,8,0"
)
xt "450,2150,1450,3050"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
)
xt "1000,1000,3300,2000"
st "Panel0"
blo "1000,1800"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "39936,56832,65280"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*122 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,2550,7900,3950"
st "<library>"
blo "1500,3750"
tm "BdLibraryNameMgr"
)
*123 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,3950,7000,5350"
st "<block>"
blo "1500,5150"
tm "BlkNameMgr"
)
*124 (Text
va (VaSet
font "courier,12,1"
)
xt "1500,5350,3000,6750"
st "I0"
blo "1500,6550"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "1500,12550,1500,12550"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-600,0,8600,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*125 (Text
va (VaSet
)
xt "-100,3000,2200,4000"
st "Library"
blo "-100,3800"
)
*126 (Text
va (VaSet
)
xt "-100,4000,5900,5000"
st "MWComponent"
blo "-100,4800"
)
*127 (Text
va (VaSet
)
xt "-100,5000,500,6000"
st "I0"
blo "-100,5800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7100,1000,-7100,1000"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-850,0,8850,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*128 (Text
va (VaSet
)
xt "-350,2550,1950,3550"
st "Library"
blo "-350,3350"
tm "BdLibraryNameMgr"
)
*129 (Text
va (VaSet
)
xt "-350,3550,5150,4550"
st "SaComponent"
blo "-350,4350"
tm "CptNameMgr"
)
*130 (Text
va (VaSet
)
xt "-350,4550,250,5550"
st "I0"
blo "-350,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7350,550,-7350,550"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-1350,0,9350,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*131 (Text
va (VaSet
)
xt "-850,2550,1450,3550"
st "Library"
blo "-850,3350"
)
*132 (Text
va (VaSet
)
xt "-850,3550,5250,4550"
st "VhdlComponent"
blo "-850,4350"
)
*133 (Text
va (VaSet
)
xt "-850,4550,-250,5550"
st "I0"
blo "-850,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-7850,550,-7850,550"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "-2100,0,10100,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*134 (Text
va (VaSet
)
xt "-1600,2550,700,3550"
st "Library"
blo "-1600,3350"
)
*135 (Text
va (VaSet
)
xt "-1600,3550,5500,4550"
st "VerilogComponent"
blo "-1600,4350"
)
*136 (Text
va (VaSet
)
xt "-1600,4550,-1000,5550"
st "I0"
blo "-1600,5350"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
font "courier,9,0"
)
xt "-8600,550,-8600,550"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,37120"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*137 (Text
va (VaSet
)
xt "2950,3400,4150,4400"
st "eb1"
blo "2950,4200"
tm "HdlTextNameMgr"
)
*138 (Text
va (VaSet
)
xt "2950,4400,3350,5400"
st "1"
blo "2950,5200"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
font "courier,9,0"
)
xt "200,200,2200,1100"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "-2875,-375,-2875,-375"
ju 2
blo "-2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "2875,-375,2875,-375"
blo "2875,-375"
tm "SignalTypeMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
)
xt "3000,500,3000,500"
blo "3000,500"
tm "WireNameMgr"
)
s (Text
va (VaSet
)
xt "3000,500,3000,500"
blo "3000,500"
tm "SignalTypeMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineColor "32768,0,0"
lineStyle 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
font "courier,12,0"
)
xt "0,0,5100,1400"
st "bundle0"
blo "0,1200"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
font "courier,12,0"
)
xt "0,1400,1400,2700"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
font "courier,12,0"
)
xt "0,0,6300,1300"
st "Auto list"
)
second (MLText
va (VaSet
font "courier,12,0"
)
xt "0,1400,12600,2700"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 2
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,17400,-400"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*139 (Text
va (VaSet
font "courier,9,1"
)
xt "11800,20000,22600,21200"
st "Frame Declarations"
blo "11800,21000"
)
*140 (MLText
va (VaSet
)
xt "11800,21200,11800,21200"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "26368,26368,26368"
lineStyle 1
lineWidth 2
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1400,10800,-400"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1750"
)
num (Text
va (VaSet
)
xt "200,300,600,1300"
st "1"
blo "200,1100"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*141 (Text
va (VaSet
font "courier,9,1"
)
xt "11800,20000,22600,21200"
st "Frame Declarations"
blo "11800,21000"
)
*142 (MLText
va (VaSet
)
xt "11800,21200,11800,21200"
tm "BdFrameDeclTextMgr"
)
]
)
style 3
)
defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,750,2600,2150"
st "Port"
blo "0,1950"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
font "courier,12,0"
)
xt "0,750,2600,2150"
st "Port"
blo "0,1950"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
isHidden 1
font "courier,8,0"
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "courier,10,1"
)
xt "-7000,26200,1600,27400"
st "Declarations"
blo "-7000,27200"
)
portLabel (Text
uid 3,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,-2800,28600"
st "Ports:"
blo "-7000,28400"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "courier,10,1"
)
xt "-7000,27400,-1000,28600"
st "Pre User:"
blo "-7000,28400"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "-5000,28600,18400,30600"
st "constant addressBitNb: positive := 24;
constant dataBitNb: positive := 16;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,4000,28600"
st "Diagram Signals:"
blo "-7000,28400"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "courier,10,1"
)
xt "-7000,27400,300,28600"
st "Post User:"
blo "-7000,28400"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "-5000,41800,-5000,41800"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 97,0
usingSuid 1
emptyRow *143 (LEmptyRow
)
uid 3310,0
optionalChildren [
*144 (RefLabelRowHdr
)
*145 (TitleRowHdr
)
*146 (FilterRowHdr
)
*147 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*148 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*149 (GroupColHdr
tm "GroupColHdrMgr"
)
*150 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*151 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*152 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*153 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*154 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*155 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*156 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 23
suid 55,0
)
)
uid 5622,0
)
*157 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 5
suid 56,0
)
)
uid 5624,0
)
*158 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 17
suid 66,0
)
)
uid 5939,0
)
*159 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 18
suid 67,0
)
)
uid 5941,0
)
*160 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWr_n"
t "std_ulogic"
o 22
suid 71,0
)
)
uid 6040,0
)
*161 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "DQ"
t "std_logic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 4
suid 75,0
)
)
uid 6056,0
)
*162 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashCE_n"
t "std_ulogic"
o 7
suid 79,0
)
)
uid 6786,0
)
*163 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memOE_n"
t "std_ulogic"
o 19
suid 81,0
)
)
uid 6790,0
)
*164 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashSTS"
t "std_ulogic"
o 13
suid 83,0
)
)
uid 6837,0
)
*165 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "BYTE_n"
t "std_ulogic"
o 2
suid 84,0
)
)
uid 6839,0
)
*166 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memAddress"
t "std_ulogic_vector"
b "(addressBitNb-1 DOWNTO 0)"
o 15
suid 85,0
)
)
uid 6841,0
)
*167 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashEn"
t "std_ulogic"
o 11
suid 86,0
)
)
uid 6970,0
)
*168 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataValid"
t "std_ulogic"
o 10
suid 87,0
)
)
uid 6972,0
)
*169 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashRd"
t "std_ulogic"
o 12
suid 88,0
)
)
uid 6974,0
)
*170 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashWr"
t "std_ulogic"
o 14
suid 89,0
)
)
uid 6976,0
)
*171 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataOut"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 9
suid 90,0
)
)
uid 6978,0
)
*172 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashDataIn"
t "std_ulogic_vector"
b "(dataBitNb-1 DOWNTO 0)"
o 8
suid 91,0
)
)
uid 6980,0
)
*173 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "flashAddr"
t "unsigned"
b "(addressBitNb-1 DOWNTO 0)"
o 6
suid 92,0
)
)
uid 6982,0
)
*174 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "A"
t "unsigned"
b "(23 DOWNTO 0)"
o 1
suid 93,0
)
)
uid 6992,0
)
*175 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "CE"
t "std_ulogic_vector"
b "(2 DOWNTO 0)"
o 3
suid 94,0
)
)
uid 7034,0
)
*176 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memWrDelayed_n"
t "std_ulogic"
o 21
suid 95,0
)
)
uid 7046,0
)
*177 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memRst_n"
t "std_ulogic"
o 20
suid 96,0
)
)
uid 7127,0
)
*178 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "memBusEn_n"
t "std_ulogic"
o 16
suid 97,0
)
)
uid 7311,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 3323,0
optionalChildren [
*179 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *180 (MRCItem
litem &143
pos 23
dimension 20
)
uid 3325,0
optionalChildren [
*181 (MRCItem
litem &144
pos 0
dimension 20
uid 3326,0
)
*182 (MRCItem
litem &145
pos 1
dimension 23
uid 3327,0
)
*183 (MRCItem
litem &146
pos 2
hidden 1
dimension 20
uid 3328,0
)
*184 (MRCItem
litem &156
pos 0
dimension 20
uid 5623,0
)
*185 (MRCItem
litem &157
pos 1
dimension 20
uid 5625,0
)
*186 (MRCItem
litem &158
pos 2
dimension 20
uid 5940,0
)
*187 (MRCItem
litem &159
pos 3
dimension 20
uid 5942,0
)
*188 (MRCItem
litem &160
pos 4
dimension 20
uid 6041,0
)
*189 (MRCItem
litem &161
pos 5
dimension 20
uid 6057,0
)
*190 (MRCItem
litem &162
pos 6
dimension 20
uid 6787,0
)
*191 (MRCItem
litem &163
pos 7
dimension 20
uid 6791,0
)
*192 (MRCItem
litem &164
pos 8
dimension 20
uid 6838,0
)
*193 (MRCItem
litem &165
pos 9
dimension 20
uid 6840,0
)
*194 (MRCItem
litem &166
pos 10
dimension 20
uid 6842,0
)
*195 (MRCItem
litem &167
pos 11
dimension 20
uid 6971,0
)
*196 (MRCItem
litem &168
pos 12
dimension 20
uid 6973,0
)
*197 (MRCItem
litem &169
pos 13
dimension 20
uid 6975,0
)
*198 (MRCItem
litem &170
pos 14
dimension 20
uid 6977,0
)
*199 (MRCItem
litem &171
pos 15
dimension 20
uid 6979,0
)
*200 (MRCItem
litem &172
pos 16
dimension 20
uid 6981,0
)
*201 (MRCItem
litem &173
pos 17
dimension 20
uid 6983,0
)
*202 (MRCItem
litem &174
pos 18
dimension 20
uid 6993,0
)
*203 (MRCItem
litem &175
pos 19
dimension 20
uid 7035,0
)
*204 (MRCItem
litem &176
pos 20
dimension 20
uid 7047,0
)
*205 (MRCItem
litem &177
pos 21
dimension 20
uid 7128,0
)
*206 (MRCItem
litem &178
pos 22
dimension 20
uid 7312,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 3329,0
optionalChildren [
*207 (MRCItem
litem &147
pos 0
dimension 20
uid 3330,0
)
*208 (MRCItem
litem &149
pos 1
dimension 50
uid 3331,0
)
*209 (MRCItem
litem &150
pos 2
dimension 100
uid 3332,0
)
*210 (MRCItem
litem &151
pos 3
dimension 50
uid 3333,0
)
*211 (MRCItem
litem &152
pos 4
dimension 100
uid 3334,0
)
*212 (MRCItem
litem &153
pos 5
dimension 100
uid 3335,0
)
*213 (MRCItem
litem &154
pos 6
dimension 50
uid 3336,0
)
*214 (MRCItem
litem &155
pos 7
dimension 80
uid 3337,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 3324,0
vaOverrides [
]
)
]
)
uid 3309,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *215 (LEmptyRow
)
uid 3339,0
optionalChildren [
*216 (RefLabelRowHdr
)
*217 (TitleRowHdr
)
*218 (FilterRowHdr
)
*219 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*220 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*221 (GroupColHdr
tm "GroupColHdrMgr"
)
*222 (NameColHdr
tm "GenericNameColHdrMgr"
)
*223 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*224 (InitColHdr
tm "GenericValueColHdrMgr"
)
*225 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*226 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 3351,0
optionalChildren [
*227 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "courier,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "courier,10,0"
)
emptyMRCItem *228 (MRCItem
litem &215
pos 0
dimension 20
)
uid 3353,0
optionalChildren [
*229 (MRCItem
litem &216
pos 0
dimension 20
uid 3354,0
)
*230 (MRCItem
litem &217
pos 1
dimension 23
uid 3355,0
)
*231 (MRCItem
litem &218
pos 2
hidden 1
dimension 20
uid 3356,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "courier,10,0"
textAngle 90
)
uid 3357,0
optionalChildren [
*232 (MRCItem
litem &219
pos 0
dimension 20
uid 3358,0
)
*233 (MRCItem
litem &221
pos 1
dimension 50
uid 3359,0
)
*234 (MRCItem
litem &222
pos 2
dimension 100
uid 3360,0
)
*235 (MRCItem
litem &223
pos 3
dimension 100
uid 3361,0
)
*236 (MRCItem
litem &224
pos 4
dimension 50
uid 3362,0
)
*237 (MRCItem
litem &225
pos 5
dimension 50
uid 3363,0
)
*238 (MRCItem
litem &226
pos 6
dimension 80
uid 3364,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 3352,0
vaOverrides [
]
)
]
)
uid 3338,0
type 1
)
activeModelName "BlockDiag"
)
Reference in New Issue View Git Blame Copy Permalink