mirror of
https://github.com/Klagarge/Cursor.git
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4175 lines
50 KiB
Plaintext
4175 lines
50 KiB
Plaintext
DocumentHdrVersion "1.1"
|
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Header (DocumentHdr
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version 2
|
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dialect 11
|
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dmPackageRefs [
|
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(DmPackageRef
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library "ieee"
|
||
unitName "std_logic_1164"
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)
|
||
(DmPackageRef
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||
library "ieee"
|
||
unitName "numeric_std"
|
||
)
|
||
]
|
||
instances [
|
||
(Instance
|
||
name "I_tester"
|
||
duLibraryName "Cursor_test"
|
||
duName "cursor_tester"
|
||
elements [
|
||
]
|
||
mwi 0
|
||
uid 1774,0
|
||
)
|
||
(Instance
|
||
name "I_DUT"
|
||
duLibraryName "Cursor"
|
||
duName "cursorCircuit"
|
||
elements [
|
||
(GiElement
|
||
name "position0"
|
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type "positive"
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value "position0"
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)
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(GiElement
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name "position1"
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type "positive"
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value "position1"
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)
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(GiElement
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name "position2"
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type "positive"
|
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value "position2"
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)
|
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(GiElement
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name "slopeShiftBitNb"
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type "positive"
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value "slopeShiftBitNb"
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)
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(GiElement
|
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name "pwmBitNb"
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type "positive"
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value "pwmBitNb"
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)
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(GiElement
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name "testLineNb"
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type "positive"
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value "0"
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)
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]
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mwi 0
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uid 5729,0
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)
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]
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libraryRefs [
|
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"ieee"
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]
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)
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version "32.1"
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appVersion "2019.2 (Build 5)"
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noEmbeddedEditors 1
|
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model (BlockDiag
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||
VExpander (VariableExpander
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vvMap [
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(vvPair
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variable " "
|
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value " "
|
||
)
|
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(vvPair
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variable "HDLDir"
|
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hdl"
|
||
)
|
||
(vvPair
|
||
variable "HDSDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
|
||
)
|
||
(vvPair
|
||
variable "SideDataDesignDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.info"
|
||
)
|
||
(vvPair
|
||
variable "SideDataUserDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd.user"
|
||
)
|
||
(vvPair
|
||
variable "SourceDir"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds"
|
||
)
|
||
(vvPair
|
||
variable "appl"
|
||
value "HDL Designer"
|
||
)
|
||
(vvPair
|
||
variable "arch_name"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "concat_file"
|
||
value "concatenated"
|
||
)
|
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(vvPair
|
||
variable "config"
|
||
value "%(unit)_%(view)_config"
|
||
)
|
||
(vvPair
|
||
variable "d"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
|
||
)
|
||
(vvPair
|
||
variable "d_logical"
|
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value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb"
|
||
)
|
||
(vvPair
|
||
variable "date"
|
||
value "21.12.2021"
|
||
)
|
||
(vvPair
|
||
variable "day"
|
||
value "mar."
|
||
)
|
||
(vvPair
|
||
variable "day_long"
|
||
value "mardi"
|
||
)
|
||
(vvPair
|
||
variable "dd"
|
||
value "21"
|
||
)
|
||
(vvPair
|
||
variable "designName"
|
||
value "$DESIGN_NAME"
|
||
)
|
||
(vvPair
|
||
variable "entity_name"
|
||
value "cursor_tb"
|
||
)
|
||
(vvPair
|
||
variable "ext"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "f"
|
||
value "struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "f_logical"
|
||
value "struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "f_noext"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_author"
|
||
value "remi"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_date"
|
||
value "21.12.2021"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_group"
|
||
value "UNKNOWN"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_host"
|
||
value "MARVIN"
|
||
)
|
||
(vvPair
|
||
variable "graphical_source_time"
|
||
value "14:45:58"
|
||
)
|
||
(vvPair
|
||
variable "group"
|
||
value "UNKNOWN"
|
||
)
|
||
(vvPair
|
||
variable "host"
|
||
value "MARVIN"
|
||
)
|
||
(vvPair
|
||
variable "language"
|
||
value "VHDL"
|
||
)
|
||
(vvPair
|
||
variable "library"
|
||
value "Cursor_test"
|
||
)
|
||
(vvPair
|
||
variable "library_downstream_ModelSim"
|
||
value "D:\\Users\\ELN_labs\\VHDL_comp"
|
||
)
|
||
(vvPair
|
||
variable "library_downstream_ModelSimCompiler"
|
||
value "$SCRATCH_DIR/Cursor_test/work"
|
||
)
|
||
(vvPair
|
||
variable "mm"
|
||
value "12"
|
||
)
|
||
(vvPair
|
||
variable "module_name"
|
||
value "cursor_tb"
|
||
)
|
||
(vvPair
|
||
variable "month"
|
||
value "d<>c."
|
||
)
|
||
(vvPair
|
||
variable "month_long"
|
||
value "d<>cembre"
|
||
)
|
||
(vvPair
|
||
variable "p"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "p_logical"
|
||
value "C:\\Users\\remi\\OneDrive\\Documents\\Cours\\05-HEVS\\S1fb\\electricity\\1-EIN\\project\\cursor\\HDLdesigner\\Cursor\\Prefs\\..\\Cursor_test\\hds\\cursor_tb\\struct.bd"
|
||
)
|
||
(vvPair
|
||
variable "package_name"
|
||
value "<Undefined Variable>"
|
||
)
|
||
(vvPair
|
||
variable "project_name"
|
||
value "hds"
|
||
)
|
||
(vvPair
|
||
variable "series"
|
||
value "HDL Designer Series"
|
||
)
|
||
(vvPair
|
||
variable "task_ADMS"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_DesignCompilerPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_HDSPath"
|
||
value "$HDS_HOME"
|
||
)
|
||
(vvPair
|
||
variable "task_ISEBinPath"
|
||
value "$ISE_HOME"
|
||
)
|
||
(vvPair
|
||
variable "task_ISEPath"
|
||
value "$SCRATCH_DIR\\$DESIGN_NAME\\Board\\ise"
|
||
)
|
||
(vvPair
|
||
variable "task_LeonardoPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_ModelSimPath"
|
||
value "/usr/opt/Modelsim/modeltech/bin"
|
||
)
|
||
(vvPair
|
||
variable "task_NC"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_NC-SimPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_PrecisionRTLPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_QuestaSimPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "task_VCSPath"
|
||
value "<TBD>"
|
||
)
|
||
(vvPair
|
||
variable "this_ext"
|
||
value "bd"
|
||
)
|
||
(vvPair
|
||
variable "this_file"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "this_file_logical"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "time"
|
||
value "14:45:58"
|
||
)
|
||
(vvPair
|
||
variable "unit"
|
||
value "cursor_tb"
|
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)
|
||
(vvPair
|
||
variable "user"
|
||
value "remi"
|
||
)
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||
(vvPair
|
||
variable "version"
|
||
value "2019.2 (Build 5)"
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)
|
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(vvPair
|
||
variable "view"
|
||
value "struct"
|
||
)
|
||
(vvPair
|
||
variable "year"
|
||
value "2021"
|
||
)
|
||
(vvPair
|
||
variable "yy"
|
||
value "21"
|
||
)
|
||
]
|
||
)
|
||
LanguageMgr "Vhdl2008LangMgr"
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||
uid 198,0
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optionalChildren [
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uid 1315,0
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decl (Decl
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uid 1325,0
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decl (Decl
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uid 1487,0
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fg "0,65535,0"
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)
|
||
xt "38250,40625,39000,41375"
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)
|
||
tg (CPTG
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||
uid 5661,0
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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uid 5662,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "40000,40300,43200,41700"
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st "go1"
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||
blo "40000,41500"
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||
)
|
||
)
|
||
thePort (LogicalPort
|
||
decl (Decl
|
||
n "go1"
|
||
t "std_uLogic"
|
||
o 6
|
||
suid 9,0
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||
)
|
||
)
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||
)
|
||
*40 (CptPort
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||
uid 5664,0
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ps "OnEdgeStrategy"
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||
shape (Triangle
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uid 5665,0
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ro 90
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va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "55000,42625,55750,43375"
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)
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tg (CPTG
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||
uid 5666,0
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ps "CptPortTextPlaceStrategy"
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stg "RightVerticalLayoutStrategy"
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f (Text
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uid 5667,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "49800,42400,54000,43800"
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st "side2"
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ju 2
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||
blo "54000,43600"
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)
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||
)
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||
thePort (LogicalPort
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||
m 1
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||
decl (Decl
|
||
n "side2"
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||
t "std_uLogic"
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||
o 20
|
||
suid 10,0
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||
)
|
||
)
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||
)
|
||
*41 (CptPort
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||
uid 5669,0
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||
ps "OnEdgeStrategy"
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||
shape (Triangle
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||
uid 5670,0
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ro 270
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||
va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "55000,48625,55750,49375"
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)
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tg (CPTG
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||
uid 5671,0
|
||
ps "CptPortTextPlaceStrategy"
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||
stg "RightVerticalLayoutStrategy"
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||
f (Text
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||
uid 5672,0
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va (VaSet
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font "Verdana,12,0"
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)
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xt "48100,48300,54000,49700"
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st "sensor2"
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||
ju 2
|
||
blo "54000,49500"
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)
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||
)
|
||
thePort (LogicalPort
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||
decl (Decl
|
||
n "sensor2"
|
||
t "std_uLogic"
|
||
o 11
|
||
suid 11,0
|
||
)
|
||
)
|
||
)
|
||
*42 (CptPort
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||
uid 5674,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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uid 5675,0
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ro 90
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||
va (VaSet
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vasetType 1
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fg "0,65535,0"
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)
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xt "55000,38625,55750,39375"
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)
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||
tg (CPTG
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||
uid 5676,0
|
||
ps "CptPortTextPlaceStrategy"
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||
stg "RightVerticalLayoutStrategy"
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||
f (Text
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uid 5677,0
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va (VaSet
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||
font "Verdana,12,0"
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)
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xt "47700,38400,54000,39800"
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st "motorOn"
|
||
ju 2
|
||
blo "54000,39600"
|
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)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "motorOn"
|
||
t "std_uLogic"
|
||
o 18
|
||
suid 12,0
|
||
)
|
||
)
|
||
)
|
||
*43 (CptPort
|
||
uid 5679,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5680,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
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||
fg "0,65535,0"
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||
)
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||
xt "55000,52625,55750,53375"
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)
|
||
tg (CPTG
|
||
uid 5681,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "RightVerticalLayoutStrategy"
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||
f (Text
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||
uid 5682,0
|
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va (VaSet
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||
font "Verdana,12,0"
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)
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xt "47300,52400,54000,53800"
|
||
st "encoderA"
|
||
ju 2
|
||
blo "54000,53600"
|
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)
|
||
)
|
||
thePort (LogicalPort
|
||
decl (Decl
|
||
n "encoderA"
|
||
t "std_uLogic"
|
||
o 3
|
||
suid 13,0
|
||
)
|
||
)
|
||
)
|
||
*44 (CptPort
|
||
uid 5684,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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uid 5685,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
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||
)
|
||
xt "55000,54625,55750,55375"
|
||
)
|
||
tg (CPTG
|
||
uid 5686,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "RightVerticalLayoutStrategy"
|
||
f (Text
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uid 5687,0
|
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va (VaSet
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||
font "Verdana,12,0"
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)
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xt "47300,54400,54000,55800"
|
||
st "encoderB"
|
||
ju 2
|
||
blo "54000,55600"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
decl (Decl
|
||
n "encoderB"
|
||
t "std_uLogic"
|
||
o 4
|
||
suid 14,0
|
||
)
|
||
)
|
||
)
|
||
*45 (CptPort
|
||
uid 5689,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5690,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
|
||
)
|
||
xt "55000,56625,55750,57375"
|
||
)
|
||
tg (CPTG
|
||
uid 5691,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "RightVerticalLayoutStrategy"
|
||
f (Text
|
||
uid 5692,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
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||
)
|
||
xt "47600,56400,54000,57800"
|
||
st "encoderI"
|
||
ju 2
|
||
blo "54000,57600"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
decl (Decl
|
||
n "encoderI"
|
||
t "std_uLogic"
|
||
o 5
|
||
suid 15,0
|
||
)
|
||
)
|
||
)
|
||
*46 (CptPort
|
||
uid 5694,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
|
||
uid 5695,0
|
||
ro 90
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
|
||
)
|
||
xt "38250,44625,39000,45375"
|
||
)
|
||
tg (CPTG
|
||
uid 5696,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
|
||
uid 5697,0
|
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va (VaSet
|
||
font "Verdana,12,0"
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||
)
|
||
xt "40000,44300,45800,45700"
|
||
st "button4"
|
||
blo "40000,45500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
lang 11
|
||
decl (Decl
|
||
n "button4"
|
||
t "std_ulogic"
|
||
o 1
|
||
suid 16,0
|
||
)
|
||
)
|
||
)
|
||
*47 (CptPort
|
||
uid 5699,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5700,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
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||
)
|
||
xt "38250,48625,39000,49375"
|
||
)
|
||
tg (CPTG
|
||
uid 5701,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
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||
uid 5702,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
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)
|
||
xt "40000,48300,44900,49700"
|
||
st "CS1_n"
|
||
blo "40000,49500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "CS1_n"
|
||
t "std_ulogic"
|
||
o 14
|
||
suid 2017,0
|
||
)
|
||
)
|
||
)
|
||
*48 (CptPort
|
||
uid 5704,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5705,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
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||
)
|
||
xt "38250,50625,39000,51375"
|
||
)
|
||
tg (CPTG
|
||
uid 5706,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
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||
uid 5707,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
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||
)
|
||
xt "40000,50300,43200,51700"
|
||
st "SCL"
|
||
blo "40000,51500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "SCL"
|
||
t "std_ulogic"
|
||
o 16
|
||
suid 2018,0
|
||
)
|
||
)
|
||
)
|
||
*49 (CptPort
|
||
uid 5709,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5710,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
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||
)
|
||
xt "38250,52625,39000,53375"
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)
|
||
tg (CPTG
|
||
uid 5711,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
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||
uid 5712,0
|
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va (VaSet
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||
font "Verdana,12,0"
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)
|
||
xt "40000,52300,42100,53700"
|
||
st "SI"
|
||
blo "40000,53500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "SI"
|
||
t "std_ulogic"
|
||
o 17
|
||
suid 2019,0
|
||
)
|
||
)
|
||
)
|
||
*50 (CptPort
|
||
uid 5714,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5715,0
|
||
ro 270
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
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)
|
||
xt "38250,54625,39000,55375"
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)
|
||
tg (CPTG
|
||
uid 5716,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
|
||
uid 5717,0
|
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va (VaSet
|
||
font "Verdana,12,0"
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)
|
||
xt "40000,54300,42400,55700"
|
||
st "A0"
|
||
blo "40000,55500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "A0"
|
||
t "std_ulogic"
|
||
o 13
|
||
suid 2020,0
|
||
)
|
||
)
|
||
)
|
||
*51 (CptPort
|
||
uid 5719,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5720,0
|
||
ro 270
|
||
va (VaSet
|
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vasetType 1
|
||
fg "0,65535,0"
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)
|
||
xt "38250,56625,39000,57375"
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)
|
||
tg (CPTG
|
||
uid 5721,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
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uid 5722,0
|
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va (VaSet
|
||
font "Verdana,12,0"
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)
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xt "40000,56300,44700,57700"
|
||
st "RST_n"
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||
blo "40000,57500"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "RST_n"
|
||
t "std_ulogic"
|
||
o 15
|
||
suid 2021,0
|
||
)
|
||
)
|
||
)
|
||
*52 (CptPort
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||
uid 5724,0
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
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||
uid 5725,0
|
||
va (VaSet
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||
vasetType 1
|
||
fg "0,65535,0"
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)
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||
xt "46625,34250,47375,35000"
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)
|
||
tg (CPTG
|
||
uid 5726,0
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "RightVerticalLayoutStrategy"
|
||
f (Text
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uid 5727,0
|
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va (VaSet
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||
font "Verdana,12,0"
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)
|
||
xt "44000,36000,49600,37400"
|
||
st "testOut"
|
||
ju 2
|
||
blo "49600,37200"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 1
|
||
decl (Decl
|
||
n "testOut"
|
||
t "std_uLogic_vector"
|
||
b "(1 DOWNTO 0)"
|
||
o 21
|
||
suid 2022,0
|
||
)
|
||
)
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)
|
||
]
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shape (Rectangle
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uid 5730,0
|
||
va (VaSet
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||
vasetType 1
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||
fg "0,65535,0"
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lineColor "0,32896,0"
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lineWidth 2
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)
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xt "39000,35000,55000,67000"
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)
|
||
oxt "40000,2000,56000,34000"
|
||
ttg (MlTextGroup
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uid 5731,0
|
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ps "CenterOffsetStrategy"
|
||
stg "VerticalLayoutStrategy"
|
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textVec [
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*53 (Text
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||
uid 5732,0
|
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va (VaSet
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font "Verdana,8,1"
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)
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||
xt "39100,66700,42800,67700"
|
||
st "Cursor"
|
||
blo "39100,67500"
|
||
tm "BdLibraryNameMgr"
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)
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*54 (Text
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uid 5733,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "39100,67700,46400,68700"
|
||
st "cursorCircuit"
|
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blo "39100,68500"
|
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tm "CptNameMgr"
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)
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*55 (Text
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uid 5734,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "39100,68700,42600,69700"
|
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st "I_DUT"
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blo "39100,69500"
|
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tm "InstanceNameMgr"
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|
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)
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ga (GenericAssociation
|
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uid 5735,0
|
||
ps "EdgeToEdgeStrategy"
|
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matrix (Matrix
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uid 5736,0
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text (MLText
|
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uid 5737,0
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va (VaSet
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||
font "Courier New,8,0"
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)
|
||
xt "39000,70200,66500,75000"
|
||
st "position0 = position0 ( positive )
|
||
position1 = position1 ( positive )
|
||
position2 = position2 ( positive )
|
||
slopeShiftBitNb = slopeShiftBitNb ( positive )
|
||
pwmBitNb = pwmBitNb ( positive )
|
||
testLineNb = 0 ( positive ) "
|
||
)
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header ""
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)
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elements [
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|
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name "position0"
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type "positive"
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value "position0"
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)
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(GiElement
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name "position1"
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type "positive"
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value "position1"
|
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)
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(GiElement
|
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name "position2"
|
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type "positive"
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value "position2"
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)
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(GiElement
|
||
name "slopeShiftBitNb"
|
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type "positive"
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value "slopeShiftBitNb"
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)
|
||
(GiElement
|
||
name "pwmBitNb"
|
||
type "positive"
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||
value "pwmBitNb"
|
||
)
|
||
(GiElement
|
||
name "testLineNb"
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type "positive"
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value "0"
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)
|
||
]
|
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)
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portVis (PortSigDisplay
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sTC 0
|
||
sT 1
|
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)
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archFileType "UNKNOWN"
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)
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*56 (Wire
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uid 1317,0
|
||
shape (OrthoPolyLine
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uid 1318,0
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||
va (VaSet
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vasetType 3
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)
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||
xt "35000,65000,38250,75000"
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pts [
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||
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||
"35000,75000"
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||
]
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)
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start &33
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
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tg (WTG
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uid 1321,0
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||
ps "ConnStartEndStrategy"
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stg "STSignalDisplayStrategy"
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f (Text
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uid 1322,0
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va (VaSet
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font "Verdana,12,0"
|
||
)
|
||
xt "35000,63600,39100,65000"
|
||
st "reset"
|
||
blo "35000,64800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &1
|
||
)
|
||
*57 (Wire
|
||
uid 1327,0
|
||
shape (OrthoPolyLine
|
||
uid 1328,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "33000,63000,38250,75000"
|
||
pts [
|
||
"38250,63000"
|
||
"33000,63000"
|
||
"33000,75000"
|
||
]
|
||
)
|
||
start &32
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 1331,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 1332,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "35000,61600,38800,63000"
|
||
st "clock"
|
||
blo "35000,62800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &2
|
||
)
|
||
*58 (Wire
|
||
uid 1925,0
|
||
shape (OrthoPolyLine
|
||
uid 1926,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "31000,61000,38250,75000"
|
||
pts [
|
||
"38250,61000"
|
||
"31000,61000"
|
||
"31000,75000"
|
||
]
|
||
)
|
||
start &38
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 1929,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 1930,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "31250,59600,37950,61000"
|
||
st "testMode"
|
||
blo "31250,60800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &18
|
||
)
|
||
*59 (Wire
|
||
uid 2446,0
|
||
shape (OrthoPolyLine
|
||
uid 2447,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,49000,67000,75000"
|
||
pts [
|
||
"55750,49000"
|
||
"67000,49000"
|
||
"67000,75000"
|
||
]
|
||
)
|
||
start &41
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 2450,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 2451,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,47600,63650,49000"
|
||
st "sensor2"
|
||
blo "57750,48800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &19
|
||
)
|
||
*60 (Wire
|
||
uid 2454,0
|
||
shape (OrthoPolyLine
|
||
uid 2455,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,47000,69000,75000"
|
||
pts [
|
||
"55750,47000"
|
||
"69000,47000"
|
||
"69000,75000"
|
||
]
|
||
)
|
||
start &37
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 2458,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 2459,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,45600,63650,47000"
|
||
st "sensor1"
|
||
blo "57750,46800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &20
|
||
)
|
||
*61 (Wire
|
||
uid 2599,0
|
||
shape (OrthoPolyLine
|
||
uid 2600,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,39000,77000,75000"
|
||
pts [
|
||
"55750,39000"
|
||
"77000,39000"
|
||
"77000,75000"
|
||
]
|
||
)
|
||
start &42
|
||
end &14
|
||
sat 32
|
||
eat 1
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 2603,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 2604,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,37600,64050,39000"
|
||
st "motorOn"
|
||
blo "57750,38800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &21
|
||
)
|
||
*62 (Wire
|
||
uid 2890,0
|
||
shape (OrthoPolyLine
|
||
uid 2891,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,41000,75000,75000"
|
||
pts [
|
||
"55750,41000"
|
||
"75000,41000"
|
||
"75000,75000"
|
||
]
|
||
)
|
||
start &34
|
||
end &14
|
||
sat 32
|
||
eat 1
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 2894,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 2895,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,39600,61950,41000"
|
||
st "side1"
|
||
blo "57750,40800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &22
|
||
)
|
||
*63 (Wire
|
||
uid 2898,0
|
||
shape (OrthoPolyLine
|
||
uid 2899,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,43000,73000,75000"
|
||
pts [
|
||
"55750,43000"
|
||
"73000,43000"
|
||
"73000,75000"
|
||
]
|
||
)
|
||
start &40
|
||
end &14
|
||
sat 32
|
||
eat 1
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 2902,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 2903,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,41600,61950,43000"
|
||
st "side2"
|
||
blo "57750,42800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &23
|
||
)
|
||
*64 (Wire
|
||
uid 3011,0
|
||
shape (OrthoPolyLine
|
||
uid 3012,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "25000,43000,38250,75000"
|
||
pts [
|
||
"38250,43000"
|
||
"25000,43000"
|
||
"25000,75000"
|
||
]
|
||
)
|
||
start &36
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3015,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3016,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "35250,41600,38450,43000"
|
||
st "go2"
|
||
blo "35250,42800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &24
|
||
)
|
||
*65 (Wire
|
||
uid 3019,0
|
||
shape (OrthoPolyLine
|
||
uid 3020,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "23000,41000,38250,75000"
|
||
pts [
|
||
"38250,41000"
|
||
"23000,41000"
|
||
"23000,75000"
|
||
]
|
||
)
|
||
start &39
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3023,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3024,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "35250,39600,38450,41000"
|
||
st "go1"
|
||
blo "35250,40800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &25
|
||
)
|
||
*66 (Wire
|
||
uid 3027,0
|
||
shape (OrthoPolyLine
|
||
uid 3028,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "21000,39000,38250,75000"
|
||
pts [
|
||
"38250,39000"
|
||
"21000,39000"
|
||
"21000,75000"
|
||
]
|
||
)
|
||
start &35
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3031,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3032,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "33250,37600,38350,39000"
|
||
st "restart"
|
||
blo "33250,38800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &26
|
||
)
|
||
*67 (Wire
|
||
uid 3035,0
|
||
shape (OrthoPolyLine
|
||
uid 3036,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,57000,59000,75000"
|
||
pts [
|
||
"55750,57000"
|
||
"59000,57000"
|
||
"59000,75000"
|
||
]
|
||
)
|
||
start &45
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3039,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3040,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,55600,64150,57000"
|
||
st "encoderI"
|
||
blo "57750,56800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &27
|
||
)
|
||
*68 (Wire
|
||
uid 3043,0
|
||
shape (OrthoPolyLine
|
||
uid 3044,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,55000,61000,75000"
|
||
pts [
|
||
"55750,55000"
|
||
"61000,55000"
|
||
"61000,75000"
|
||
]
|
||
)
|
||
start &44
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3047,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3048,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,53600,64450,55000"
|
||
st "encoderB"
|
||
blo "57750,54800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &28
|
||
)
|
||
*69 (Wire
|
||
uid 3051,0
|
||
shape (OrthoPolyLine
|
||
uid 3052,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "55750,53000,63000,75000"
|
||
pts [
|
||
"55750,53000"
|
||
"63000,53000"
|
||
"63000,75000"
|
||
]
|
||
)
|
||
start &43
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3055,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3056,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "57750,51600,64450,53000"
|
||
st "encoderA"
|
||
blo "57750,52800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &29
|
||
)
|
||
*70 (Wire
|
||
uid 3656,0
|
||
shape (OrthoPolyLine
|
||
uid 3657,0
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
xt "27000,45000,38250,75000"
|
||
pts [
|
||
"38250,45000"
|
||
"27000,45000"
|
||
"27000,75000"
|
||
]
|
||
)
|
||
start &46
|
||
end &14
|
||
sat 32
|
||
eat 2
|
||
stc 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
uid 3660,0
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
uid 3661,0
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "32000,43600,37800,45000"
|
||
st "button4"
|
||
blo "32000,44800"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
on &30
|
||
)
|
||
]
|
||
bg "65535,65535,65535"
|
||
grid (Grid
|
||
origin "0,0"
|
||
isVisible 1
|
||
isActive 1
|
||
xSpacing 1000
|
||
xySpacing 1000
|
||
xShown 1
|
||
yShown 1
|
||
color "32768,32768,32768"
|
||
)
|
||
packageList *71 (PackageList
|
||
uid 187,0
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*72 (Text
|
||
uid 1297,0
|
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va (VaSet
|
||
font "Verdana,12,0"
|
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)
|
||
xt "-7000,19600,2100,20900"
|
||
st "Package List"
|
||
blo "-7000,20600"
|
||
)
|
||
*73 (MLText
|
||
uid 1298,0
|
||
va (VaSet
|
||
)
|
||
xt "-7000,21000,10500,24600"
|
||
st "LIBRARY ieee;
|
||
USE ieee.std_logic_1164.all;
|
||
USE ieee.numeric_std.all;"
|
||
tm "PackageList"
|
||
)
|
||
]
|
||
)
|
||
compDirBlock (MlTextGroup
|
||
uid 190,0
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*74 (Text
|
||
uid 191,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "20000,0,32000,1000"
|
||
st "Compiler Directives"
|
||
blo "20000,800"
|
||
)
|
||
*75 (Text
|
||
uid 192,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "20000,1400,33800,2400"
|
||
st "Pre-module directives:"
|
||
blo "20000,2200"
|
||
)
|
||
*76 (MLText
|
||
uid 193,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "20000,2800,32100,5200"
|
||
st "`resetall
|
||
`timescale 1ns/10ps"
|
||
tm "BdCompilerDirectivesTextMgr"
|
||
)
|
||
*77 (Text
|
||
uid 194,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "20000,5600,34400,6600"
|
||
st "Post-module directives:"
|
||
blo "20000,6400"
|
||
)
|
||
*78 (MLText
|
||
uid 195,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "20000,7000,20000,7000"
|
||
tm "BdCompilerDirectivesTextMgr"
|
||
)
|
||
*79 (Text
|
||
uid 196,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "20000,7200,33800,8200"
|
||
st "End-module directives:"
|
||
blo "20000,8000"
|
||
)
|
||
*80 (MLText
|
||
uid 197,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
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||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "3000,500,3000,500"
|
||
blo "3000,500"
|
||
tm "WireNameMgr"
|
||
)
|
||
s (Text
|
||
va (VaSet
|
||
)
|
||
xt "3000,500,3000,500"
|
||
blo "3000,500"
|
||
tm "SignalTypeMgr"
|
||
)
|
||
)
|
||
)
|
||
defaultSignal (Wire
|
||
shape (OrthoPolyLine
|
||
va (VaSet
|
||
vasetType 3
|
||
)
|
||
pts [
|
||
"0,0"
|
||
"0,0"
|
||
]
|
||
)
|
||
ss 0
|
||
es 0
|
||
sat 32
|
||
eat 32
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,0,2600,1400"
|
||
st "sig0"
|
||
blo "0,1200"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
)
|
||
defaultBus (Wire
|
||
shape (OrthoPolyLine
|
||
va (VaSet
|
||
vasetType 3
|
||
lineWidth 2
|
||
)
|
||
pts [
|
||
"0,0"
|
||
"0,0"
|
||
]
|
||
)
|
||
ss 0
|
||
es 0
|
||
sat 32
|
||
eat 32
|
||
sty 1
|
||
stc 0
|
||
st 0
|
||
sf 1
|
||
si 0
|
||
tg (WTG
|
||
ps "ConnStartEndStrategy"
|
||
stg "STSignalDisplayStrategy"
|
||
f (Text
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,0,3900,1400"
|
||
st "dbus0"
|
||
blo "0,1200"
|
||
tm "WireNameMgr"
|
||
)
|
||
)
|
||
)
|
||
defaultBundle (Bundle
|
||
shape (OrthoPolyLine
|
||
va (VaSet
|
||
vasetType 3
|
||
lineColor "32768,0,0"
|
||
lineStyle 3
|
||
lineWidth 2
|
||
)
|
||
pts [
|
||
"0,0"
|
||
"0,0"
|
||
]
|
||
)
|
||
ss 0
|
||
es 0
|
||
sat 32
|
||
eat 32
|
||
textGroup (BiTextGroup
|
||
ps "ConnStartEndStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
first (Text
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,0,5100,1400"
|
||
st "bundle0"
|
||
blo "0,1200"
|
||
tm "BundleNameMgr"
|
||
)
|
||
second (MLText
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,1400,1800,2800"
|
||
st "()"
|
||
tm "BundleContentsMgr"
|
||
)
|
||
)
|
||
bundleNet &0
|
||
)
|
||
defaultPortMapFrame (PortMapFrame
|
||
ps "PortMapFrameStrategy"
|
||
shape (RectFrame
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
lineColor "0,0,32768"
|
||
lineWidth 2
|
||
)
|
||
xt "0,0,10000,12000"
|
||
)
|
||
portMapText (BiTextGroup
|
||
ps "BottomRightOffsetStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
first (MLText
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,0,5900,1400"
|
||
st "Auto list"
|
||
)
|
||
second (MLText
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,1400,11800,2800"
|
||
st "User defined list"
|
||
tm "PortMapTextMgr"
|
||
)
|
||
)
|
||
)
|
||
defaultGenFrame (Frame
|
||
shape (RectFrame
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
lineColor "26368,26368,26368"
|
||
lineStyle 2
|
||
lineWidth 2
|
||
)
|
||
xt "0,0,20000,20000"
|
||
)
|
||
title (TextAssociate
|
||
ps "TopLeftStrategy"
|
||
text (MLText
|
||
va (VaSet
|
||
)
|
||
xt "0,-1400,18500,-200"
|
||
st "g0: FOR i IN 0 TO n GENERATE"
|
||
tm "FrameTitleTextMgr"
|
||
)
|
||
)
|
||
seqNum (FrameSequenceNumber
|
||
ps "TopLeftStrategy"
|
||
shape (Rectangle
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
)
|
||
xt "50,50,1050,1750"
|
||
)
|
||
num (Text
|
||
va (VaSet
|
||
)
|
||
xt "200,300,600,1300"
|
||
st "1"
|
||
blo "200,1100"
|
||
tm "FrameSeqNumMgr"
|
||
)
|
||
)
|
||
decls (MlTextGroup
|
||
ps "BottomRightOffsetStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*98 (Text
|
||
va (VaSet
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "11800,20000,22600,21200"
|
||
st "Frame Declarations"
|
||
blo "11800,21000"
|
||
)
|
||
*99 (MLText
|
||
va (VaSet
|
||
)
|
||
xt "11800,21200,11800,21200"
|
||
tm "BdFrameDeclTextMgr"
|
||
)
|
||
]
|
||
)
|
||
)
|
||
defaultBlockFrame (Frame
|
||
shape (RectFrame
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
lineColor "26368,26368,26368"
|
||
lineStyle 1
|
||
lineWidth 2
|
||
)
|
||
xt "0,0,20000,20000"
|
||
)
|
||
title (TextAssociate
|
||
ps "TopLeftStrategy"
|
||
text (MLText
|
||
va (VaSet
|
||
)
|
||
xt "0,-1400,11000,-200"
|
||
st "b0: BLOCK (guard)"
|
||
tm "FrameTitleTextMgr"
|
||
)
|
||
)
|
||
seqNum (FrameSequenceNumber
|
||
ps "TopLeftStrategy"
|
||
shape (Rectangle
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
)
|
||
xt "50,50,1050,1750"
|
||
)
|
||
num (Text
|
||
va (VaSet
|
||
)
|
||
xt "200,300,600,1300"
|
||
st "1"
|
||
blo "200,1100"
|
||
tm "FrameSeqNumMgr"
|
||
)
|
||
)
|
||
decls (MlTextGroup
|
||
ps "BottomRightOffsetStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
textVec [
|
||
*100 (Text
|
||
va (VaSet
|
||
font "Verdana,9,1"
|
||
)
|
||
xt "11800,20000,22600,21200"
|
||
st "Frame Declarations"
|
||
blo "11800,21000"
|
||
)
|
||
*101 (MLText
|
||
va (VaSet
|
||
)
|
||
xt "11800,21200,11800,21200"
|
||
tm "BdFrameDeclTextMgr"
|
||
)
|
||
]
|
||
)
|
||
style 3
|
||
)
|
||
defaultSaCptPort (CptPort
|
||
ps "OnEdgeStrategy"
|
||
shape (Triangle
|
||
ro 90
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "0,65535,0"
|
||
)
|
||
xt "0,0,750,750"
|
||
)
|
||
tg (CPTG
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,750,2600,2150"
|
||
st "Port"
|
||
blo "0,1950"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
decl (Decl
|
||
n "Port"
|
||
t ""
|
||
o 0
|
||
)
|
||
)
|
||
)
|
||
defaultSaCptPortBuffer (CptPort
|
||
ps "OnEdgeStrategy"
|
||
shape (Diamond
|
||
va (VaSet
|
||
vasetType 1
|
||
fg "65535,65535,65535"
|
||
)
|
||
xt "0,0,750,750"
|
||
)
|
||
tg (CPTG
|
||
ps "CptPortTextPlaceStrategy"
|
||
stg "VerticalLayoutStrategy"
|
||
f (Text
|
||
va (VaSet
|
||
font "Verdana,12,0"
|
||
)
|
||
xt "0,750,2600,2150"
|
||
st "Port"
|
||
blo "0,1950"
|
||
)
|
||
)
|
||
thePort (LogicalPort
|
||
m 3
|
||
decl (Decl
|
||
n "Port"
|
||
t ""
|
||
o 0
|
||
)
|
||
)
|
||
)
|
||
defaultDeclText (MLText
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
)
|
||
archDeclarativeBlock (BdArchDeclBlock
|
||
uid 1,0
|
||
stg "BdArchDeclBlockLS"
|
||
declLabel (Text
|
||
uid 2,0
|
||
va (VaSet
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "-7000,24400,800,25400"
|
||
st "Declarations"
|
||
blo "-7000,25200"
|
||
)
|
||
portLabel (Text
|
||
uid 3,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "-7000,25600,-3400,26600"
|
||
st "Ports:"
|
||
blo "-7000,26400"
|
||
)
|
||
preUserLabel (Text
|
||
uid 4,0
|
||
va (VaSet
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "-7000,25400,-1600,26400"
|
||
st "Pre User:"
|
||
blo "-7000,26200"
|
||
)
|
||
preUserText (MLText
|
||
uid 5,0
|
||
va (VaSet
|
||
)
|
||
xt "-5000,26400,38900,36000"
|
||
st "constant stepsPerTurn : positive := 500 * 4;
|
||
constant mmPerTurn : real:= 1.75;
|
||
constant position0 : positive := integer(3.0 * real(stepsPerTurn) / mmPerTurn );
|
||
constant position1 : positive := integer(8.0 * real(stepsPerTurn) / mmPerTurn );
|
||
constant position2 : positive := integer(12.0 * real(stepsPerTurn) / mmPerTurn );
|
||
constant slopeShiftBitNb : positive := 2;
|
||
constant pwmBitNb : positive := 8;
|
||
constant testLineNb : positive := 16;"
|
||
tm "BdDeclarativeTextMgr"
|
||
)
|
||
diagSignalLabel (Text
|
||
uid 6,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "-7000,25600,3200,26600"
|
||
st "Diagram Signals:"
|
||
blo "-7000,26400"
|
||
)
|
||
postUserLabel (Text
|
||
uid 7,0
|
||
va (VaSet
|
||
isHidden 1
|
||
font "Verdana,10,1"
|
||
)
|
||
xt "-7000,25600,-400,26600"
|
||
st "Post User:"
|
||
blo "-7000,26400"
|
||
)
|
||
postUserText (MLText
|
||
uid 8,0
|
||
va (VaSet
|
||
isHidden 1
|
||
)
|
||
xt "-5000,40000,-5000,40000"
|
||
tm "BdDeclarativeTextMgr"
|
||
)
|
||
)
|
||
commonDM (CommonDM
|
||
ldm (LogicalDM
|
||
suid 38,0
|
||
usingSuid 1
|
||
emptyRow *102 (LEmptyRow
|
||
)
|
||
uid 3264,0
|
||
optionalChildren [
|
||
*103 (RefLabelRowHdr
|
||
)
|
||
*104 (TitleRowHdr
|
||
)
|
||
*105 (FilterRowHdr
|
||
)
|
||
*106 (RefLabelColHdr
|
||
tm "RefLabelColHdrMgr"
|
||
)
|
||
*107 (RowExpandColHdr
|
||
tm "RowExpandColHdrMgr"
|
||
)
|
||
*108 (GroupColHdr
|
||
tm "GroupColHdrMgr"
|
||
)
|
||
*109 (NameColHdr
|
||
tm "BlockDiagramNameColHdrMgr"
|
||
)
|
||
*110 (ModeColHdr
|
||
tm "BlockDiagramModeColHdrMgr"
|
||
)
|
||
*111 (TypeColHdr
|
||
tm "BlockDiagramTypeColHdrMgr"
|
||
)
|
||
*112 (BoundsColHdr
|
||
tm "BlockDiagramBoundsColHdrMgr"
|
||
)
|
||
*113 (InitColHdr
|
||
tm "BlockDiagramInitColHdrMgr"
|
||
)
|
||
*114 (EolColHdr
|
||
tm "BlockDiagramEolColHdrMgr"
|
||
)
|
||
*115 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "reset"
|
||
t "std_ulogic"
|
||
o 9
|
||
suid 1,0
|
||
)
|
||
)
|
||
uid 3233,0
|
||
)
|
||
*116 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "clock"
|
||
t "std_ulogic"
|
||
o 2
|
||
suid 2,0
|
||
)
|
||
)
|
||
uid 3235,0
|
||
)
|
||
*117 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "testMode"
|
||
t "std_uLogic"
|
||
o 15
|
||
suid 3,0
|
||
)
|
||
)
|
||
uid 3237,0
|
||
)
|
||
*118 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "sensor2"
|
||
t "std_uLogic"
|
||
o 12
|
||
suid 4,0
|
||
)
|
||
)
|
||
uid 3239,0
|
||
)
|
||
*119 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "sensor1"
|
||
t "std_uLogic"
|
||
o 11
|
||
suid 5,0
|
||
)
|
||
)
|
||
uid 3241,0
|
||
)
|
||
*120 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "motorOn"
|
||
t "std_uLogic"
|
||
o 8
|
||
suid 6,0
|
||
)
|
||
)
|
||
uid 3243,0
|
||
)
|
||
*121 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "side1"
|
||
t "std_uLogic"
|
||
o 13
|
||
suid 7,0
|
||
)
|
||
)
|
||
uid 3245,0
|
||
)
|
||
*122 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "side2"
|
||
t "std_uLogic"
|
||
o 14
|
||
suid 8,0
|
||
)
|
||
)
|
||
uid 3247,0
|
||
)
|
||
*123 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "go2"
|
||
t "std_uLogic"
|
||
o 7
|
||
suid 10,0
|
||
)
|
||
)
|
||
uid 3251,0
|
||
)
|
||
*124 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "go1"
|
||
t "std_uLogic"
|
||
o 6
|
||
suid 11,0
|
||
)
|
||
)
|
||
uid 3253,0
|
||
)
|
||
*125 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "restart"
|
||
t "std_uLogic"
|
||
o 10
|
||
suid 12,0
|
||
)
|
||
)
|
||
uid 3255,0
|
||
)
|
||
*126 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "encoderI"
|
||
t "std_uLogic"
|
||
o 5
|
||
suid 13,0
|
||
)
|
||
)
|
||
uid 3257,0
|
||
)
|
||
*127 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "encoderB"
|
||
t "std_uLogic"
|
||
o 4
|
||
suid 14,0
|
||
)
|
||
)
|
||
uid 3259,0
|
||
)
|
||
*128 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "encoderA"
|
||
t "std_uLogic"
|
||
o 3
|
||
suid 15,0
|
||
)
|
||
)
|
||
uid 3261,0
|
||
)
|
||
*129 (LeafLogPort
|
||
port (LogicalPort
|
||
m 4
|
||
decl (Decl
|
||
n "button4"
|
||
t "std_uLogic"
|
||
o 1
|
||
suid 16,0
|
||
)
|
||
)
|
||
uid 3662,0
|
||
)
|
||
]
|
||
)
|
||
pdm (PhysicalDM
|
||
displayShortBounds 1
|
||
editShortBounds 1
|
||
uid 3277,0
|
||
optionalChildren [
|
||
*130 (Sheet
|
||
sheetRow (SheetRow
|
||
headerVa (MVa
|
||
cellColor "49152,49152,49152"
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)
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cellVa (MVa
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groupVa (MVa
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)
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emptyMRCItem *131 (MRCItem
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litem &102
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pos 15
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dimension 20
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)
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||
uid 3279,0
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optionalChildren [
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*132 (MRCItem
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litem &103
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pos 0
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||
dimension 20
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||
uid 3280,0
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)
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||
*133 (MRCItem
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||
litem &104
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pos 1
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||
dimension 23
|
||
uid 3281,0
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||
)
|
||
*134 (MRCItem
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||
litem &105
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||
pos 2
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||
hidden 1
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||
dimension 20
|
||
uid 3282,0
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)
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*135 (MRCItem
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||
litem &115
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pos 0
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||
dimension 20
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||
uid 3234,0
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)
|
||
*136 (MRCItem
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||
litem &116
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||
pos 1
|
||
dimension 20
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||
uid 3236,0
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||
)
|
||
*137 (MRCItem
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||
litem &117
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||
pos 2
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||
dimension 20
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||
uid 3238,0
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)
|
||
*138 (MRCItem
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||
litem &118
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pos 3
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dimension 20
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uid 3240,0
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)
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*139 (MRCItem
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||
litem &119
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||
pos 4
|
||
dimension 20
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||
uid 3242,0
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)
|
||
*140 (MRCItem
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||
litem &120
|
||
pos 5
|
||
dimension 20
|
||
uid 3244,0
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)
|
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*141 (MRCItem
|
||
litem &121
|
||
pos 6
|
||
dimension 20
|
||
uid 3246,0
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)
|
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*142 (MRCItem
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||
litem &122
|
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pos 7
|
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dimension 20
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uid 3248,0
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)
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*143 (MRCItem
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litem &123
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pos 8
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dimension 20
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uid 3252,0
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)
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*144 (MRCItem
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||
litem &124
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pos 9
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dimension 20
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uid 3254,0
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)
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*145 (MRCItem
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litem &125
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pos 10
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dimension 20
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uid 3256,0
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)
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*146 (MRCItem
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litem &126
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pos 11
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dimension 20
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uid 3258,0
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)
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*147 (MRCItem
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litem &127
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pos 12
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dimension 20
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uid 3260,0
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)
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*148 (MRCItem
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||
litem &128
|
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pos 13
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dimension 20
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uid 3262,0
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)
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*149 (MRCItem
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||
litem &129
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pos 14
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dimension 20
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uid 3663,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 3283,0
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optionalChildren [
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*150 (MRCItem
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||
litem &106
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pos 0
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dimension 20
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||
uid 3284,0
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)
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*151 (MRCItem
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litem &108
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pos 1
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dimension 50
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uid 3285,0
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)
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*152 (MRCItem
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litem &109
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pos 2
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dimension 100
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uid 3286,0
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)
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*153 (MRCItem
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litem &110
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pos 3
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dimension 50
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uid 3287,0
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)
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*154 (MRCItem
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litem &111
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pos 4
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dimension 100
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uid 3288,0
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)
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*155 (MRCItem
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litem &112
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pos 5
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dimension 100
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uid 3289,0
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)
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*156 (MRCItem
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litem &113
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pos 6
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dimension 50
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uid 3290,0
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)
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*157 (MRCItem
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litem &114
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pos 7
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dimension 80
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uid 3291,0
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)
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]
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)
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fixedCol 4
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fixedRow 2
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name "Ports"
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uid 3278,0
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vaOverrides [
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]
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)
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]
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)
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uid 3263,0
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)
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genericsCommonDM (CommonDM
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ldm (LogicalDM
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emptyRow *158 (LEmptyRow
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)
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uid 3293,0
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optionalChildren [
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*159 (RefLabelRowHdr
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)
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*160 (TitleRowHdr
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)
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*161 (FilterRowHdr
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)
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*162 (RefLabelColHdr
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tm "RefLabelColHdrMgr"
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)
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*163 (RowExpandColHdr
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tm "RowExpandColHdrMgr"
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)
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*164 (GroupColHdr
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tm "GroupColHdrMgr"
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)
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*165 (NameColHdr
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tm "GenericNameColHdrMgr"
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)
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*166 (TypeColHdr
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tm "GenericTypeColHdrMgr"
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)
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*167 (InitColHdr
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tm "GenericValueColHdrMgr"
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)
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*168 (PragmaColHdr
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tm "GenericPragmaColHdrMgr"
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)
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*169 (EolColHdr
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tm "GenericEolColHdrMgr"
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)
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]
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)
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pdm (PhysicalDM
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uid 3305,0
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optionalChildren [
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*170 (Sheet
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sheetRow (SheetRow
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headerVa (MVa
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cellColor "49152,49152,49152"
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font "Tahoma,10,0"
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)
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cellVa (MVa
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cellColor "65535,65535,65535"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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groupVa (MVa
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cellColor "39936,56832,65280"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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)
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emptyMRCItem *171 (MRCItem
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litem &158
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pos 0
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dimension 20
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)
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uid 3307,0
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optionalChildren [
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*172 (MRCItem
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litem &159
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pos 0
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dimension 20
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uid 3308,0
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)
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*173 (MRCItem
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||
litem &160
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pos 1
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dimension 23
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uid 3309,0
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)
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*174 (MRCItem
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litem &161
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pos 2
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hidden 1
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dimension 20
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uid 3310,0
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)
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]
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)
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sheetCol (SheetCol
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propVa (MVa
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cellColor "0,49152,49152"
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fontColor "0,0,0"
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font "Tahoma,10,0"
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textAngle 90
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)
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uid 3311,0
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optionalChildren [
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*175 (MRCItem
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litem &162
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pos 0
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dimension 20
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uid 3312,0
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)
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*176 (MRCItem
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litem &164
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pos 1
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dimension 50
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uid 3313,0
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)
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*177 (MRCItem
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litem &165
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pos 2
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dimension 100
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uid 3314,0
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)
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*178 (MRCItem
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litem &166
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pos 3
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dimension 100
|
||
uid 3315,0
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)
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*179 (MRCItem
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||
litem &167
|
||
pos 4
|
||
dimension 50
|
||
uid 3316,0
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)
|
||
*180 (MRCItem
|
||
litem &168
|
||
pos 5
|
||
dimension 50
|
||
uid 3317,0
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)
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*181 (MRCItem
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||
litem &169
|
||
pos 6
|
||
dimension 80
|
||
uid 3318,0
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||
)
|
||
]
|
||
)
|
||
fixedCol 3
|
||
fixedRow 2
|
||
name "Ports"
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||
uid 3306,0
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||
vaOverrides [
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||
]
|
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)
|
||
]
|
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)
|
||
uid 3292,0
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type 1
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)
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activeModelName "BlockDiag"
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)
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