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17 lines
427 B
VHDL
17 lines
427 B
VHDL
ARCHITECTURE sim OF mux4to1ULogicVector IS
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BEGIN
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muxSelect: process(sel, in0, in1, in2, in3)
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begin
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case to_integer(sel) is
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when 0 => muxOut <= in0 after delay;
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when 1 => muxOut <= in1 after delay;
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when 2 => muxOut <= in2 after delay;
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when 3 => muxOut <= in3 after delay;
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when others => muxOut <= (others => 'X') after delay;
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end case;
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end process muxSelect;
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END ARCHITECTURE sim;
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