mirror of
https://github.com/Klagarge/Cursor.git
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1594 lines
20 KiB
Plaintext
1594 lines
20 KiB
Plaintext
DocumentHdrVersion "1.1"
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Header (DocumentHdr
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version 2
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dialect 11
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dmPackageRefs [
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(DmPackageRef
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library "ieee"
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unitName "std_logic_1164"
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)
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(DmPackageRef
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library "gates"
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unitName "gates"
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)
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]
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libraryRefs [
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"ieee"
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"gates"
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]
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)
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version "26.1"
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appVersion "2018.1 (Build 12)"
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model (Symbol
|
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commonDM (CommonDM
|
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ldm (LogicalDM
|
|
suid 2004,0
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usingSuid 1
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|
emptyRow *1 (LEmptyRow
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|
)
|
|
uid 158,0
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|
optionalChildren [
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|
*2 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in3"
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|
t "std_uLogic"
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o 3
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suid 2,0
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|
)
|
|
)
|
|
uid 159,0
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|
)
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|
*3 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in1"
|
|
t "std_uLogic"
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|
o 1
|
|
suid 1,0
|
|
)
|
|
)
|
|
uid 160,0
|
|
)
|
|
*4 (LogPort
|
|
port (LogicalPort
|
|
decl (Decl
|
|
n "in2"
|
|
t "std_uLogic"
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|
o 2
|
|
suid 3,0
|
|
)
|
|
)
|
|
uid 161,0
|
|
)
|
|
*5 (LogPort
|
|
port (LogicalPort
|
|
m 1
|
|
decl (Decl
|
|
n "out1"
|
|
t "std_uLogic"
|
|
o 4
|
|
suid 4,0
|
|
)
|
|
)
|
|
uid 162,0
|
|
)
|
|
*6 (RefLabelRowHdr
|
|
)
|
|
*7 (TitleRowHdr
|
|
)
|
|
*8 (FilterRowHdr
|
|
)
|
|
*9 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*10 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*11 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*12 (NameColHdr
|
|
tm "NameColHdrMgr"
|
|
)
|
|
*13 (ModeColHdr
|
|
tm "ModeColHdrMgr"
|
|
)
|
|
*14 (TypeColHdr
|
|
tm "TypeColHdrMgr"
|
|
)
|
|
*15 (BoundsColHdr
|
|
tm "BoundsColHdrMgr"
|
|
)
|
|
*16 (InitColHdr
|
|
tm "InitColHdrMgr"
|
|
)
|
|
*17 (EolColHdr
|
|
tm "EolColHdrMgr"
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 163,0
|
|
optionalChildren [
|
|
*18 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *19 (MRCItem
|
|
litem &1
|
|
pos 4
|
|
dimension 20
|
|
)
|
|
uid 100,0
|
|
optionalChildren [
|
|
*20 (MRCItem
|
|
litem &6
|
|
pos 0
|
|
dimension 20
|
|
uid 103,0
|
|
)
|
|
*21 (MRCItem
|
|
litem &7
|
|
pos 1
|
|
dimension 23
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|
uid 105,0
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)
|
|
*22 (MRCItem
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litem &8
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pos 2
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hidden 1
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|
dimension 20
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|
uid 107,0
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)
|
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*23 (MRCItem
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|
litem &2
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pos 2
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dimension 20
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uid 126,0
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)
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*24 (MRCItem
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litem &3
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pos 0
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dimension 20
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uid 127,0
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)
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*25 (MRCItem
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litem &4
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pos 1
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|
dimension 20
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uid 128,0
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)
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*26 (MRCItem
|
|
litem &5
|
|
pos 3
|
|
dimension 20
|
|
uid 129,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 101,0
|
|
optionalChildren [
|
|
*27 (MRCItem
|
|
litem &9
|
|
pos 0
|
|
dimension 20
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|
uid 109,0
|
|
)
|
|
*28 (MRCItem
|
|
litem &11
|
|
pos 1
|
|
dimension 50
|
|
uid 113,0
|
|
)
|
|
*29 (MRCItem
|
|
litem &12
|
|
pos 2
|
|
dimension 100
|
|
uid 115,0
|
|
)
|
|
*30 (MRCItem
|
|
litem &13
|
|
pos 3
|
|
dimension 50
|
|
uid 117,0
|
|
)
|
|
*31 (MRCItem
|
|
litem &14
|
|
pos 4
|
|
dimension 100
|
|
uid 119,0
|
|
)
|
|
*32 (MRCItem
|
|
litem &15
|
|
pos 5
|
|
dimension 100
|
|
uid 121,0
|
|
)
|
|
*33 (MRCItem
|
|
litem &16
|
|
pos 6
|
|
dimension 50
|
|
uid 123,0
|
|
)
|
|
*34 (MRCItem
|
|
litem &17
|
|
pos 7
|
|
dimension 80
|
|
uid 125,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 4
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 99,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 157,0
|
|
)
|
|
genericsCommonDM (CommonDM
|
|
ldm (LogicalDM
|
|
emptyRow *35 (LEmptyRow
|
|
)
|
|
uid 165,0
|
|
optionalChildren [
|
|
*36 (RefLabelRowHdr
|
|
)
|
|
*37 (TitleRowHdr
|
|
)
|
|
*38 (FilterRowHdr
|
|
)
|
|
*39 (RefLabelColHdr
|
|
tm "RefLabelColHdrMgr"
|
|
)
|
|
*40 (RowExpandColHdr
|
|
tm "RowExpandColHdrMgr"
|
|
)
|
|
*41 (GroupColHdr
|
|
tm "GroupColHdrMgr"
|
|
)
|
|
*42 (NameColHdr
|
|
tm "GenericNameColHdrMgr"
|
|
)
|
|
*43 (TypeColHdr
|
|
tm "GenericTypeColHdrMgr"
|
|
)
|
|
*44 (InitColHdr
|
|
tm "GenericValueColHdrMgr"
|
|
)
|
|
*45 (PragmaColHdr
|
|
tm "GenericPragmaColHdrMgr"
|
|
)
|
|
*46 (EolColHdr
|
|
tm "GenericEolColHdrMgr"
|
|
)
|
|
*47 (LogGeneric
|
|
generic (GiElement
|
|
name "delay"
|
|
type "time"
|
|
value "gateDelay"
|
|
)
|
|
uid 155,0
|
|
)
|
|
]
|
|
)
|
|
pdm (PhysicalDM
|
|
uid 166,0
|
|
optionalChildren [
|
|
*48 (Sheet
|
|
sheetRow (SheetRow
|
|
headerVa (MVa
|
|
cellColor "49152,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
cellVa (MVa
|
|
cellColor "65535,65535,65535"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
groupVa (MVa
|
|
cellColor "39936,56832,65280"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
)
|
|
emptyMRCItem *49 (MRCItem
|
|
litem &35
|
|
pos 1
|
|
dimension 20
|
|
)
|
|
uid 131,0
|
|
optionalChildren [
|
|
*50 (MRCItem
|
|
litem &36
|
|
pos 0
|
|
dimension 20
|
|
uid 134,0
|
|
)
|
|
*51 (MRCItem
|
|
litem &37
|
|
pos 1
|
|
dimension 23
|
|
uid 136,0
|
|
)
|
|
*52 (MRCItem
|
|
litem &38
|
|
pos 2
|
|
hidden 1
|
|
dimension 20
|
|
uid 138,0
|
|
)
|
|
*53 (MRCItem
|
|
litem &47
|
|
pos 0
|
|
dimension 20
|
|
uid 156,0
|
|
)
|
|
]
|
|
)
|
|
sheetCol (SheetCol
|
|
propVa (MVa
|
|
cellColor "0,49152,49152"
|
|
fontColor "0,0,0"
|
|
font "Tahoma,10,0"
|
|
textAngle 90
|
|
)
|
|
uid 132,0
|
|
optionalChildren [
|
|
*54 (MRCItem
|
|
litem &39
|
|
pos 0
|
|
dimension 20
|
|
uid 140,0
|
|
)
|
|
*55 (MRCItem
|
|
litem &41
|
|
pos 1
|
|
dimension 50
|
|
uid 144,0
|
|
)
|
|
*56 (MRCItem
|
|
litem &42
|
|
pos 2
|
|
dimension 100
|
|
uid 146,0
|
|
)
|
|
*57 (MRCItem
|
|
litem &43
|
|
pos 3
|
|
dimension 100
|
|
uid 148,0
|
|
)
|
|
*58 (MRCItem
|
|
litem &44
|
|
pos 4
|
|
dimension 50
|
|
uid 150,0
|
|
)
|
|
*59 (MRCItem
|
|
litem &45
|
|
pos 5
|
|
dimension 50
|
|
uid 152,0
|
|
)
|
|
*60 (MRCItem
|
|
litem &46
|
|
pos 6
|
|
dimension 80
|
|
uid 154,0
|
|
)
|
|
]
|
|
)
|
|
fixedCol 3
|
|
fixedRow 2
|
|
name "Ports"
|
|
uid 130,0
|
|
vaOverrides [
|
|
]
|
|
)
|
|
]
|
|
)
|
|
uid 164,0
|
|
type 1
|
|
)
|
|
VExpander (VariableExpander
|
|
vvMap [
|
|
(vvPair
|
|
variable " "
|
|
value " "
|
|
)
|
|
(vvPair
|
|
variable "HDLDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hdl"
|
|
)
|
|
(vvPair
|
|
variable "HDSDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "SideDataDesignDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m\\symbol.sb.info"
|
|
)
|
|
(vvPair
|
|
variable "SideDataUserDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m\\symbol.sb.user"
|
|
)
|
|
(vvPair
|
|
variable "SourceDir"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds"
|
|
)
|
|
(vvPair
|
|
variable "appl"
|
|
value "HDL Designer"
|
|
)
|
|
(vvPair
|
|
variable "arch_name"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "concat_file"
|
|
value "concatenated"
|
|
)
|
|
(vvPair
|
|
variable "config"
|
|
value "%(unit)_%(view)_config"
|
|
)
|
|
(vvPair
|
|
variable "d"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m"
|
|
)
|
|
(vvPair
|
|
variable "d_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m"
|
|
)
|
|
(vvPair
|
|
variable "date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "day"
|
|
value "Wed"
|
|
)
|
|
(vvPair
|
|
variable "day_long"
|
|
value "Wednesday"
|
|
)
|
|
(vvPair
|
|
variable "dd"
|
|
value "11"
|
|
)
|
|
(vvPair
|
|
variable "entity_name"
|
|
value "or3_m"
|
|
)
|
|
(vvPair
|
|
variable "ext"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "f"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_logical"
|
|
value "symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "f_noext"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_author"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_date"
|
|
value "11.09.2019"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "graphical_source_time"
|
|
value "14:35:08"
|
|
)
|
|
(vvPair
|
|
variable "group"
|
|
value "UNKNOWN"
|
|
)
|
|
(vvPair
|
|
variable "host"
|
|
value "WE6996"
|
|
)
|
|
(vvPair
|
|
variable "language"
|
|
value "VHDL"
|
|
)
|
|
(vvPair
|
|
variable "library"
|
|
value "gates"
|
|
)
|
|
(vvPair
|
|
variable "library_downstream_ModelSimCompiler"
|
|
value "$SCRATCH_DIR/ElN/Libraries/Gates/work"
|
|
)
|
|
(vvPair
|
|
variable "mm"
|
|
value "09"
|
|
)
|
|
(vvPair
|
|
variable "module_name"
|
|
value "or3_m"
|
|
)
|
|
(vvPair
|
|
variable "month"
|
|
value "Sep"
|
|
)
|
|
(vvPair
|
|
variable "month_long"
|
|
value "September"
|
|
)
|
|
(vvPair
|
|
variable "p"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "p_logical"
|
|
value "C:\\work\\git\\Education\\eln\\labo\\solution\\eln_labs\\Libs\\Gates\\hds\\or3_m\\symbol.sb"
|
|
)
|
|
(vvPair
|
|
variable "package_name"
|
|
value "<Undefined Variable>"
|
|
)
|
|
(vvPair
|
|
variable "project_name"
|
|
value "hds"
|
|
)
|
|
(vvPair
|
|
variable "series"
|
|
value "HDL Designer Series"
|
|
)
|
|
(vvPair
|
|
variable "task_ADMS"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_DesignCompilerPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ISEPath"
|
|
value "D:\\Labs\\ElN\\Kart\\Board\\ise"
|
|
)
|
|
(vvPair
|
|
variable "task_LeonardoPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_ModelSimPath"
|
|
value "C:\\EDA\\Modelsim\\win32"
|
|
)
|
|
(vvPair
|
|
variable "task_NC"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_NC-SimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_PrecisionRTLPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_QuestaSimPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "task_VCSPath"
|
|
value "<TBD>"
|
|
)
|
|
(vvPair
|
|
variable "this_ext"
|
|
value "sb"
|
|
)
|
|
(vvPair
|
|
variable "this_file"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "this_file_logical"
|
|
value "symbol"
|
|
)
|
|
(vvPair
|
|
variable "time"
|
|
value "14:35:08"
|
|
)
|
|
(vvPair
|
|
variable "unit"
|
|
value "or3_m"
|
|
)
|
|
(vvPair
|
|
variable "user"
|
|
value "silvan.zahno"
|
|
)
|
|
(vvPair
|
|
variable "version"
|
|
value "2018.1 (Build 12)"
|
|
)
|
|
(vvPair
|
|
variable "view"
|
|
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)
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packageList *82 (PackageList
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uid 8,0
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stg "VerticalLayoutStrategy"
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textVec [
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uid 97,0
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va (VaSet
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font "Verdana,8,1"
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)
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st "Package List"
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uid 98,0
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va (VaSet
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)
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xt "0,1000,17500,5800"
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USE ieee.std_logic_1164.all;
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LIBRARY gates;
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USE gates.gates.all;"
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tm "PackageList"
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)
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viewArea "-1100,-1100,75364,53908"
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defaultCommentText (CommentText
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va (VaSet
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)
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text (MLText
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va (VaSet
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)
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st "
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tm "CommentText"
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visibleWidth 14600
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)
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)
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defaultRequirementText (RequirementText
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shape (ZoomableIcon
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layer 0
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va (VaSet
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vasetType 1
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)
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text (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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st "
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tm "RequirementText"
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)
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)
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defaultPanel (Panel
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shape (RectFrame
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va (VaSet
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)
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title (TextAssociate
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ps "TopLeftStrategy"
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text (Text
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va (VaSet
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font "Verdana,8,1"
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)
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blo "1000,1800"
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tm "PanelText"
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)
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)
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)
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parentGraphicsRef (HdmGraphicsRef
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libraryName ""
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entityName ""
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viewName ""
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)
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defaultSymbolBody (SymbolBody
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shape (Rectangle
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va (VaSet
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vasetType 1
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biTextGroup (BiTextGroup
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ps "CenterOffsetStrategy"
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stg "VerticalLayoutStrategy"
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first (Text
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va (VaSet
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font "Verdana,8,1"
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)
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xt "26600,24700,30200,25700"
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st "<library>"
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blo "26600,25500"
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second (Text
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va (VaSet
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font "Verdana,8,1"
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st "<cell>"
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blo "26600,26500"
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)
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)
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gi *85 (GenericInterface
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ps "CenterOffsetStrategy"
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matrix (Matrix
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text (MLText
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va (VaSet
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isHidden 1
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)
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xt "20000,5000,20000,5000"
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)
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header "Generic Declarations"
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)
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elements [
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]
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)
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portInstanceVis (PortSigDisplay
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sT 1
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sIVOD 1
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)
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portVis (PortSigDisplay
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sIVOD 1
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)
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)
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defaultCptPort (CptPort
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ps "OnEdgeStrategy"
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shape (Triangle
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ro 90
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va (VaSet
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vasetType 1
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,8,0"
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)
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st "In0"
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blo "0,1450"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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)
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thePort (LogicalPort
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lang 11
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decl (Decl
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n "In0"
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t "std_logic_vector"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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defaultCptPortBuffer (CptPort
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ps "OnEdgeStrategy"
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shape (Diamond
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va (VaSet
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vasetType 1
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fg "65535,65535,65535"
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bg "0,0,0"
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)
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)
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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stg "VerticalLayoutStrategy"
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f (Text
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va (VaSet
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font "Verdana,8,0"
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)
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xt "0,750,3500,1650"
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st "Buffer0"
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blo "0,1450"
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tm "CptPortNameMgr"
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)
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)
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dt (MLText
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va (VaSet
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font "Verdana,8,0"
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)
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)
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thePort (LogicalPort
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lang 11
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m 3
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decl (Decl
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n "Buffer0"
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t "std_logic_vector"
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b "(15 DOWNTO 0)"
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o 0
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)
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)
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)
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DeclarativeBlock *86 (SymDeclBlock
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uid 1,0
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stg "SymDeclLayoutStrategy"
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declLabel (Text
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uid 2,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "0,7800,5400,8800"
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st "Declarations"
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blo "0,8600"
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)
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portLabel (Text
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uid 3,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "0,8800,2700,9800"
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st "Ports:"
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blo "0,9600"
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)
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externalLabel (Text
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uid 4,0
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va (VaSet
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font "Verdana,8,1"
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)
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xt "0,13400,2500,14300"
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st "User:"
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blo "0,14100"
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)
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internalLabel (Text
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uid 6,0
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va (VaSet
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isHidden 1
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font "Verdana,8,1"
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)
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xt "0,7800,5800,8800"
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st "Internal User:"
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blo "0,8600"
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)
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externalText (MLText
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uid 5,0
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va (VaSet
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font "Verdana,8,0"
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)
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xt "2000,14300,2000,14300"
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tm "SyDeclarativeTextMgr"
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)
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internalText (MLText
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uid 7,0
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va (VaSet
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isHidden 1
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font "Verdana,8,0"
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)
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xt "18000,7800,18000,7800"
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tm "SyDeclarativeTextMgr"
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)
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)
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lastUid 313,0
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)
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