1
0
mirror of https://github.com/Klagarge/Cursor.git synced 2024-11-23 18:03:27 +00:00
Cursor/Board/hds/@f@p@g@a_cursor/symbol.sb
2021-11-24 10:50:51 +01:00

2730 lines
33 KiB
Plaintext

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t "std_uLogic"
o 9
suid 6,0
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)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,17625,48750,18375"
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tg (CPTG
uid 192,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "41600,17400,47000,18400"
st "sensor1_n"
ju 2
blo "47000,18200"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
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xt "2000,18600,16500,19600"
st "sensor1_n : IN std_uLogic ;"
)
thePort (LogicalPort
decl (Decl
n "sensor1_n"
t "std_uLogic"
o 10
suid 7,0
)
)
)
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uid 195,0
ps "OnEdgeStrategy"
shape (Triangle
uid 196,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,19625,48750,20375"
)
tg (CPTG
uid 197,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 198,0
va (VaSet
)
xt "41600,19400,47000,20400"
st "sensor2_n"
ju 2
blo "47000,20200"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 199,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,19600,16500,20600"
st "sensor2_n : IN std_uLogic ;"
)
thePort (LogicalPort
decl (Decl
n "sensor2_n"
t "std_uLogic"
o 11
suid 8,0
)
)
)
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uid 215,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,9625,48750,10375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
)
xt "42800,9400,47000,10400"
st "motorOn"
ju 2
blo "47000,10200"
tm "CptPortNameMgr"
)
)
dt (MLText
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va (VaSet
font "Verdana,8,0"
)
xt "2000,29600,17000,30600"
st "motorOn : OUT std_uLogic ;"
)
thePort (LogicalPort
m 1
decl (Decl
n "motorOn"
t "std_uLogic"
o 21
suid 9,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,11625,48750,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "44000,11400,47000,12400"
st "side1"
ju 2
blo "47000,12200"
tm "CptPortNameMgr"
)
)
dt (MLText
uid 234,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,30600,16200,31600"
st "side1 : OUT std_uLogic ;"
)
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m 1
decl (Decl
n "side1"
t "std_uLogic"
o 22
suid 11,0
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)
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uid 235,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,13625,48750,14375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "44000,13400,47000,14400"
st "side2"
ju 2
blo "47000,14200"
tm "CptPortNameMgr"
)
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va (VaSet
font "Verdana,8,0"
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xt "2000,31600,15500,32600"
st "side2 : OUT std_uLogic "
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m 1
decl (Decl
n "side2"
t "std_uLogic"
o 23
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "48000,23625,48750,24375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "40400,23400,47000,24400"
st "encoderA_n"
ju 2
blo "47000,24200"
tm "CptPortNameMgr"
)
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xt "2000,11600,16800,12600"
st "encoderA_n : IN std_uLogic ;"
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decl (Decl
n "encoderA_n"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "48000,25625,48750,26375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "40400,25400,47000,26400"
st "encoderB_n"
ju 2
blo "47000,26200"
tm "CptPortNameMgr"
)
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xt "2000,12600,16800,13600"
st "encoderB_n : IN std_uLogic ;"
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decl (Decl
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ps "OnEdgeStrategy"
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "48000,27625,48750,28375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "40400,27400,47000,28400"
st "encoderI_n"
ju 2
blo "47000,28200"
tm "CptPortNameMgr"
)
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va (VaSet
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xt "2000,13600,16600,14600"
st "encoderI_n : IN std_uLogic ;"
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decl (Decl
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "31250,11625,32000,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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xt "33000,11400,36000,12400"
st "go1_n"
blo "33000,12200"
tm "CptPortNameMgr"
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va (VaSet
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xt "2000,14600,16100,15600"
st "go1_n : IN std_uLogic ;"
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decl (Decl
n "go1_n"
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o 6
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "31250,13625,32000,14375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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xt "33000,13400,36000,14400"
st "go2_n"
blo "33000,14200"
tm "CptPortNameMgr"
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va (VaSet
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xt "2000,15600,16100,16600"
st "go2_n : IN std_uLogic ;"
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ps "OnEdgeStrategy"
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ro 90
va (VaSet
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xt "31250,30625,32000,31375"
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tg (CPTG
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va (VaSet
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xt "33000,30400,38400,31400"
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blo "33000,31200"
tm "CptPortNameMgr"
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blo "47000,29200"
tm "CptPortNameMgr"
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blo "47000,30200"
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ro 90
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blo "47000,31200"
tm "CptPortNameMgr"
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ro 90
va (VaSet
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blo "47000,32200"
tm "CptPortNameMgr"
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ro 90
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