From 81b5e547f2f40d1bbfc66ba7d9c7315fb538cb2e Mon Sep 17 00:00:00 2001 From: Klagarge Date: Mon, 18 Mar 2024 13:47:07 +0100 Subject: [PATCH] Initial commit --- .gitignore | 79 + .../Target_1_STM32F746NGHx_2.0.0.dbgconf | 76 + EventRecorderStub.scvd | 9 + RTE/CMSIS/RTX_Config.c | 64 + RTE/CMSIS/RTX_Config.h | 580 +++ RTE/Compiler/EventRecorderConf.h | 34 + RTE/Device/STM32F746NGHx/RTE_Device.h | 3261 +++++++++++++++++ .../STM32F746NGHx/startup_stm32f746xx.s | 483 +++ RTE/Device/STM32F746NGHx/stm32f7xx_hal_conf.h | 596 +++ RTE/Device/STM32F746NGHx/system_stm32f7xx.c | 278 ++ RTE/Hesso_pack/ext_led.c | 224 ++ RTE/Hesso_pack/ext_led.h | 51 + RTE/Hesso_pack/ext_uart.c | 57 + RTE/Hesso_pack/ext_uart.h | 44 + RTE/_Target_1/RTE_Components.h | 49 + lab04-queue.uvprojx | 608 +++ main.c | 135 + 17 files changed, 6628 insertions(+) create mode 100644 .gitignore create mode 100644 DebugConfig/Target_1_STM32F746NGHx_2.0.0.dbgconf create mode 100644 EventRecorderStub.scvd create mode 100644 RTE/CMSIS/RTX_Config.c create mode 100644 RTE/CMSIS/RTX_Config.h create mode 100644 RTE/Compiler/EventRecorderConf.h create mode 100644 RTE/Device/STM32F746NGHx/RTE_Device.h create mode 100644 RTE/Device/STM32F746NGHx/startup_stm32f746xx.s create mode 100644 RTE/Device/STM32F746NGHx/stm32f7xx_hal_conf.h create mode 100644 RTE/Device/STM32F746NGHx/system_stm32f7xx.c create mode 100644 RTE/Hesso_pack/ext_led.c create mode 100644 RTE/Hesso_pack/ext_led.h create mode 100644 RTE/Hesso_pack/ext_uart.c create mode 100644 RTE/Hesso_pack/ext_uart.h create mode 100644 RTE/_Target_1/RTE_Components.h create mode 100644 lab04-queue.uvprojx create mode 100644 main.c diff --git a/.gitignore b/.gitignore new file mode 100644 index 0000000..790c418 --- /dev/null +++ b/.gitignore @@ -0,0 +1,79 @@ +# A .gitignore for Keil projects. +# Taken mostly from http://www.keil.com/support/man/docs/uv4/uv4_b_filetypes.htm + +# User-specific uVision files +*.opt +*.uvopt +*.uvoptx +*.uvgui +*.uvgui.* +*.uvguix.* + +# Listing files +*.cod +*.htm +*.i +*.lst +*.map +*.m51 +*.m66 +# define exception below if needed +*.scr + +# Object and HEX files +*.axf +*.b[0-3][0-9] +*.hex +*.d +*.crf +*.elf +*.hex +*.h86 +*.lib +*.obj +*.o +*.sbr + +# Build files +# define exception below if needed +*.bat +*._ia +*.__i +*._ii + +# Generated output files +/Listings/* +/Objects/* + +# Debugger files +# define exception below if needed +*.ini + +# Other files +*.build_log.htm +*.cdb +*.dep +*.ic +*.lin +*.lnp +*.orc +# define exception below if needed +*.pack +# define exception below if needed +*.pdsc +*.plg +# define exception below if needed +*.sct +*.sfd +*.sfr + +# Miscellaneous +*.tra +*.bin +*.fed +*.l1p +*.l2p +*.iex + +# To explicitly override the above, define any exceptions here; e.g.: +# !my_customized_scatter_file.sct diff --git a/DebugConfig/Target_1_STM32F746NGHx_2.0.0.dbgconf b/DebugConfig/Target_1_STM32F746NGHx_2.0.0.dbgconf new file mode 100644 index 0000000..39e361a --- /dev/null +++ b/DebugConfig/Target_1_STM32F746NGHx_2.0.0.dbgconf @@ -0,0 +1,76 @@ +// File: STM32F74x_75x.dbgconf +// Version: 1.0.0 +// Note: refer to STM32F75xxx STM32F74xxx reference manual (RM0385) +// refer to STM32F75xxx STM32F74xxx datasheets + +// <<< Use Configuration Wizard in Context Menu >>> + +// Debug MCU configuration register (DBGMCU_CR) +// DBG_STANDBY Debug standby mode +// DBG_STOP Debug stop mode +// DBG_SLEEP Debug sleep mode +// +DbgMCU_CR = 0x00000007; + +// Debug MCU APB1 freeze register (DBGMCU_APB1_FZ) +// Reserved bits must be kept at reset value +// DBG_CAN2_STOP Debug CAN2 stopped when core is halted +// DBG_CAN1_STOP Debug CAN1 stopped when core is halted +// DBG_I2C4_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C3_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C2_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_I2C1_SMBUS_TIMEOUT SMBUS timeout mode stopped when core is halted +// DBG_IWDG_STOP Debug independent watchdog stopped when core is halted +// DBG_WWDG_STOP Debug window watchdog stopped when core is halted +// DBG_RTC_STOP RTC stopped when core is halted +// DBG_LPTIM1_STOP LPTMI1 counter stopped when core is halted +// DBG_TIM14_STOP TIM14 counter stopped when core is halted +// DBG_TIM13_STOP TIM13 counter stopped when core is halted +// DBG_TIM12_STOP TIM12 counter stopped when core is halted +// DBG_TIM7_STOP TIM7 counter stopped when core is halted +// DBG_TIM6_STOP TIM6 counter stopped when core is halted +// DBG_TIM5_STOP TIM5 counter stopped when core is halted +// DBG_TIM4_STOP TIM4 counter stopped when core is halted +// DBG_TIM3_STOP TIM3 counter stopped when core is halted +// DBG_TIM2_STOP TIM2 counter stopped when core is halted +// +DbgMCU_APB1_Fz = 0x00000000; + +// Debug MCU APB2 freeze register (DBGMCU_APB2_FZ) +// Reserved bits must be kept at reset value +// DBG_TIM11_STOP TIM11 counter stopped when core is halted +// DBG_TIM10_STOP TIM10 counter stopped when core is halted +// DBG_TIM9_STOP TIM9 counter stopped when core is halted +// DBG_TIM8_STOP TIM8 counter stopped when core is halted +// DBG_TIM1_STOP TIM1 counter stopped when core is halted +// +DbgMCU_APB2_Fz = 0x00000000; + +// TPIU Pin Routing (TRACECLK fixed on Pin PE2) +// TRACECLK: Pin PE2 +// TRACED0 +// ETM Trace Data 0 +// <0x00040003=> Pin PE3 +// <0x00020001=> Pin PC1 +// <0x0006000D=> Pin PG13 +// TRACED1 +// ETM Trace Data 1 +// <0x00040004=> Pin PE4 +// <0x00020008=> Pin PC8 +// <0x0006000E=> Pin PG14 +// TRACED2 +// ETM Trace Data 2 +// <0x00040005=> Pin PE5 +// <0x00030002=> Pin PD2 +// TRACED3 +// ETM Trace Data 3 +// <0x00040006=> Pin PE6 +// <0x0002000C=> Pin PC12 +// +TraceClk_Pin = 0x00040002; +TraceD0_Pin = 0x00040003; +TraceD1_Pin = 0x00040004; +TraceD2_Pin = 0x00040005; +TraceD3_Pin = 0x00040006; + +// <<< end of configuration section >>> diff --git a/EventRecorderStub.scvd b/EventRecorderStub.scvd new file mode 100644 index 0000000..2956b29 --- /dev/null +++ b/EventRecorderStub.scvd @@ -0,0 +1,9 @@ + + + + + + + + + diff --git a/RTE/CMSIS/RTX_Config.c b/RTE/CMSIS/RTX_Config.c new file mode 100644 index 0000000..737078a --- /dev/null +++ b/RTE/CMSIS/RTX_Config.c @@ -0,0 +1,64 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.1.1 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration + * + * ----------------------------------------------------------------------------- + */ + +#include "cmsis_compiler.h" +#include "rtx_os.h" + +// OS Idle Thread +__WEAK __NO_RETURN void osRtxIdleThread (void *argument) { + (void)argument; + + for (;;) {} +} + +// OS Error Callback function +__WEAK uint32_t osRtxErrorNotify (uint32_t code, void *object_id) { + (void)object_id; + + switch (code) { + case osRtxErrorStackOverflow: + // Stack overflow detected for thread (thread_id=object_id) + break; + case osRtxErrorISRQueueOverflow: + // ISR Queue overflow detected when inserting object (object_id) + break; + case osRtxErrorTimerQueueOverflow: + // User Timer Callback Queue overflow detected for timer (timer_id=object_id) + break; + case osRtxErrorClibSpace: + // Standard C/C++ library libspace not available: increase OS_THREAD_LIBSPACE_NUM + break; + case osRtxErrorClibMutex: + // Standard C/C++ library mutex initialization failed + break; + default: + // Reserved + break; + } + for (;;) {} +//return 0U; +} diff --git a/RTE/CMSIS/RTX_Config.h b/RTE/CMSIS/RTX_Config.h new file mode 100644 index 0000000..4d2f501 --- /dev/null +++ b/RTE/CMSIS/RTX_Config.h @@ -0,0 +1,580 @@ +/* + * Copyright (c) 2013-2021 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * ----------------------------------------------------------------------------- + * + * $Revision: V5.5.2 + * + * Project: CMSIS-RTOS RTX + * Title: RTX Configuration definitions + * + * ----------------------------------------------------------------------------- + */ + +#ifndef RTX_CONFIG_H_ +#define RTX_CONFIG_H_ + +#ifdef _RTE_ +#include "RTE_Components.h" +#ifdef RTE_RTX_CONFIG_H +#include RTE_RTX_CONFIG_H +#endif +#endif + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// System Configuration +// ======================= + +// Global Dynamic Memory size [bytes] <0-1073741824:8> +// Defines the combined global dynamic memory size. +// Default: 32768 +#ifndef OS_DYNAMIC_MEM_SIZE +#define OS_DYNAMIC_MEM_SIZE 32768 +#endif + +// Kernel Tick Frequency [Hz] <1-1000000> +// Defines base time unit for delays and timeouts. +// Default: 1000 (1ms tick) +#ifndef OS_TICK_FREQ +#define OS_TICK_FREQ 1000 +#endif + +// Round-Robin Thread switching +// Enables Round-Robin Thread switching. +#ifndef OS_ROBIN_ENABLE +#define OS_ROBIN_ENABLE 1 +#endif + +// Round-Robin Timeout <1-1000> +// Defines how many ticks a thread will execute before a thread switch. +// Default: 5 +#ifndef OS_ROBIN_TIMEOUT +#define OS_ROBIN_TIMEOUT 5 +#endif + +// + +// ISR FIFO Queue +// <4=> 4 entries <8=> 8 entries <12=> 12 entries <16=> 16 entries +// <24=> 24 entries <32=> 32 entries <48=> 48 entries <64=> 64 entries +// <96=> 96 entries <128=> 128 entries <196=> 196 entries <256=> 256 entries +// RTOS Functions called from ISR store requests to this buffer. +// Default: 16 entries +#ifndef OS_ISR_FIFO_QUEUE +#define OS_ISR_FIFO_QUEUE 16 +#endif + +// Object Memory usage counters +// Enables object memory usage counters (requires RTX source variant). +#ifndef OS_OBJ_MEM_USAGE +#define OS_OBJ_MEM_USAGE 0 +#endif + +// + +// Thread Configuration +// ======================= + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_THREAD_OBJ_MEM +#define OS_THREAD_OBJ_MEM 0 +#endif + +// Number of user Threads <1-1000> +// Defines maximum number of user threads that can be active at the same time. +// Applies to user threads with system provided memory for control blocks. +#ifndef OS_THREAD_NUM +#define OS_THREAD_NUM 1 +#endif + +// Number of user Threads with default Stack size <0-1000> +// Defines maximum number of user threads with default stack size. +// Applies to user threads with zero stack size specified. +#ifndef OS_THREAD_DEF_STACK_NUM +#define OS_THREAD_DEF_STACK_NUM 0 +#endif + +// Total Stack size [bytes] for user Threads with user-provided Stack size <0-1073741824:8> +// Defines the combined stack size for user threads with user-provided stack size. +// Applies to user threads with user-provided stack size and system provided memory for stack. +// Default: 0 +#ifndef OS_THREAD_USER_STACK_SIZE +#define OS_THREAD_USER_STACK_SIZE 0 +#endif + +// + +// Default Thread Stack size [bytes] <96-1073741824:8> +// Defines stack size for threads with zero stack size specified. +// Default: 3072 +#ifndef OS_STACK_SIZE +#define OS_STACK_SIZE 3072 +#endif + +// Idle Thread Stack size [bytes] <72-1073741824:8> +// Defines stack size for Idle thread. +// Default: 512 +#ifndef OS_IDLE_THREAD_STACK_SIZE +#define OS_IDLE_THREAD_STACK_SIZE 512 +#endif + +// Idle Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_IDLE_THREAD_TZ_MOD_ID +#define OS_IDLE_THREAD_TZ_MOD_ID 0 +#endif + +// Stack overrun checking +// Enables stack overrun check at thread switch (requires RTX source variant). +// Enabling this option increases slightly the execution time of a thread switch. +#ifndef OS_STACK_CHECK +#define OS_STACK_CHECK 0 +#endif + +// Stack usage watermark +// Initializes thread stack with watermark pattern for analyzing stack usage. +// Enabling this option increases significantly the execution time of thread creation. +#ifndef OS_STACK_WATERMARK +#define OS_STACK_WATERMARK 0 +#endif + +// Processor mode for Thread execution +// <0=> Unprivileged mode +// <1=> Privileged mode +// Default: Privileged mode +#ifndef OS_PRIVILEGE_MODE +#define OS_PRIVILEGE_MODE 1 +#endif + +// + +// Timer Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_TIMER_OBJ_MEM +#define OS_TIMER_OBJ_MEM 0 +#endif + +// Number of Timer objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_TIMER_NUM +#define OS_TIMER_NUM 1 +#endif + +// + +// Timer Thread Priority +// <8=> Low +// <16=> Below Normal <24=> Normal <32=> Above Normal +// <40=> High +// <48=> Realtime +// Defines priority for timer thread +// Default: High +#ifndef OS_TIMER_THREAD_PRIO +#define OS_TIMER_THREAD_PRIO 40 +#endif + +// Timer Thread Stack size [bytes] <0-1073741824:8> +// Defines stack size for Timer thread. +// May be set to 0 when timers are not used. +// Default: 512 +#ifndef OS_TIMER_THREAD_STACK_SIZE +#define OS_TIMER_THREAD_STACK_SIZE 512 +#endif + +// Timer Thread TrustZone Module Identifier +// Defines TrustZone Thread Context Management Identifier. +// Applies only to cores with TrustZone technology. +// Default: 0 (not used) +#ifndef OS_TIMER_THREAD_TZ_MOD_ID +#define OS_TIMER_THREAD_TZ_MOD_ID 0 +#endif + +// Timer Callback Queue entries <0-256> +// Number of concurrent active timer callback functions. +// May be set to 0 when timers are not used. +// Default: 4 +#ifndef OS_TIMER_CB_QUEUE +#define OS_TIMER_CB_QUEUE 4 +#endif + +// + +// Event Flags Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_EVFLAGS_OBJ_MEM +#define OS_EVFLAGS_OBJ_MEM 0 +#endif + +// Number of Event Flags objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_EVFLAGS_NUM +#define OS_EVFLAGS_NUM 1 +#endif + +// + +// + +// Mutex Configuration +// ====================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MUTEX_OBJ_MEM +#define OS_MUTEX_OBJ_MEM 0 +#endif + +// Number of Mutex objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MUTEX_NUM +#define OS_MUTEX_NUM 1 +#endif + +// + +// + +// Semaphore Configuration +// ========================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_SEMAPHORE_OBJ_MEM +#define OS_SEMAPHORE_OBJ_MEM 0 +#endif + +// Number of Semaphore objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_SEMAPHORE_NUM +#define OS_SEMAPHORE_NUM 1 +#endif + +// + +// + +// Memory Pool Configuration +// ============================ + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MEMPOOL_OBJ_MEM +#define OS_MEMPOOL_OBJ_MEM 0 +#endif + +// Number of Memory Pool objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MEMPOOL_NUM +#define OS_MEMPOOL_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MEMPOOL_DATA_SIZE +#define OS_MEMPOOL_DATA_SIZE 0 +#endif + +// + +// + +// Message Queue Configuration +// ============================== + +// Object specific Memory allocation +// Enables object specific memory allocation. +#ifndef OS_MSGQUEUE_OBJ_MEM +#define OS_MSGQUEUE_OBJ_MEM 0 +#endif + +// Number of Message Queue objects <1-1000> +// Defines maximum number of objects that can be active at the same time. +// Applies to objects with system provided memory for control blocks. +#ifndef OS_MSGQUEUE_NUM +#define OS_MSGQUEUE_NUM 1 +#endif + +// Data Storage Memory size [bytes] <0-1073741824:8> +// Defines the combined data storage memory size. +// Applies to objects with system provided memory for data storage. +// Default: 0 +#ifndef OS_MSGQUEUE_DATA_SIZE +#define OS_MSGQUEUE_DATA_SIZE 0 +#endif + +// + +// + +// Event Recorder Configuration +// =============================== + +// Global Initialization +// Initialize Event Recorder during 'osKernelInitialize'. +#ifndef OS_EVR_INIT +#define OS_EVR_INIT 0 +#endif + +// Start recording +// Start event recording after initialization. +#ifndef OS_EVR_START +#define OS_EVR_START 1 +#endif + +// Global Event Filter Setup +// Initial recording level applied to all components. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_LEVEL +#define OS_EVR_LEVEL 0x00U +#endif + +// RTOS Event Filter Setup +// Recording levels for RTX components. +// Only applicable if events for the respective component are generated. + +// Memory Management +// Recording level for Memory Management events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMORY_LEVEL +#define OS_EVR_MEMORY_LEVEL 0x81U +#endif + +// Kernel +// Recording level for Kernel events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_KERNEL_LEVEL +#define OS_EVR_KERNEL_LEVEL 0x81U +#endif + +// Thread +// Recording level for Thread events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THREAD_LEVEL +#define OS_EVR_THREAD_LEVEL 0x85U +#endif + +// Generic Wait +// Recording level for Generic Wait events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_WAIT_LEVEL +#define OS_EVR_WAIT_LEVEL 0x81U +#endif + +// Thread Flags +// Recording level for Thread Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_THFLAGS_LEVEL +#define OS_EVR_THFLAGS_LEVEL 0x81U +#endif + +// Event Flags +// Recording level for Event Flags events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_EVFLAGS_LEVEL +#define OS_EVR_EVFLAGS_LEVEL 0x81U +#endif + +// Timer +// Recording level for Timer events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_TIMER_LEVEL +#define OS_EVR_TIMER_LEVEL 0x81U +#endif + +// Mutex +// Recording level for Mutex events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MUTEX_LEVEL +#define OS_EVR_MUTEX_LEVEL 0x81U +#endif + +// Semaphore +// Recording level for Semaphore events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_SEMAPHORE_LEVEL +#define OS_EVR_SEMAPHORE_LEVEL 0x81U +#endif + +// Memory Pool +// Recording level for Memory Pool events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MEMPOOL_LEVEL +#define OS_EVR_MEMPOOL_LEVEL 0x81U +#endif + +// Message Queue +// Recording level for Message Queue events. +// Error events +// API function call events +// Operation events +// Detailed operation events +// +#ifndef OS_EVR_MSGQUEUE_LEVEL +#define OS_EVR_MSGQUEUE_LEVEL 0x81U +#endif + +// + +// + +// RTOS Event Generation +// Enables event generation for RTX components (requires RTX source variant). + +// Memory Management +// Enables Memory Management event generation. +#ifndef OS_EVR_MEMORY +#define OS_EVR_MEMORY 1 +#endif + +// Kernel +// Enables Kernel event generation. +#ifndef OS_EVR_KERNEL +#define OS_EVR_KERNEL 1 +#endif + +// Thread +// Enables Thread event generation. +#ifndef OS_EVR_THREAD +#define OS_EVR_THREAD 1 +#endif + +// Generic Wait +// Enables Generic Wait event generation. +#ifndef OS_EVR_WAIT +#define OS_EVR_WAIT 1 +#endif + +// Thread Flags +// Enables Thread Flags event generation. +#ifndef OS_EVR_THFLAGS +#define OS_EVR_THFLAGS 1 +#endif + +// Event Flags +// Enables Event Flags event generation. +#ifndef OS_EVR_EVFLAGS +#define OS_EVR_EVFLAGS 1 +#endif + +// Timer +// Enables Timer event generation. +#ifndef OS_EVR_TIMER +#define OS_EVR_TIMER 1 +#endif + +// Mutex +// Enables Mutex event generation. +#ifndef OS_EVR_MUTEX +#define OS_EVR_MUTEX 1 +#endif + +// Semaphore +// Enables Semaphore event generation. +#ifndef OS_EVR_SEMAPHORE +#define OS_EVR_SEMAPHORE 1 +#endif + +// Memory Pool +// Enables Memory Pool event generation. +#ifndef OS_EVR_MEMPOOL +#define OS_EVR_MEMPOOL 1 +#endif + +// Message Queue +// Enables Message Queue event generation. +#ifndef OS_EVR_MSGQUEUE +#define OS_EVR_MSGQUEUE 1 +#endif + +// + +// + +// Number of Threads which use standard C/C++ library libspace +// (when thread specific memory allocation is not used). +#if (OS_THREAD_OBJ_MEM == 0) +#ifndef OS_THREAD_LIBSPACE_NUM +#define OS_THREAD_LIBSPACE_NUM 4 +#endif +#else +#define OS_THREAD_LIBSPACE_NUM OS_THREAD_NUM +#endif + +//------------- <<< end of configuration section >>> --------------------------- + +#endif // RTX_CONFIG_H_ diff --git a/RTE/Compiler/EventRecorderConf.h b/RTE/Compiler/EventRecorderConf.h new file mode 100644 index 0000000..210af0f --- /dev/null +++ b/RTE/Compiler/EventRecorderConf.h @@ -0,0 +1,34 @@ +/*------------------------------------------------------------------------------ + * MDK - Component ::Event Recorder + * Copyright (c) 2016-2018 ARM Germany GmbH. All rights reserved. + *------------------------------------------------------------------------------ + * Name: EventRecorderConf.h + * Purpose: Event Recorder Configuration + * Rev.: V1.1.0 + *----------------------------------------------------------------------------*/ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +// Event Recorder + +// Number of Records +// <8=>8 <16=>16 <32=>32 <64=>64 <128=>128 <256=>256 <512=>512 <1024=>1024 +// <2048=>2048 <4096=>4096 <8192=>8192 <16384=>16384 <32768=>32768 +// <65536=>65536 +// Configures size of Event Record Buffer (each record is 16 bytes) +// Must be 2^n (min=8, max=65536) +#define EVENT_RECORD_COUNT 1024U + +// Time Stamp Source +// <0=> DWT Cycle Counter <1=> SysTick <2=> CMSIS-RTOS2 System Timer +// <3=> User Timer (Normal Reset) <4=> User Timer (Power-On Reset) +// Selects source for 32-bit time stamp +#define EVENT_TIMESTAMP_SOURCE 0 + +// Time Stamp Clock Frequency [Hz] <0-1000000000> +// Defines initial time stamp clock frequency (0 when not used) +#define EVENT_TIMESTAMP_FREQ 0U + +// + +//------------- <<< end of configuration section >>> --------------------------- diff --git a/RTE/Device/STM32F746NGHx/RTE_Device.h b/RTE/Device/STM32F746NGHx/RTE_Device.h new file mode 100644 index 0000000..8fef49c --- /dev/null +++ b/RTE/Device/STM32F746NGHx/RTE_Device.h @@ -0,0 +1,3261 @@ +/* ----------------------------------------------------------------------------- + * Copyright (c) 2013-2019 Arm Limited (or its affiliates). All + * rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + * + * $Date: 17. June 2019 + * $Revision: V1.5.1 + * + * Project: RTE Device Configuration for ST STM32F7xx + * -------------------------------------------------------------------------- */ + +//-------- <<< Use Configuration Wizard in Context Menu >>> -------------------- + +#ifndef __RTE_DEVICE_H +#define __RTE_DEVICE_H + + +#define GPIO_PORT0 GPIOA +#define GPIO_PORT1 GPIOB +#define GPIO_PORT2 GPIOC +#define GPIO_PORT3 GPIOD +#define GPIO_PORT4 GPIOE +#define GPIO_PORT5 GPIOF +#define GPIO_PORT6 GPIOG +#define GPIO_PORT7 GPIOH +#define GPIO_PORT8 GPIOI +#define GPIO_PORT9 GPIOJ +#define GPIO_PORT10 GPIOK + +#define GPIO_PORT(num) GPIO_PORT##num + + +// USART1 (Universal synchronous asynchronous receiver transmitter) [Driver_USART1] +// Configuration settings for Driver_USART1 in component ::CMSIS Driver:USART +#define RTE_USART1 0 + +// USART1_TX Pin <0=>Not Used <1=>PA9 <2=>PB6 <3=>PB14 +#define RTE_USART1_TX_ID 0 +#if (RTE_USART1_TX_ID == 0) +#define RTE_USART1_TX 0 +#elif (RTE_USART1_TX_ID == 1) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOA +#define RTE_USART1_TX_BIT 9 +#elif (RTE_USART1_TX_ID == 2) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 6 +#elif (RTE_USART1_TX_ID == 3) +#define RTE_USART1_TX 1 +#define RTE_USART1_TX_PORT GPIOB +#define RTE_USART1_TX_BIT 14 +#else +#error "Invalid USART1_TX Pin Configuration!" +#endif + +// USART1_RX Pin <0=>Not Used <1=>PA10 <2=>PB7 <3=>PB15 +#define RTE_USART1_RX_ID 0 +#if (RTE_USART1_RX_ID == 0) +#define RTE_USART1_RX 0 +#elif (RTE_USART1_RX_ID == 1) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOA +#define RTE_USART1_RX_BIT 10 +#elif (RTE_USART1_RX_ID == 2) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 7 +#elif (RTE_USART1_RX_ID == 3) +#define RTE_USART1_RX 1 +#define RTE_USART1_RX_PORT GPIOB +#define RTE_USART1_RX_BIT 15 +#else +#error "Invalid USART1_RX Pin Configuration!" +#endif + +// USART1_CK Pin <0=>Not Used <1=>PA8 +#define RTE_USART1_CK_ID 0 +#if (RTE_USART1_CK_ID == 0) +#define RTE_USART1_CK 0 +#elif (RTE_USART1_CK_ID == 1) +#define RTE_USART1_CK 1 +#define RTE_USART1_CK_PORT GPIOA +#define RTE_USART1_CK_BIT 8 +#else +#error "Invalid USART1_CK Pin Configuration!" +#endif + +// USART1_CTS Pin <0=>Not Used <1=>PA11 +#define RTE_USART1_CTS_ID 0 +#if (RTE_USART1_CTS_ID == 0) +#define RTE_USART1_CTS 0 +#elif (RTE_USART1_CTS_ID == 1) +#define RTE_USART1_CTS 1 +#define RTE_USART1_CTS_PORT GPIOA +#define RTE_USART1_CTS_BIT 11 +#else +#error "Invalid USART1_CTS Pin Configuration!" +#endif + +// USART1_RTS Pin <0=>Not Used <1=>PA12 +#define RTE_USART1_RTS_ID 0 +#if (RTE_USART1_RTS_ID == 0) +#define RTE_USART1_RTS 0 +#elif (RTE_USART1_RTS_ID == 1) +#define RTE_USART1_RTS 1 +#define RTE_USART1_RTS_PORT GPIOA +#define RTE_USART1_RTS_BIT 12 +#else +#error "Invalid USART1_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <2=>2 <5=>5 +// Selects DMA Stream (only Stream 2 or 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_RX_DMA 0 +#define RTE_USART1_RX_DMA_NUMBER 2 +#define RTE_USART1_RX_DMA_STREAM 2 +#define RTE_USART1_RX_DMA_CHANNEL 4 +#define RTE_USART1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART1_TX_DMA 0 +#define RTE_USART1_TX_DMA_NUMBER 2 +#define RTE_USART1_TX_DMA_STREAM 7 +#define RTE_USART1_TX_DMA_CHANNEL 4 +#define RTE_USART1_TX_DMA_PRIORITY 0 + +// + + +// USART2 (Universal synchronous asynchronous receiver transmitter) [Driver_USART2] +// Configuration settings for Driver_USART2 in component ::CMSIS Driver:USART +#define RTE_USART2 0 + +// USART2_TX Pin <0=>Not Used <1=>PA2 <2=>PD5 +#define RTE_USART2_TX_ID 0 +#if (RTE_USART2_TX_ID == 0) +#define RTE_USART2_TX 0 +#elif (RTE_USART2_TX_ID == 1) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOA +#define RTE_USART2_TX_BIT 2 +#elif (RTE_USART2_TX_ID == 2) +#define RTE_USART2_TX 1 +#define RTE_USART2_TX_PORT GPIOD +#define RTE_USART2_TX_BIT 5 +#else +#error "Invalid USART2_TX Pin Configuration!" +#endif + +// USART2_RX Pin <0=>Not Used <1=>PA3 <2=>PD6 +#define RTE_USART2_RX_ID 0 +#if (RTE_USART2_RX_ID == 0) +#define RTE_USART2_RX 0 +#elif (RTE_USART2_RX_ID == 1) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOA +#define RTE_USART2_RX_BIT 3 +#elif (RTE_USART2_RX_ID == 2) +#define RTE_USART2_RX 1 +#define RTE_USART2_RX_PORT GPIOD +#define RTE_USART2_RX_BIT 6 +#else +#error "Invalid USART2_RX Pin Configuration!" +#endif + +// USART2_CK Pin <0=>Not Used <1=>PA4 <2=>PD7 +#define RTE_USART2_CK_ID 0 +#if (RTE_USART2_CK_ID == 0) +#define RTE_USART2_CK 0 +#elif (RTE_USART2_CK_ID == 1) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOA +#define RTE_USART2_CK_BIT 4 +#elif (RTE_USART2_CK_ID == 2) +#define RTE_USART2_CK 1 +#define RTE_USART2_CK_PORT GPIOD +#define RTE_USART2_CK_BIT 7 +#else +#error "Invalid USART2_CK Pin Configuration!" +#endif + +// USART2_CTS Pin <0=>Not Used <1=>PA0 <2=>PD3 +#define RTE_USART2_CTS_ID 0 +#if (RTE_USART2_CTS_ID == 0) +#define RTE_USART2_CTS 0 +#elif (RTE_USART2_CTS_ID == 1) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOA +#define RTE_USART2_CTS_BIT 0 +#elif (RTE_USART2_CTS_ID == 2) +#define RTE_USART2_CTS 1 +#define RTE_USART2_CTS_PORT GPIOD +#define RTE_USART2_CTS_BIT 3 +#else +#error "Invalid USART2_CTS Pin Configuration!" +#endif + +// USART2_RTS Pin <0=>Not Used <1=>PA1 <2=>PD4 +#define RTE_USART2_RTS_ID 0 +#if (RTE_USART2_RTS_ID == 0) +#define RTE_USART2_RTS 0 +#elif (RTE_USART2_RTS_ID == 1) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOA +#define RTE_USART2_RTS_BIT 1 +#elif (RTE_USART2_RTS_ID == 2) +#define RTE_USART2_RTS 1 +#define RTE_USART2_RTS_PORT GPIOD +#define RTE_USART2_RTS_BIT 4 +#else +#error "Invalid USART2_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_RX_DMA 0 +#define RTE_USART2_RX_DMA_NUMBER 1 +#define RTE_USART2_RX_DMA_STREAM 5 +#define RTE_USART2_RX_DMA_CHANNEL 4 +#define RTE_USART2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART2_TX_DMA 0 +#define RTE_USART2_TX_DMA_NUMBER 1 +#define RTE_USART2_TX_DMA_STREAM 6 +#define RTE_USART2_TX_DMA_CHANNEL 4 +#define RTE_USART2_TX_DMA_PRIORITY 0 + +// + + +// USART3 (Universal synchronous asynchronous receiver transmitter) [Driver_USART3] +// Configuration settings for Driver_USART3 in component ::CMSIS Driver:USART +#define RTE_USART3 0 + +// USART3_TX Pin <0=>Not Used <1=>PB10 <2=>PC10 <3=>PD8 +#define RTE_USART3_TX_ID 0 +#if (RTE_USART3_TX_ID == 0) +#define RTE_USART3_TX 0 +#elif (RTE_USART3_TX_ID == 1) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOB +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 2) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOC +#define RTE_USART3_TX_BIT 10 +#elif (RTE_USART3_TX_ID == 3) +#define RTE_USART3_TX 1 +#define RTE_USART3_TX_PORT GPIOD +#define RTE_USART3_TX_BIT 8 +#else +#error "Invalid USART3_TX Pin Configuration!" +#endif + +// USART3_RX Pin <0=>Not Used <1=>PB11 <2=>PC11 <3=>PD9 +#define RTE_USART3_RX_ID 0 +#if (RTE_USART3_RX_ID == 0) +#define RTE_USART3_RX 0 +#elif (RTE_USART3_RX_ID == 1) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOB +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 2) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOC +#define RTE_USART3_RX_BIT 11 +#elif (RTE_USART3_RX_ID == 3) +#define RTE_USART3_RX 1 +#define RTE_USART3_RX_PORT GPIOD +#define RTE_USART3_RX_BIT 9 +#else +#error "Invalid USART3_RX Pin Configuration!" +#endif + +// USART3_CK Pin <0=>Not Used <1=>PB12 <2=>PC12 <3=>PD10 +#define RTE_USART3_CK_ID 0 +#if (RTE_USART3_CK_ID == 0) +#define RTE_USART3_CK 0 +#elif (RTE_USART3_CK_ID == 1) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOB +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 2) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOC +#define RTE_USART3_CK_BIT 12 +#elif (RTE_USART3_CK_ID == 3) +#define RTE_USART3_CK 1 +#define RTE_USART3_CK_PORT GPIOD +#define RTE_USART3_CK_BIT 10 +#else +#error "Invalid USART3_CK Pin Configuration!" +#endif + +// USART3_CTS Pin <0=>Not Used <1=>PB13 <2=>PD11 +#define RTE_USART3_CTS_ID 0 +#if (RTE_USART3_CTS_ID == 0) +#define RTE_USART3_CTS 0 +#elif (RTE_USART3_CTS_ID == 1) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOB +#define RTE_USART3_CTS_BIT 13 +#elif (RTE_USART3_CTS_ID == 2) +#define RTE_USART3_CTS 1 +#define RTE_USART3_CTS_PORT GPIOD +#define RTE_USART3_CTS_BIT 11 +#else +#error "Invalid USART3_CTS Pin Configuration!" +#endif + +// USART3_RTS Pin <0=>Not Used <1=>PB14 <2=>PD12 +#define RTE_USART3_RTS_ID 0 +#if (RTE_USART3_RTS_ID == 0) +#define RTE_USART3_RTS 0 +#elif (RTE_USART3_RTS_ID == 1) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOB +#define RTE_USART3_RTS_BIT 14 +#elif (RTE_USART3_RTS_ID == 2) +#define RTE_USART3_RTS 1 +#define RTE_USART3_RTS_PORT GPIOD +#define RTE_USART3_RTS_BIT 12 +#else +#error "Invalid USART3_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_RX_DMA 0 +#define RTE_USART3_RX_DMA_NUMBER 1 +#define RTE_USART3_RX_DMA_STREAM 1 +#define RTE_USART3_RX_DMA_CHANNEL 4 +#define RTE_USART3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 <4=>4 +// Selects DMA Stream (only Stream 3 or 4 can be used) +// Channel <4=>4 <7=>7 +// Selects DMA Channel (only Channel 4 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART3_TX_DMA 0 +#define RTE_USART3_TX_DMA_NUMBER 1 +#define RTE_USART3_TX_DMA_STREAM 3 +#define RTE_USART3_TX_DMA_CHANNEL 4 +#define RTE_USART3_TX_DMA_PRIORITY 0 + +// + + +// UART4 (Universal asynchronous receiver transmitter) [Driver_USART4] +// Configuration settings for Driver_USART4 in component ::CMSIS Driver:USART +#define RTE_UART4 0 + +// UART4_TX Pin <0=>Not Used <1=>PA0 <2=>PC10 <3=>PA12 <4=>PD1 <5=>PH13 +#define RTE_UART4_TX_ID 0 +#if (RTE_UART4_TX_ID == 0) +#define RTE_UART4_TX 0 +#elif (RTE_UART4_TX_ID == 1) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 0 +#elif (RTE_UART4_TX_ID == 2) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOC +#define RTE_UART4_TX_BIT 10 +#elif (RTE_UART4_TX_ID == 3) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOA +#define RTE_UART4_TX_BIT 12 +#elif (RTE_UART4_TX_ID == 4) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOD +#define RTE_UART4_TX_BIT 1 +#elif (RTE_UART4_TX_ID == 5) +#define RTE_UART4_TX 1 +#define RTE_UART4_TX_PORT GPIOH +#define RTE_UART4_TX_BIT 13 +#else +#error "Invalid UART4_TX Pin Configuration!" +#endif + +// UART4_RX Pin <0=>Not Used <1=>PA1 <2=>PC11 <3=>PA11 <4=>PD0 <5=>PH14 <6=>PI9 +#define RTE_UART4_RX_ID 0 +#if (RTE_UART4_RX_ID == 0) +#define RTE_UART4_RX 0 +#elif (RTE_UART4_RX_ID == 1) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 1 +#elif (RTE_UART4_RX_ID == 2) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOC +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 3) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOA +#define RTE_UART4_RX_BIT 11 +#elif (RTE_UART4_RX_ID == 4) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOD +#define RTE_UART4_RX_BIT 0 +#elif (RTE_UART4_RX_ID == 5) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOH +#define RTE_UART4_RX_BIT 14 +#elif (RTE_UART4_RX_ID == 6) +#define RTE_UART4_RX 1 +#define RTE_UART4_RX_PORT GPIOI +#define RTE_UART4_RX_BIT 9 +#else +#error "Invalid UART4_RX Pin Configuration!" +#endif + +// UART4_CTS Pin <0=>Not Used <1=>PB0 <2=>PB15 +#define RTE_UART4_CTS_ID 0 +#if (RTE_UART4_CTS_ID == 0) +#define RTE_UART4_CTS 0 +#elif (RTE_UART4_CTS_ID == 1) +#define RTE_UART4_CTS 1 +#define RTE_UART4_CTS_PORT GPIOB +#define RTE_UART4_CTS_BIT 0 +#elif (RTE_UART4_CTS_ID == 2) +#define RTE_UART4_CTS 1 +#define RTE_UART4_CTS_PORT GPIOB +#define RTE_UART4_CTS_BIT 15 +#else +#error "Invalid UART4_CTS Pin Configuration!" +#endif + +// UART4_RTS Pin <0=>Not Used <1=>PA15 <2=>PB14 +#define RTE_UART4_RTS_ID 0 +#if (RTE_UART4_RTS_ID == 0) +#define RTE_UART4_RTS 0 +#elif (RTE_UART4_RTS_ID == 1) +#define RTE_UART4_RTS 1 +#define RTE_UART4_RTS_PORT GPIOA +#define RTE_UART4_RTS_BIT 15 +#elif (RTE_UART4_RTS_ID == 2) +#define RTE_UART4_RTS 1 +#define RTE_UART4_RTS_PORT GPIOB +#define RTE_UART4_RTS_BIT 14 +#else +#error "Invalid UART4_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_RX_DMA 0 +#define RTE_UART4_RX_DMA_NUMBER 1 +#define RTE_UART4_RX_DMA_STREAM 2 +#define RTE_UART4_RX_DMA_CHANNEL 4 +#define RTE_UART4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART4_TX_DMA 0 +#define RTE_UART4_TX_DMA_NUMBER 1 +#define RTE_UART4_TX_DMA_STREAM 4 +#define RTE_UART4_TX_DMA_CHANNEL 4 +#define RTE_UART4_TX_DMA_PRIORITY 0 + +// + + +// UART5 (Universal asynchronous receiver transmitter) [Driver_USART5] +// Configuration settings for Driver_USART5 in component ::CMSIS Driver:USART +#define RTE_UART5 0 + +// UART5_TX Pin <0=>Not Used <1=>PC12 <2=>PB6 <3=>PB9 <4=>PB13 +#define RTE_UART5_TX_ID 0 +#if (RTE_UART5_TX_ID == 0) +#define RTE_UART5_TX 0 +#elif (RTE_UART5_TX_ID == 1) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOC +#define RTE_UART5_TX_BIT 12 +#elif (RTE_UART5_TX_ID == 2) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 6 +#elif (RTE_UART5_TX_ID == 3) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 9 +#elif (RTE_UART5_TX_ID == 4) +#define RTE_UART5_TX 1 +#define RTE_UART5_TX_PORT GPIOB +#define RTE_UART5_TX_BIT 13 +#else +#error "Invalid UART5_TX Pin Configuration!" +#endif + +// UART5_RX Pin <0=>Not Used <1=>PD2 <2=>PB5 <3=>PB8 <4=>PB12 +#define RTE_UART5_RX_ID 0 +#if (RTE_UART5_RX_ID == 0) +#define RTE_UART5_RX 0 +#elif (RTE_UART5_RX_ID == 1) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOD +#define RTE_UART5_RX_BIT 2 +#elif (RTE_UART5_RX_ID == 2) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOB +#define RTE_UART5_RX_BIT 5 +#elif (RTE_UART5_RX_ID == 3) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOB +#define RTE_UART5_RX_BIT 8 +#elif (RTE_UART5_RX_ID == 4) +#define RTE_UART5_RX 1 +#define RTE_UART5_RX_PORT GPIOB +#define RTE_UART5_RX_BIT 12 +#else +#error "Invalid UART5_RX Pin Configuration!" +#endif + +// UART5_CTS Pin <0=>Not Used <1=>PC9 +#define RTE_UART5_CTS_ID 0 +#if (RTE_UART5_CTS_ID == 0) +#define RTE_UART5_CTS 0 +#elif (RTE_UART5_CTS_ID == 1) +#define RTE_UART5_CTS 1 +#define RTE_UART5_CTS_PORT GPIOC +#define RTE_UART5_CTS_BIT 9 +#else +#error "Invalid UART5_CTS Pin Configuration!" +#endif + +// UART5_RTS Pin <0=>Not Used <1=>PC8 +#define RTE_UART5_RTS_ID 0 +#if (RTE_UART5_RTS_ID == 0) +#define RTE_UART5_RTS 0 +#elif (RTE_UART5_RTS_ID == 1) +#define RTE_UART5_RTS 1 +#define RTE_UART5_RTS_PORT GPIOC +#define RTE_UART5_RTS_BIT 8 +#else +#error "Invalid UART5_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_RX_DMA 0 +#define RTE_UART5_RX_DMA_NUMBER 1 +#define RTE_UART5_RX_DMA_STREAM 0 +#define RTE_UART5_RX_DMA_CHANNEL 4 +#define RTE_UART5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART5_TX_DMA 0 +#define RTE_UART5_TX_DMA_NUMBER 1 +#define RTE_UART5_TX_DMA_STREAM 7 +#define RTE_UART5_TX_DMA_CHANNEL 4 +#define RTE_UART5_TX_DMA_PRIORITY 0 + +// + + +// USART6 (Universal synchronous asynchronous receiver transmitter) [Driver_USART6] +// Configuration settings for Driver_USART6 in component ::CMSIS Driver:USART +#define RTE_USART6 0 + +// USART6_TX Pin <0=>Not Used <1=>PC6 <2=>PG14 +#define RTE_USART6_TX_ID 0 +#if (RTE_USART6_TX_ID == 0) +#define RTE_USART6_TX 0 +#elif (RTE_USART6_TX_ID == 1) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOC +#define RTE_USART6_TX_BIT 6 +#elif (RTE_USART6_TX_ID == 2) +#define RTE_USART6_TX 1 +#define RTE_USART6_TX_PORT GPIOG +#define RTE_USART6_TX_BIT 14 +#else +#error "Invalid USART6_TX Pin Configuration!" +#endif + +// USART6_RX Pin <0=>Not Used <1=>PC7 <2=>PG9 +#define RTE_USART6_RX_ID 0 +#if (RTE_USART6_RX_ID == 0) +#define RTE_USART6_RX 0 +#elif (RTE_USART6_RX_ID == 1) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOC +#define RTE_USART6_RX_BIT 7 +#elif (RTE_USART6_RX_ID == 2) +#define RTE_USART6_RX 1 +#define RTE_USART6_RX_PORT GPIOG +#define RTE_USART6_RX_BIT 9 +#else +#error "Invalid USART6_RX Pin Configuration!" +#endif + +// USART6_CK Pin <0=>Not Used <1=>PC8 <2=>PG7 +#define RTE_USART6_CK_ID 0 +#if (RTE_USART6_CK_ID == 0) +#define RTE_USART6_CK 0 +#elif (RTE_USART6_CK_ID == 1) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOC +#define RTE_USART6_CK_BIT 8 +#elif (RTE_USART6_CK_ID == 2) +#define RTE_USART6_CK 1 +#define RTE_USART6_CK_PORT GPIOG +#define RTE_USART6_CK_BIT 7 +#else +#error "Invalid USART6_CK Pin Configuration!" +#endif + +// USART6_CTS Pin <0=>Not Used <1=>PG13 <2=>PG15 +#define RTE_USART6_CTS_ID 0 +#if (RTE_USART6_CTS_ID == 0) +#define RTE_USART6_CTS 0 +#elif (RTE_USART6_CTS_ID == 1) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 13 +#elif (RTE_USART6_CTS_ID == 2) +#define RTE_USART6_CTS 1 +#define RTE_USART6_CTS_PORT GPIOG +#define RTE_USART6_CTS_BIT 15 +#else +#error "Invalid USART6_CTS Pin Configuration!" +#endif + +// USART6_RTS Pin <0=>Not Used <1=>PG8 <2=>PG12 +#define RTE_USART6_RTS_ID 0 +#if (RTE_USART6_RTS_ID == 0) +#define RTE_USART6_RTS 0 +#elif (RTE_USART6_RTS_ID == 1) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 8 +#elif (RTE_USART6_RTS_ID == 2) +#define RTE_USART6_RTS 1 +#define RTE_USART6_RTS_PORT GPIOG +#define RTE_USART6_RTS_BIT 12 +#else +#error "Invalid USART6_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_RX_DMA 0 +#define RTE_USART6_RX_DMA_NUMBER 2 +#define RTE_USART6_RX_DMA_STREAM 1 +#define RTE_USART6_RX_DMA_CHANNEL 5 +#define RTE_USART6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_USART6_TX_DMA 0 +#define RTE_USART6_TX_DMA_NUMBER 2 +#define RTE_USART6_TX_DMA_STREAM 6 +#define RTE_USART6_TX_DMA_CHANNEL 5 +#define RTE_USART6_TX_DMA_PRIORITY 0 + +// + +// UART7 (Universal asynchronous receiver transmitter) [Driver_USART7] +// Configuration settings for Driver_USART7 in component ::CMSIS Driver:USART +#define RTE_UART7 0 + +// UART7_TX Pin <0=>Not Used <1=>PF7 <2=>PE8 <3=>PA15 <4=>PB4 +#define RTE_UART7_TX_ID 0 +#if (RTE_UART7_TX_ID == 0) +#define RTE_UART7_TX 0 +#elif (RTE_UART7_TX_ID == 1) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOF +#define RTE_UART7_TX_BIT 7 +#elif (RTE_UART7_TX_ID == 2) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOE +#define RTE_UART7_TX_BIT 8 +#elif (RTE_UART7_TX_ID == 3) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOA +#define RTE_UART7_TX_BIT 15 +#elif (RTE_UART7_TX_ID == 4) +#define RTE_UART7_TX 1 +#define RTE_UART7_TX_PORT GPIOB +#define RTE_UART7_TX_BIT 4 +#else +#error "Invalid UART7_TX Pin Configuration!" +#endif + +// UART7_RX Pin <0=>Not Used <1=>PF6 <2=>PE7 <3=>PA8 <4=>PB3 +#define RTE_UART7_RX_ID 0 +#if (RTE_UART7_RX_ID == 0) +#define RTE_UART7_RX 0 +#elif (RTE_UART7_RX_ID == 1) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOF +#define RTE_UART7_RX_BIT 6 +#elif (RTE_UART7_RX_ID == 2) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOE +#define RTE_UART7_RX_BIT 7 +#elif (RTE_UART7_RX_ID == 3) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOA +#define RTE_UART7_RX_BIT 8 +#elif (RTE_UART7_RX_ID == 4) +#define RTE_UART7_RX 1 +#define RTE_UART7_RX_PORT GPIOB +#define RTE_UART7_RX_BIT 3 +#else +#error "Invalid UART7_RX Pin Configuration!" +#endif + +// UART7_CTS Pin <0=>Not Used <1=>PF9 <2=>PE10 +#define RTE_UART7_CTS_ID 0 +#if (RTE_UART7_CTS_ID == 0) +#define RTE_UART7_CTS 0 +#elif (RTE_UART7_CTS_ID == 1) +#define RTE_UART7_CTS 1 +#define RTE_UART7_CTS_PORT GPIOF +#define RTE_UART7_CTS_BIT 9 +#elif (RTE_UART7_CTS_ID == 2) +#define RTE_UART7_CTS 1 +#define RTE_UART7_CTS_PORT GPIOE +#define RTE_UART7_CTS_BIT 10 +#else +#error "Invalid UART7_CTS Pin Configuration!" +#endif + +// UART7_RTS Pin <0=>Not Used <1=>PF8 <2=>PE9 +#define RTE_UART7_RTS_ID 0 +#if (RTE_UART7_RTS_ID == 0) +#define RTE_UART7_RTS 0 +#elif (RTE_UART7_RTS_ID == 1) +#define RTE_UART7_RTS 1 +#define RTE_UART7_RTS_PORT GPIOF +#define RTE_UART7_RTS_BIT 8 +#elif (RTE_UART7_RTS_ID == 2) +#define RTE_UART7_RTS 1 +#define RTE_UART7_RTS_PORT GPIOE +#define RTE_UART7_RTS_BIT 9 +#else +#error "Invalid UART7_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_RX_DMA 0 +#define RTE_UART7_RX_DMA_NUMBER 1 +#define RTE_UART7_RX_DMA_STREAM 3 +#define RTE_UART7_RX_DMA_CHANNEL 5 +#define RTE_UART7_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 +// Selects DMA Stream (only Stream 1 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART7_TX_DMA 0 +#define RTE_UART7_TX_DMA_NUMBER 1 +#define RTE_UART7_TX_DMA_STREAM 1 +#define RTE_UART7_TX_DMA_CHANNEL 5 +#define RTE_UART7_TX_DMA_PRIORITY 0 + +// + +// UART8 (Universal asynchronous receiver transmitter) [Driver_USART8] +// Configuration settings for Driver_USART8 in component ::CMSIS Driver:USART +#define RTE_UART8 0 + +// UART8_TX Pin <0=>Not Used <1=>PE1 +#define RTE_UART8_TX_ID 0 +#if (RTE_UART8_TX_ID == 0) +#define RTE_UART8_TX 0 +#elif (RTE_UART8_TX_ID == 1) +#define RTE_UART8_TX 1 +#define RTE_UART8_TX_PORT GPIOE +#define RTE_UART8_TX_BIT 1 +#else +#error "Invalid UART8_TX Pin Configuration!" +#endif + +// UART8_RX Pin <0=>Not Used <1=>PE0 +#define RTE_UART8_RX_ID 0 +#if (RTE_UART8_RX_ID == 0) +#define RTE_UART8_RX 0 +#elif (RTE_UART8_RX_ID == 1) +#define RTE_UART8_RX 1 +#define RTE_UART8_RX_PORT GPIOE +#define RTE_UART8_RX_BIT 0 +#else +#error "Invalid UART8_RX Pin Configuration!" +#endif + +// UART8_CTS Pin <0=>Not Used <1=>PD14 +#define RTE_UART8_CTS_ID 0 +#if (RTE_UART8_CTS_ID == 0) +#define RTE_UART8_CTS 0 +#elif (RTE_UART8_CTS_ID == 1) +#define RTE_UART8_CTS 1 +#define RTE_UART8_CTS_PORT GPIOD +#define RTE_UART8_CTS_BIT 14 +#else +#error "Invalid UART8_CTS Pin Configuration!" +#endif + +// UART8_RTS Pin <0=>Not Used <1=>PD15 +#define RTE_UART8_RTS_ID 0 +#if (RTE_UART8_RTS_ID == 0) +#define RTE_UART8_RTS 0 +#elif (RTE_UART8_RTS_ID == 1) +#define RTE_UART8_RTS 1 +#define RTE_UART8_RTS_PORT GPIOD +#define RTE_UART8_RTS_BIT 15 +#else +#error "Invalid UART8_RTS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_RX_DMA 0 +#define RTE_UART8_RX_DMA_NUMBER 1 +#define RTE_UART8_RX_DMA_STREAM 6 +#define RTE_UART8_RX_DMA_CHANNEL 5 +#define RTE_UART8_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 +// Selects DMA Stream (only Stream 0 can be used) +// Channel <5=>5 +// Selects DMA Channel (only Channel 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_UART8_TX_DMA 0 +#define RTE_UART8_TX_DMA_NUMBER 1 +#define RTE_UART8_TX_DMA_STREAM 0 +#define RTE_UART8_TX_DMA_CHANNEL 5 +#define RTE_UART8_TX_DMA_PRIORITY 0 + +// + + +// I2C1 (Inter-integrated Circuit Interface 1) [Driver_I2C1] +// Configuration settings for Driver_I2C1 in component ::CMSIS Driver:I2C +#define RTE_I2C1 0 + +// I2C1_SCL Pin <0=>PB6 <1=>PB8 +#define RTE_I2C1_SCL_PORT_ID 0 +#if (RTE_I2C1_SCL_PORT_ID == 0) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 6 +#elif (RTE_I2C1_SCL_PORT_ID == 1) +#define RTE_I2C1_SCL_PORT GPIOB +#define RTE_I2C1_SCL_BIT 8 +#else +#error "Invalid I2C1_SCL Pin Configuration!" +#endif + +// I2C1_SDA Pin <0=>PB7 <1=>PB9 +#define RTE_I2C1_SDA_PORT_ID 0 +#if (RTE_I2C1_SDA_PORT_ID == 0) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 7 +#elif (RTE_I2C1_SDA_PORT_ID == 1) +#define RTE_I2C1_SDA_PORT GPIOB +#define RTE_I2C1_SDA_BIT 9 +#else +#error "Invalid I2C1_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_RX_DMA 0 +#define RTE_I2C1_RX_DMA_NUMBER 1 +#define RTE_I2C1_RX_DMA_STREAM 0 +#define RTE_I2C1_RX_DMA_CHANNEL 1 +#define RTE_I2C1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C1_TX_DMA 0 +#define RTE_I2C1_TX_DMA_NUMBER 1 +#define RTE_I2C1_TX_DMA_STREAM 6 +#define RTE_I2C1_TX_DMA_CHANNEL 1 +#define RTE_I2C1_TX_DMA_PRIORITY 0 + +// + + +// I2C2 (Inter-integrated Circuit Interface 2) [Driver_I2C2] +// Configuration settings for Driver_I2C2 in component ::CMSIS Driver:I2C +#define RTE_I2C2 0 + +// I2C2_SCL Pin <0=>PF1 <1=>PH4 <2=>PB10 +#define RTE_I2C2_SCL_PORT_ID 0 +#if (RTE_I2C2_SCL_PORT_ID == 0) +#define RTE_I2C2_SCL_PORT GPIOF +#define RTE_I2C2_SCL_BIT 1 +#elif (RTE_I2C2_SCL_PORT_ID == 1) +#define RTE_I2C2_SCL_PORT GPIOH +#define RTE_I2C2_SCL_BIT 4 +#elif (RTE_I2C2_SCL_PORT_ID == 2) +#define RTE_I2C2_SCL_PORT GPIOB +#define RTE_I2C2_SCL_BIT 10 +#else +#error "Invalid I2C2_SCL Pin Configuration!" +#endif + +// I2C2_SDA Pin <0=>PF0 <1=>PH5 <2=>PB11 +#define RTE_I2C2_SDA_PORT_ID 0 +#if (RTE_I2C2_SDA_PORT_ID == 0) +#define RTE_I2C2_SDA_PORT GPIOF +#define RTE_I2C2_SDA_BIT 0 +#elif (RTE_I2C2_SDA_PORT_ID == 1) +#define RTE_I2C2_SDA_PORT GPIOH +#define RTE_I2C2_SDA_BIT 5 +#elif (RTE_I2C2_SDA_PORT_ID == 2) +#define RTE_I2C2_SDA_PORT GPIOB +#define RTE_I2C2_SDA_BIT 11 +#else +#error "Invalid I2C2_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 <3=>3 +// Selects DMA Stream (only Stream 2 or 3 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_RX_DMA 0 +#define RTE_I2C2_RX_DMA_NUMBER 1 +#define RTE_I2C2_RX_DMA_STREAM 2 +#define RTE_I2C2_RX_DMA_CHANNEL 7 +#define RTE_I2C2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <7=>7 +// Selects DMA Stream (only Stream 7 can be used) +// Channel <7=>7 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C2_TX_DMA 0 +#define RTE_I2C2_TX_DMA_NUMBER 1 +#define RTE_I2C2_TX_DMA_STREAM 7 +#define RTE_I2C2_TX_DMA_CHANNEL 7 +#define RTE_I2C2_TX_DMA_PRIORITY 0 + +// + + +// I2C3 (Inter-integrated Circuit Interface 3) [Driver_I2C3] +// Configuration settings for Driver_I2C3 in component ::CMSIS Driver:I2C +#define RTE_I2C3 0 + +// I2C3_SCL Pin <0=>PH7 <1=>PA8 +#define RTE_I2C3_SCL_PORT_ID 0 +#if (RTE_I2C3_SCL_PORT_ID == 0) +#define RTE_I2C3_SCL_PORT GPIOH +#define RTE_I2C3_SCL_BIT 7 +#elif (RTE_I2C3_SCL_PORT_ID == 1) +#define RTE_I2C3_SCL_PORT GPIOA +#define RTE_I2C3_SCL_BIT 8 +#else +#error "Invalid I2C3_SCL Pin Configuration!" +#endif + +// I2C3_SDA Pin <0=>PH8 <1=>PC9 +#define RTE_I2C3_SDA_PORT_ID 0 +#if (RTE_I2C3_SDA_PORT_ID == 0) +#define RTE_I2C3_SDA_PORT GPIOH +#define RTE_I2C3_SDA_BIT 8 +#elif (RTE_I2C3_SDA_PORT_ID == 1) +#define RTE_I2C3_SDA_PORT GPIOC +#define RTE_I2C3_SDA_BIT 9 +#else +#error "Invalid I2C3_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <1=>1 <2=>2 +// Selects DMA Stream (only Stream 1 or 2 can be used) +// Channel <1=>1 <3=>3 +// Selects DMA Channel (only Channel 1 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_RX_DMA 0 +#define RTE_I2C3_RX_DMA_NUMBER 1 +#define RTE_I2C3_RX_DMA_STREAM 2 +#define RTE_I2C3_RX_DMA_CHANNEL 3 +#define RTE_I2C3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C3_TX_DMA 0 +#define RTE_I2C3_TX_DMA_NUMBER 1 +#define RTE_I2C3_TX_DMA_STREAM 4 +#define RTE_I2C3_TX_DMA_CHANNEL 3 +#define RTE_I2C3_TX_DMA_PRIORITY 0 + +// + + +// I2C4 (Inter-integrated Circuit Interface 4) [Driver_I2C4] +// Configuration settings for Driver_I2C4 in component ::CMSIS Driver:I2C +#define RTE_I2C4 0 + +// I2C4_SCL Pin <0=>PD12 <1=>PF14 <2=>PH11 <3=>PB6 <4=>PB8 +#define RTE_I2C4_SCL_PORT_ID 0 +#if (RTE_I2C4_SCL_PORT_ID == 0) +#define RTE_I2C4_SCL_PORT GPIOD +#define RTE_I2C4_SCL_BIT 12 +#elif (RTE_I2C4_SCL_PORT_ID == 1) +#define RTE_I2C4_SCL_PORT GPIOF +#define RTE_I2C4_SCL_BIT 14 +#elif (RTE_I2C4_SCL_PORT_ID == 2) +#define RTE_I2C4_SCL_PORT GPIOH +#define RTE_I2C4_SCL_BIT 11 +#elif (RTE_I2C4_SCL_PORT_ID == 3) +#define RTE_I2C4_SCL_PORT GPIOB +#define RTE_I2C4_SCL_BIT 6 +#elif (RTE_I2C4_SCL_PORT_ID == 4) +#define RTE_I2C4_SCL_PORT GPIOB +#define RTE_I2C4_SCL_BIT 8 +#else +#error "Invalid I2C4_SCL Pin Configuration!" +#endif + +// I2C4_SDA Pin <0=>PD13 <1=>PF15 <2=>PH12 <3=>PB7 <4=>PB9 +#define RTE_I2C4_SDA_PORT_ID 0 +#if (RTE_I2C4_SDA_PORT_ID == 0) +#define RTE_I2C4_SDA_PORT GPIOD +#define RTE_I2C4_SDA_BIT 13 +#elif (RTE_I2C4_SDA_PORT_ID == 1) +#define RTE_I2C4_SDA_PORT GPIOF +#define RTE_I2C4_SDA_BIT 15 +#elif (RTE_I2C4_SDA_PORT_ID == 2) +#define RTE_I2C4_SDA_PORT GPIOH +#define RTE_I2C4_SDA_BIT 12 +#elif (RTE_I2C4_SDA_PORT_ID == 3) +#define RTE_I2C4_SDA_PORT GPIOB +#define RTE_I2C4_SDA_BIT 7 +#elif (RTE_I2C4_SDA_PORT_ID == 4) +#define RTE_I2C4_SDA_PORT GPIOB +#define RTE_I2C4_SDA_BIT 9 +#else +#error "Invalid I2C4_SDA Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <2=>2 +// Selects DMA Stream (only Stream 2 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C4_RX_DMA 0 +#define RTE_I2C4_RX_DMA_NUMBER 1 +#define RTE_I2C4_RX_DMA_STREAM 2 +#define RTE_I2C4_RX_DMA_CHANNEL 3 +#define RTE_I2C4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <2=>2 +// Selects DMA Channel (only Channel 2 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_I2C4_TX_DMA 0 +#define RTE_I2C4_TX_DMA_NUMBER 1 +#define RTE_I2C4_TX_DMA_STREAM 4 +#define RTE_I2C4_TX_DMA_CHANNEL 3 +#define RTE_I2C4_TX_DMA_PRIORITY 0 + +// + + +// SPI1 (Serial Peripheral Interface 1) [Driver_SPI1] +// Configuration settings for Driver_SPI1 in component ::CMSIS Driver:SPI +#define RTE_SPI1 0 + +// SPI1_MISO Pin <0=>Not Used <1=>PA6 <2=>PB4 <3=>PG9 +#define RTE_SPI1_MISO_PORT_ID 0 +#if (RTE_SPI1_MISO_PORT_ID == 0) +#define RTE_SPI1_MISO 0 +#elif (RTE_SPI1_MISO_PORT_ID == 1) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOA +#define RTE_SPI1_MISO_BIT 6 +#elif (RTE_SPI1_MISO_PORT_ID == 2) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOB +#define RTE_SPI1_MISO_BIT 4 +#elif (RTE_SPI1_MISO_PORT_ID == 3) +#define RTE_SPI1_MISO 1 +#define RTE_SPI1_MISO_PORT GPIOG +#define RTE_SPI1_MISO_BIT 9 +#else +#error "Invalid SPI1_MISO Pin Configuration!" +#endif + +// SPI1_MOSI Pin <0=>Not Used <1=>PA7 <2=>PB5 <3=>PD7 +#define RTE_SPI1_MOSI_PORT_ID 0 +#if (RTE_SPI1_MOSI_PORT_ID == 0) +#define RTE_SPI1_MOSI 0 +#elif (RTE_SPI1_MOSI_PORT_ID == 1) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOA +#define RTE_SPI1_MOSI_BIT 7 +#elif (RTE_SPI1_MOSI_PORT_ID == 2) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOB +#define RTE_SPI1_MOSI_BIT 5 +#elif (RTE_SPI1_MOSI_PORT_ID == 3) +#define RTE_SPI1_MOSI 1 +#define RTE_SPI1_MOSI_PORT GPIOD +#define RTE_SPI1_MOSI_BIT 7 +#else +#error "Invalid SPI1_MOSI Pin Configuration!" +#endif + +// SPI1_SCK Pin <0=>PA5 <1=>PB3 <2=>PG11 +#define RTE_SPI1_SCL_PORT_ID 0 +#if (RTE_SPI1_SCL_PORT_ID == 0) +#define RTE_SPI1_SCL_PORT GPIOA +#define RTE_SPI1_SCL_BIT 5 +#elif (RTE_SPI1_SCL_PORT_ID == 1) +#define RTE_SPI1_SCL_PORT GPIOB +#define RTE_SPI1_SCL_BIT 3 +#elif (RTE_SPI1_SCL_PORT_ID == 2) +#define RTE_SPI1_SCL_PORT GPIOG +#define RTE_SPI1_SCL_BIT 11 +#else +#error "Invalid SPI1_SCK Pin Configuration!" +#endif + +// SPI1_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 <3=>PG10 +#define RTE_SPI1_NSS_PORT_ID 0 +#if (RTE_SPI1_NSS_PORT_ID == 0) +#define RTE_SPI1_NSS_PIN 0 +#elif (RTE_SPI1_NSS_PORT_ID == 1) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 4 +#elif (RTE_SPI1_NSS_PORT_ID == 2) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOA +#define RTE_SPI1_NSS_BIT 15 +#elif (RTE_SPI1_NSS_PORT_ID == 3) +#define RTE_SPI1_NSS_PIN 1 +#define RTE_SPI1_NSS_PORT GPIOG +#define RTE_SPI1_NSS_BIT 10 +#else +#error "Invalid SPI1_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_RX_DMA 0 +#define RTE_SPI1_RX_DMA_NUMBER 2 +#define RTE_SPI1_RX_DMA_STREAM 0 +#define RTE_SPI1_RX_DMA_CHANNEL 3 +#define RTE_SPI1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI1_TX_DMA 0 +#define RTE_SPI1_TX_DMA_NUMBER 2 +#define RTE_SPI1_TX_DMA_STREAM 5 +#define RTE_SPI1_TX_DMA_CHANNEL 3 +#define RTE_SPI1_TX_DMA_PRIORITY 0 + +// + + +// SPI2 (Serial Peripheral Interface 2) [Driver_SPI2] +// Configuration settings for Driver_SPI2 in component ::CMSIS Driver:SPI +#define RTE_SPI2 0 + +// SPI2_MISO Pin <0=>Not Used <1=>PB14 <2=>PC2 <3=>PI2 +#define RTE_SPI2_MISO_PORT_ID 0 +#if (RTE_SPI2_MISO_PORT_ID == 0) +#define RTE_SPI2_MISO 0 +#elif (RTE_SPI2_MISO_PORT_ID == 1) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOB +#define RTE_SPI2_MISO_BIT 14 +#elif (RTE_SPI2_MISO_PORT_ID == 2) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOC +#define RTE_SPI2_MISO_BIT 2 +#elif (RTE_SPI2_MISO_PORT_ID == 3) +#define RTE_SPI2_MISO 1 +#define RTE_SPI2_MISO_PORT GPIOI +#define RTE_SPI2_MISO_BIT 2 +#else +#error "Invalid SPI2_MISO Pin Configuration!" +#endif + +// SPI2_MOSI Pin <0=>Not Used <1=>PB15 <2=>PC1 <3=>PC3 <4=>PI3 +#define RTE_SPI2_MOSI_PORT_ID 0 +#if (RTE_SPI2_MOSI_PORT_ID == 0) +#define RTE_SPI2_MOSI 0 +#elif (RTE_SPI2_MOSI_PORT_ID == 1) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOB +#define RTE_SPI2_MOSI_BIT 15 +#elif (RTE_SPI2_MOSI_PORT_ID == 2) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 1 +#elif (RTE_SPI2_MOSI_PORT_ID == 3) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOC +#define RTE_SPI2_MOSI_BIT 3 +#elif (RTE_SPI2_MOSI_PORT_ID == 4) +#define RTE_SPI2_MOSI 1 +#define RTE_SPI2_MOSI_PORT GPIOI +#define RTE_SPI2_MOSI_BIT 3 +#else +#error "Invalid SPI2_MOSI Pin Configuration!" +#endif + +// SPI2_SCK Pin <0=>PA9 <1=>PB10 <2=>PB13 <3=>PD3 <4=>PI1 <5=>PA12 +#define RTE_SPI2_SCL_PORT_ID 0 +#if (RTE_SPI2_SCL_PORT_ID == 0) +#define RTE_SPI2_SCL_PORT GPIOA +#define RTE_SPI2_SCL_BIT 9 +#elif (RTE_SPI2_SCL_PORT_ID == 1) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 10 +#elif (RTE_SPI2_SCL_PORT_ID == 2) +#define RTE_SPI2_SCL_PORT GPIOB +#define RTE_SPI2_SCL_BIT 13 +#elif (RTE_SPI2_SCL_PORT_ID == 3) +#define RTE_SPI2_SCL_PORT GPIOD +#define RTE_SPI2_SCL_BIT 3 +#elif (RTE_SPI2_SCL_PORT_ID == 4) +#define RTE_SPI2_SCL_PORT GPIOI +#define RTE_SPI2_SCL_BIT 1 +#elif (RTE_SPI2_SCL_PORT_ID == 5) +#define RTE_SPI2_SCL_PORT GPIOA +#define RTE_SPI2_SCL_BIT 12 +#else +#error "Invalid SPI2_SCK Pin Configuration!" +#endif + +// SPI2_NSS Pin <0=>Not Used <1=>PB4 <2=>PB9 <3=>PB12 <4=>PI0 <5=>PA11 +#define RTE_SPI2_NSS_PORT_ID 0 +#if (RTE_SPI2_NSS_PORT_ID == 0) +#define RTE_SPI2_NSS_PIN 0 +#elif (RTE_SPI2_NSS_PORT_ID == 1) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 4 +#elif (RTE_SPI2_NSS_PORT_ID == 2) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 9 +#elif (RTE_SPI2_NSS_PORT_ID == 3) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOB +#define RTE_SPI2_NSS_BIT 12 +#elif (RTE_SPI2_NSS_PORT_ID == 4) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOI +#define RTE_SPI2_NSS_BIT 0 +#elif (RTE_SPI2_NSS_PORT_ID == 5) +#define RTE_SPI2_NSS_PIN 1 +#define RTE_SPI2_NSS_PORT GPIOA +#define RTE_SPI2_NSS_BIT 11 +#else +#error "Invalid SPI2_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <3=>3 +// Selects DMA Stream (only Stream 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_RX_DMA 0 +#define RTE_SPI2_RX_DMA_NUMBER 1 +#define RTE_SPI2_RX_DMA_STREAM 3 +#define RTE_SPI2_RX_DMA_CHANNEL 0 +#define RTE_SPI2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI2_TX_DMA 0 +#define RTE_SPI2_TX_DMA_NUMBER 1 +#define RTE_SPI2_TX_DMA_STREAM 4 +#define RTE_SPI2_TX_DMA_CHANNEL 0 +#define RTE_SPI2_TX_DMA_PRIORITY 0 + +// + + +// SPI3 (Serial Peripheral Interface 3) [Driver_SPI3] +// Configuration settings for Driver_SPI3 in component ::CMSIS Driver:SPI +#define RTE_SPI3 0 + +// SPI3_MISO Pin <0=>Not Used <1=>PB4 <2=>PC11 +#define RTE_SPI3_MISO_PORT_ID 0 +#if (RTE_SPI3_MISO_PORT_ID == 0) +#define RTE_SPI3_MISO 0 +#elif (RTE_SPI3_MISO_PORT_ID == 1) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOB +#define RTE_SPI3_MISO_BIT 4 +#elif (RTE_SPI3_MISO_PORT_ID == 2) +#define RTE_SPI3_MISO 1 +#define RTE_SPI3_MISO_PORT GPIOC +#define RTE_SPI3_MISO_BIT 11 +#else +#error "Invalid SPI3_MISO Pin Configuration!" +#endif + +// SPI3_MOSI Pin <0=>Not Used <1=>PB2 <2=>PB5 <3=>PC12 <4=>PD6 +#define RTE_SPI3_MOSI_PORT_ID 0 +#if (RTE_SPI3_MOSI_PORT_ID == 0) +#define RTE_SPI3_MOSI 0 +#elif (RTE_SPI3_MOSI_PORT_ID == 1) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 2 +#elif (RTE_SPI3_MOSI_PORT_ID == 2) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOB +#define RTE_SPI3_MOSI_BIT 5 +#elif (RTE_SPI3_MOSI_PORT_ID == 3) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOC +#define RTE_SPI3_MOSI_BIT 12 +#elif (RTE_SPI3_MOSI_PORT_ID == 4) +#define RTE_SPI3_MOSI 1 +#define RTE_SPI3_MOSI_PORT GPIOD +#define RTE_SPI3_MOSI_BIT 6 +#else +#error "Invalid SPI3_MOSI Pin Configuration!" +#endif + +// SPI3_SCK Pin <0=>PB3 <1=>PC10 +#define RTE_SPI3_SCL_PORT_ID 0 +#if (RTE_SPI3_SCL_PORT_ID == 0) +#define RTE_SPI3_SCL_PORT GPIOB +#define RTE_SPI3_SCL_BIT 3 +#elif (RTE_SPI3_SCL_PORT_ID == 1) +#define RTE_SPI3_SCL_PORT GPIOC +#define RTE_SPI3_SCL_BIT 10 +#else +#error "Invalid SPI3_SCK Pin Configuration!" +#endif + +// SPI3_NSS Pin <0=>Not Used <1=>PA4 <2=>PA15 +#define RTE_SPI3_NSS_PORT_ID 0 +#if (RTE_SPI3_NSS_PORT_ID == 0) +#define RTE_SPI3_NSS_PIN 0 +#elif (RTE_SPI3_NSS_PORT_ID == 1) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 4 +#elif (RTE_SPI3_NSS_PORT_ID == 2) +#define RTE_SPI3_NSS_PIN 1 +#define RTE_SPI3_NSS_PORT GPIOA +#define RTE_SPI3_NSS_BIT 15 +#else +#error "Invalid SPI3_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <0=>0 <2=>2 +// Selects DMA Stream (only Stream 0 or 2 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_RX_DMA 0 +#define RTE_SPI3_RX_DMA_NUMBER 1 +#define RTE_SPI3_RX_DMA_STREAM 0 +#define RTE_SPI3_RX_DMA_CHANNEL 0 +#define RTE_SPI3_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <1=>1 +// Selects DMA Number (only DMA1 can be used) +// Stream <5=>5 <7=>7 +// Selects DMA Stream (only Stream 5 or 7 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI3_TX_DMA 0 +#define RTE_SPI3_TX_DMA_NUMBER 1 +#define RTE_SPI3_TX_DMA_STREAM 5 +#define RTE_SPI3_TX_DMA_CHANNEL 0 +#define RTE_SPI3_TX_DMA_PRIORITY 0 + +// + + +// SPI4 (Serial Peripheral Interface 4) [Driver_SPI4] +// Configuration settings for Driver_SPI4 in component ::CMSIS Driver:SPI +#define RTE_SPI4 0 + +// SPI4_MISO Pin <0=>Not Used <1=>PE5 <2=>PE13 +#define RTE_SPI4_MISO_PORT_ID 0 +#if (RTE_SPI4_MISO_PORT_ID == 0) +#define RTE_SPI4_MISO 0 +#elif (RTE_SPI4_MISO_PORT_ID == 1) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 5 +#elif (RTE_SPI4_MISO_PORT_ID == 2) +#define RTE_SPI4_MISO 1 +#define RTE_SPI4_MISO_PORT GPIOE +#define RTE_SPI4_MISO_BIT 13 +#else +#error "Invalid SPI4_MISO Pin Configuration!" +#endif + +// SPI4_MOSI Pin <0=>Not Used <1=>PE6 <2=>PE14 +#define RTE_SPI4_MOSI_PORT_ID 0 +#if (RTE_SPI4_MOSI_PORT_ID == 0) +#define RTE_SPI4_MOSI 0 +#elif (RTE_SPI4_MOSI_PORT_ID == 1) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 6 +#elif (RTE_SPI4_MOSI_PORT_ID == 2) +#define RTE_SPI4_MOSI 1 +#define RTE_SPI4_MOSI_PORT GPIOE +#define RTE_SPI4_MOSI_BIT 14 +#else +#error "Invalid SPI4_MOSI Pin Configuration!" +#endif + +// SPI4_SCK Pin <0=>PE2 <1=>PE12 +#define RTE_SPI4_SCL_PORT_ID 0 +#if (RTE_SPI4_SCL_PORT_ID == 0) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 2 +#elif (RTE_SPI4_SCL_PORT_ID == 1) +#define RTE_SPI4_SCL_PORT GPIOE +#define RTE_SPI4_SCL_BIT 12 +#else +#error "Invalid SPI4_SCK Pin Configuration!" +#endif + +// SPI4_NSS Pin <0=>Not Used <1=>PE4 <2=>PE11 +#define RTE_SPI4_NSS_PORT_ID 0 +#if (RTE_SPI4_NSS_PORT_ID == 0) +#define RTE_SPI4_NSS_PIN 0 +#elif (RTE_SPI4_NSS_PORT_ID == 1) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 4 +#elif (RTE_SPI4_NSS_PORT_ID == 2) +#define RTE_SPI4_NSS_PIN 1 +#define RTE_SPI4_NSS_PORT GPIOE +#define RTE_SPI4_NSS_BIT 11 +#else +#error "Invalid SPI4_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <3=>3 +// Selects DMA Stream (only Stream 0 or 3 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_RX_DMA 0 +#define RTE_SPI4_RX_DMA_NUMBER 2 +#define RTE_SPI4_RX_DMA_STREAM 0 +#define RTE_SPI4_RX_DMA_CHANNEL 4 +#define RTE_SPI4_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <4=>4 +// Selects DMA Stream (only Stream 1 or 4 can be used) +// Channel <4=>4 <5=>5 +// Selects DMA Channel (only Channel 4 or 5 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI4_TX_DMA 0 +#define RTE_SPI4_TX_DMA_NUMBER 2 +#define RTE_SPI4_TX_DMA_STREAM 1 +#define RTE_SPI4_TX_DMA_CHANNEL 4 +#define RTE_SPI4_TX_DMA_PRIORITY 0 + +// + + +// SPI5 (Serial Peripheral Interface 5) [Driver_SPI5] +// Configuration settings for Driver_SPI5 in component ::CMSIS Driver:SPI +#define RTE_SPI5 0 + +// SPI5_MISO Pin <0=>Not Used <1=>PF8 <2=>PH7 +#define RTE_SPI5_MISO_PORT_ID 0 +#if (RTE_SPI5_MISO_PORT_ID == 0) +#define RTE_SPI5_MISO 0 +#elif (RTE_SPI5_MISO_PORT_ID == 1) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOF +#define RTE_SPI5_MISO_BIT 8 +#elif (RTE_SPI5_MISO_PORT_ID == 2) +#define RTE_SPI5_MISO 1 +#define RTE_SPI5_MISO_PORT GPIOH +#define RTE_SPI5_MISO_BIT 7 +#else +#error "Invalid SPI5_MISO Pin Configuration!" +#endif + +// SPI5_MOSI Pin <0=>Not Used <1=>PF9 <2=>PF11 +#define RTE_SPI5_MOSI_PORT_ID 0 +#if (RTE_SPI5_MOSI_PORT_ID == 0) +#define RTE_SPI5_MOSI 0 +#elif (RTE_SPI5_MOSI_PORT_ID == 1) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 9 +#elif (RTE_SPI5_MOSI_PORT_ID == 2) +#define RTE_SPI5_MOSI 1 +#define RTE_SPI5_MOSI_PORT GPIOF +#define RTE_SPI5_MOSI_BIT 11 +#else +#error "Invalid SPI5_MOSI Pin Configuration!" +#endif + +// SPI5_SCK Pin <0=>PF7 <1=>PH6 +#define RTE_SPI5_SCL_PORT_ID 0 +#if (RTE_SPI5_SCL_PORT_ID == 0) +#define RTE_SPI5_SCL_PORT GPIOF +#define RTE_SPI5_SCL_BIT 7 +#elif (RTE_SPI5_SCL_PORT_ID == 1) +#define RTE_SPI5_SCL_PORT GPIOH +#define RTE_SPI5_SCL_BIT 6 +#else +#error "Invalid SPI5_SCK Pin Configuration!" +#endif + +// SPI5_NSS Pin <0=>Not Used <1=>PF6 <2=>PH5 +#define RTE_SPI5_NSS_PORT_ID 0 +#if (RTE_SPI5_NSS_PORT_ID == 0) +#define RTE_SPI5_NSS_PIN 0 +#elif (RTE_SPI5_NSS_PORT_ID == 1) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOF +#define RTE_SPI5_NSS_BIT 6 +#elif (RTE_SPI5_NSS_PORT_ID == 2) +#define RTE_SPI5_NSS_PIN 1 +#define RTE_SPI5_NSS_PORT GPIOH +#define RTE_SPI5_NSS_BIT 5 +#else +#error "Invalid SPI5_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <5=>5 +// Selects DMA Stream (only Stream 3 or 5 can be used) +// Channel <2=>2 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_RX_DMA 0 +#define RTE_SPI5_RX_DMA_NUMBER 2 +#define RTE_SPI5_RX_DMA_STREAM 3 +#define RTE_SPI5_RX_DMA_CHANNEL 2 +#define RTE_SPI5_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <4=>4 <6=>6 +// Selects DMA Stream (only Stream 4 or 6 can be used) +// Channel <2=>2 <7=>7 +// Selects DMA Channel (only Channel 2 or 7 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI5_TX_DMA 0 +#define RTE_SPI5_TX_DMA_NUMBER 2 +#define RTE_SPI5_TX_DMA_STREAM 4 +#define RTE_SPI5_TX_DMA_CHANNEL 2 +#define RTE_SPI5_TX_DMA_PRIORITY 0 + +// + + +// SPI6 (Serial Peripheral Interface 6) [Driver_SPI6] +// Configuration settings for Driver_SPI6 in component ::CMSIS Driver:SPI +#define RTE_SPI6 0 + +// SPI6_MISO Pin <0=>Not Used <1=>PG12 <2=>PA6 <3=>PB4 +#define RTE_SPI6_MISO_PORT_ID 0 +#if (RTE_SPI6_MISO_PORT_ID == 0) +#define RTE_SPI6_MISO 0 +#elif (RTE_SPI6_MISO_PORT_ID == 1) +#define RTE_SPI6_MISO 1 +#define RTE_SPI6_MISO_PORT GPIOG +#define RTE_SPI6_MISO_BIT 12 +#elif (RTE_SPI6_MISO_PORT_ID == 2) +#define RTE_SPI6_MISO 1 +#define RTE_SPI6_MISO_PORT GPIOA +#define RTE_SPI6_MISO_BIT 6 +#elif (RTE_SPI6_MISO_PORT_ID == 3) +#define RTE_SPI6_MISO 1 +#define RTE_SPI6_MISO_PORT GPIOB +#define RTE_SPI6_MISO_BIT 4 +#else +#error "Invalid SPI6_MISO Pin Configuration!" +#endif + +// SPI6_MOSI Pin <0=>Not Used <1=>PG14 <2=>PA7 <3=>PB5 +#define RTE_SPI6_MOSI_PORT_ID 0 +#if (RTE_SPI6_MOSI_PORT_ID == 0) +#define RTE_SPI6_MOSI 0 +#elif (RTE_SPI6_MOSI_PORT_ID == 1) +#define RTE_SPI6_MOSI 1 +#define RTE_SPI6_MOSI_PORT GPIOG +#define RTE_SPI6_MOSI_BIT 14 +#elif (RTE_SPI6_MOSI_PORT_ID == 2) +#define RTE_SPI6_MOSI 1 +#define RTE_SPI6_MOSI_PORT GPIOA +#define RTE_SPI6_MOSI_BIT 7 +#elif (RTE_SPI6_MOSI_PORT_ID == 3) +#define RTE_SPI6_MOSI 1 +#define RTE_SPI6_MOSI_PORT GPIOB +#define RTE_SPI6_MOSI_BIT 5 +#else +#error "Invalid SPI6_MOSI Pin Configuration!" +#endif + +// SPI6_SCK Pin <0=>PG13 <1=>PA5 <2=>PB3 +#define RTE_SPI6_SCL_PORT_ID 0 +#if (RTE_SPI6_SCL_PORT_ID == 0) +#define RTE_SPI6_SCL_PORT GPIOG +#define RTE_SPI6_SCL_BIT 13 +#elif (RTE_SPI6_SCL_PORT_ID == 1) +#define RTE_SPI6_SCL_PORT GPIOA +#define RTE_SPI6_SCL_BIT 5 +#elif (RTE_SPI6_SCL_PORT_ID == 2) +#define RTE_SPI6_SCL_PORT GPIOB +#define RTE_SPI6_SCL_BIT 3 +#else +#error "Invalid SPI6_SCK Pin Configuration!" +#endif + +// SPI6_NSS Pin <0=>Not Used <1=>PG8 <2=>PA4 <3=>PA15 +#define RTE_SPI6_NSS_PORT_ID 0 +#if (RTE_SPI6_NSS_PORT_ID == 0) +#define RTE_SPI6_NSS_PIN 0 +#elif (RTE_SPI6_NSS_PORT_ID == 1) +#define RTE_SPI6_NSS_PIN 1 +#define RTE_SPI6_NSS_PORT GPIOG +#define RTE_SPI6_NSS_BIT 8 +#elif (RTE_SPI6_NSS_PORT_ID == 2) +#define RTE_SPI6_NSS_PIN 1 +#define RTE_SPI6_NSS_PORT GPIOA +#define RTE_SPI6_NSS_BIT 4 +#elif (RTE_SPI6_NSS_PORT_ID == 3) +#define RTE_SPI6_NSS_PIN 1 +#define RTE_SPI6_NSS_PORT GPIOA +#define RTE_SPI6_NSS_BIT 15 +#else +#error "Invalid SPI6_NSS Pin Configuration!" +#endif + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 +// Selects DMA Stream (only Stream 6 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_RX_DMA 0 +#define RTE_SPI6_RX_DMA_NUMBER 2 +#define RTE_SPI6_RX_DMA_STREAM 6 +#define RTE_SPI6_RX_DMA_CHANNEL 1 +#define RTE_SPI6_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <5=>5 +// Selects DMA Stream (only Stream 5 can be used) +// Channel <1=>1 +// Selects DMA Channel (only Channel 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SPI6_TX_DMA 0 +#define RTE_SPI6_TX_DMA_NUMBER 2 +#define RTE_SPI6_TX_DMA_STREAM 5 +#define RTE_SPI6_TX_DMA_CHANNEL 1 +#define RTE_SPI6_TX_DMA_PRIORITY 0 + +// + + +// SAI1 (Serial Audio Interface 1) [Driver_SAI1] +// Configuration settings for Driver_SAI1 in component ::CMSIS Driver:SAI +#define RTE_SAI1 0 + +// SAI1_SD_A Pin <0=>Not Used <1=>PB2 <2=>PC1 <3=>PD6 <4=>PE6 +#define RTE_SAI1_SD_A_PORT_ID 0 +#if (RTE_SAI1_SD_A_PORT_ID == 0) +#define RTE_SAI1_SD_A_PIN 0 +#elif (RTE_SAI1_SD_A_PORT_ID == 1) +#define RTE_SAI1_SD_A_PIN 1 +#define RTE_SAI1_SD_A_PORT GPIOB +#define RTE_SAI1_SD_A_BIT 2 +#elif (RTE_SAI1_SD_A_PORT_ID == 2) +#define RTE_SAI1_SD_A_PIN 1 +#define RTE_SAI1_SD_A_PORT GPIOC +#define RTE_SAI1_SD_A_BIT 1 +#elif (RTE_SAI1_SD_A_PORT_ID == 3) +#define RTE_SAI1_SD_A_PIN 1 +#define RTE_SAI1_SD_A_PORT GPIOD +#define RTE_SAI1_SD_A_BIT 6 +#elif (RTE_SAI1_SD_A_PORT_ID == 4) +#define RTE_SAI1_SD_A_PIN 1 +#define RTE_SAI1_SD_A_PORT GPIOE +#define RTE_SAI1_SD_A_BIT 6 +#else +#error "Invalid SAI1_SD_A Pin Configuration!" +#endif + +// SAI1_FS_A Pin <0=>Not Used <1=>PE4 +#define RTE_SAI1_FS_A_PORT_ID 0 +#if (RTE_SAI1_FS_A_PORT_ID == 0) +#define RTE_SAI1_FS_A_PIN 0 +#elif (RTE_SAI1_FS_A_PORT_ID == 1) +#define RTE_SAI1_FS_A_PIN 1 +#define RTE_SAI1_FS_A_PORT GPIOE +#define RTE_SAI1_FS_A_BIT 4 +#else +#error "Invalid SAI1_FS_A Pin Configuration!" +#endif + +// SAI1_SCK_A Pin <0=>Not Used <1=>PE5 +#define RTE_SAI1_SCK_A_PORT_ID 0 +#if (RTE_SAI1_SCK_A_PORT_ID == 0) +#define RTE_SAI1_SCK_A_PIN 0 +#elif (RTE_SAI1_SCK_A_PORT_ID == 1) +#define RTE_SAI1_SCK_A_PIN 1 +#define RTE_SAI1_SCK_A_PORT GPIOE +#define RTE_SAI1_SCK_A_BIT 5 +#else +#error "Invalid SAI1_SCK_A Pin Configuration!" +#endif + +// SAI1_MCLK_A Pin <0=>Not Used <1=>PE2 <2=>PG7 +#define RTE_SAI1_MCLK_A_PORT_ID 0 +#if (RTE_SAI1_MCLK_A_PORT_ID == 0) +#define RTE_SAI1_MCLK_A_PIN 0 +#elif (RTE_SAI1_MCLK_A_PORT_ID == 1) +#define RTE_SAI1_MCLK_A_PIN 1 +#define RTE_SAI1_MCLK_A_PORT GPIOE +#define RTE_SAI1_MCLK_A_BIT 2 +#elif (RTE_SAI1_MCLK_A_PORT_ID == 2) +#define RTE_SAI1_MCLK_A_PIN 1 +#define RTE_SAI1_MCLK_A_PORT GPIOG +#define RTE_SAI1_MCLK_A_BIT 7 +#else +#error "Invalid SAI1_MCLK_A Pin Configuration!" +#endif + +// SAI1_SD_B Pin <0=>Not Used <1=>PE3 <2=>PF6 +#define RTE_SAI1_SD_B_PORT_ID 0 +#if (RTE_SAI1_SD_B_PORT_ID == 0) +#define RTE_SAI1_SD_B_PIN 0 +#elif (RTE_SAI1_SD_B_PORT_ID == 1) +#define RTE_SAI1_SD_B_PIN 1 +#define RTE_SAI1_SD_B_PORT GPIOE +#define RTE_SAI1_SD_B_BIT 3 +#elif (RTE_SAI1_SD_B_PORT_ID == 2) +#define RTE_SAI1_SD_B_PIN 1 +#define RTE_SAI1_SD_B_PORT GPIOF +#define RTE_SAI1_SD_B_BIT 6 +#else +#error "Invalid SAI1_SD_B Pin Configuration!" +#endif + +// SAI1_FS_B Pin <0=>Not Used <1=>PF9 +#define RTE_SAI1_FS_B_PORT_ID 0 +#if (RTE_SAI1_FS_B_PORT_ID == 0) +#define RTE_SAI1_FS_B_PIN 0 +#elif (RTE_SAI1_FS_B_PORT_ID == 1) +#define RTE_SAI1_FS_B_PIN 1 +#define RTE_SAI1_FS_B_PORT GPIOF +#define RTE_SAI1_FS_B_BIT 9 +#else +#error "Invalid SAI1_FS_B Pin Configuration!" +#endif + +// SAI1_SCK_B Pin <0=>Not Used <1=>PF8 +#define RTE_SAI1_SCK_B_PORT_ID 0 +#if (RTE_SAI1_SCK_B_PORT_ID == 0) +#define RTE_SAI1_SCK_B_PIN 0 +#elif (RTE_SAI1_SCK_B_PORT_ID == 1) +#define RTE_SAI1_SCK_B_PIN 1 +#define RTE_SAI1_SCK_B_PORT GPIOF +#define RTE_SAI1_SCK_B_BIT 8 +#else +#error "Invalid SAI1_SCK_B Pin Configuration!" +#endif + +// SAI1_MCLK_B Pin <0=>Not Used <1=>PF7 +#define RTE_SAI1_MCLK_B_PORT_ID 0 +#if (RTE_SAI1_MCLK_B_PORT_ID == 0) +#define RTE_SAI1_MCLK_B_PIN 0 +#elif (RTE_SAI1_MCLK_B_PORT_ID == 1) +#define RTE_SAI1_MCLK_B_PIN 1 +#define RTE_SAI1_MCLK_B_PORT GPIOF +#define RTE_SAI1_MCLK_B_BIT 7 +#else +#error "Invalid SAI1_MCLK_B Pin Configuration!" +#endif + +// DMA SAI1_A +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <1=>1 <3=>3 +// Selects DMA Stream (only Stream 1 or 3 can be used) +// Channel <0=>0 +// Selects DMA Channel (only Channel 0 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SAI1_A_DMA 0 +#define RTE_SAI1_A_DMA_NUMBER 2 +#define RTE_SAI1_A_DMA_STREAM 1 +#define RTE_SAI1_A_DMA_CHANNEL 0 +#define RTE_SAI1_A_DMA_PRIORITY 0 + +// DMA SAI1_B +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <4=>4 <5=>5 <7=>7 +// Selects DMA Stream (only Stream 4, 5 or 7 can be used) +// Channel <0=>0 <1=>1 +// Selects DMA Channel (only Channel 0 or 1 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SAI1_B_DMA 0 +#define RTE_SAI1_B_DMA_NUMBER 2 +#define RTE_SAI1_B_DMA_STREAM 5 +#define RTE_SAI1_B_DMA_CHANNEL 0 +#define RTE_SAI1_B_DMA_PRIORITY 0 + +// + +// SAI2 (Serial Audio Interface 2) [Driver_SAI2] +// Configuration settings for Driver_SAI2 in component ::CMSIS Driver:SAI +#define RTE_SAI2 0 + +// SAI2_SD_A Pin <0=>Not Used <1=>PD11 <2=>PI6 +#define RTE_SAI2_SD_A_PORT_ID 0 +#if (RTE_SAI2_SD_A_PORT_ID == 0) +#define RTE_SAI2_SD_A_PIN 0 +#elif (RTE_SAI2_SD_A_PORT_ID == 1) +#define RTE_SAI2_SD_A_PIN 1 +#define RTE_SAI2_SD_A_PORT GPIOD +#define RTE_SAI2_SD_A_BIT 11 +#elif (RTE_SAI2_SD_A_PORT_ID == 2) +#define RTE_SAI2_SD_A_PIN 1 +#define RTE_SAI2_SD_A_PORT GPIOI +#define RTE_SAI2_SD_A_BIT 6 +#else +#error "Invalid SAI2_SD_A Pin Configuration!" +#endif + +// SAI2_FS_A Pin <0=>Not Used <1=>PD12 <2=>PI7 +#define RTE_SAI2_FS_A_PORT_ID 0 +#if (RTE_SAI2_FS_A_PORT_ID == 0) +#define RTE_SAI2_FS_A_PIN 0 +#elif (RTE_SAI2_FS_A_PORT_ID == 1) +#define RTE_SAI2_FS_A_PIN 1 +#define RTE_SAI2_FS_A_PORT GPIOD +#define RTE_SAI2_FS_A_BIT 12 +#elif (RTE_SAI2_FS_A_PORT_ID == 2) +#define RTE_SAI2_FS_A_PIN 1 +#define RTE_SAI2_FS_A_PORT GPIOI +#define RTE_SAI2_FS_A_BIT 7 +#else +#error "Invalid SAI2_FS_A Pin Configuration!" +#endif + +// SAI2_SCK_A Pin <0=>Not Used <1=>PD13 <2=>PI5 +#define RTE_SAI2_SCK_A_PORT_ID 0 +#if (RTE_SAI2_SCK_A_PORT_ID == 0) +#define RTE_SAI2_SCK_A_PIN 0 +#elif (RTE_SAI2_SCK_A_PORT_ID == 1) +#define RTE_SAI2_SCK_A_PIN 1 +#define RTE_SAI2_SCK_A_PORT GPIOD +#define RTE_SAI2_SCK_A_BIT 13 +#elif (RTE_SAI2_SCK_A_PORT_ID == 2) +#define RTE_SAI2_SCK_A_PIN 1 +#define RTE_SAI2_SCK_A_PORT GPIOI +#define RTE_SAI2_SCK_A_BIT 5 +#else +#error "Invalid SAI2_SCK_A Pin Configuration!" +#endif + +// SAI2_MCLK_A Pin <0=>Not Used <1=>PE0 <2=>PI4 +#define RTE_SAI2_MCLK_A_PORT_ID 0 +#if (RTE_SAI2_MCLK_A_PORT_ID == 0) +#define RTE_SAI2_MCLK_A_PIN 0 +#elif (RTE_SAI2_MCLK_A_PORT_ID == 1) +#define RTE_SAI2_MCLK_A_PIN 1 +#define RTE_SAI2_MCLK_A_PORT GPIOE +#define RTE_SAI2_MCLK_A_BIT 0 +#elif (RTE_SAI2_MCLK_A_PORT_ID == 2) +#define RTE_SAI2_MCLK_A_PIN 1 +#define RTE_SAI2_MCLK_A_PORT GPIOI +#define RTE_SAI2_MCLK_A_BIT 4 +#else +#error "Invalid SAI2_MCLK_A Pin Configuration!" +#endif + +// SAI2_SD_B Pin <0=>Not Used <1=>PA0 <2=>PE11 <3=>PF11 <4=>PG10 +#define RTE_SAI2_SD_B_PORT_ID 0 +#if (RTE_SAI2_SD_B_PORT_ID == 0) +#define RTE_SAI2_SD_B_PIN 0 +#elif (RTE_SAI2_SD_B_PORT_ID == 1) +#define RTE_SAI2_SD_B_PIN 1 +#define RTE_SAI2_SD_B_PORT GPIOA +#define RTE_SAI2_SD_B_BIT 0 +#elif (RTE_SAI2_SD_B_PORT_ID == 2) +#define RTE_SAI2_SD_B_PIN 1 +#define RTE_SAI2_SD_B_PORT GPIOE +#define RTE_SAI2_SD_B_BIT 11 +#elif (RTE_SAI2_SD_B_PORT_ID == 3) +#define RTE_SAI2_SD_B_PIN 1 +#define RTE_SAI2_SD_B_PORT GPIOF +#define RTE_SAI2_SD_B_BIT 11 +#elif (RTE_SAI2_SD_B_PORT_ID == 4) +#define RTE_SAI2_SD_B_PIN 1 +#define RTE_SAI2_SD_B_PORT GPIOG +#define RTE_SAI2_SD_B_BIT 10 +#else +#error "Invalid SAI2_SD_B Pin Configuration!" +#endif + +// SAI2_FS_B Pin <0=>Not Used <1=>PA12 <2=>PC0 <3=>PE13 <4=>PG9 +#define RTE_SAI2_FS_B_PORT_ID 0 +#if (RTE_SAI2_FS_B_PORT_ID == 0) +#define RTE_SAI2_FS_B_PIN 0 +#elif (RTE_SAI2_FS_B_PORT_ID == 1) +#define RTE_SAI2_FS_B_PIN 1 +#define RTE_SAI2_FS_B_PORT GPIOA +#define RTE_SAI2_FS_B_BIT 12 +#elif (RTE_SAI2_FS_B_PORT_ID == 2) +#define RTE_SAI2_FS_B_PIN 1 +#define RTE_SAI2_FS_B_PORT GPIOC +#define RTE_SAI2_FS_B_BIT 0 +#elif (RTE_SAI2_FS_B_PORT_ID == 3) +#define RTE_SAI2_FS_B_PIN 1 +#define RTE_SAI2_FS_B_PORT GPIOE +#define RTE_SAI2_FS_B_BIT 13 +#elif (RTE_SAI2_FS_B_PORT_ID == 4) +#define RTE_SAI2_FS_B_PIN 1 +#define RTE_SAI2_FS_B_PORT GPIOG +#define RTE_SAI2_FS_B_BIT 9 +#else +#error "Invalid SAI2_FS_B Pin Configuration!" +#endif + +// SAI2_SCK_B Pin <0=>Not Used <1=>PA2 <2=>PE12 <3=>PH2 +#define RTE_SAI2_SCK_B_PORT_ID 0 +#if (RTE_SAI2_SCK_B_PORT_ID == 0) +#define RTE_SAI2_SCK_B_PIN 0 +#elif (RTE_SAI2_SCK_B_PORT_ID == 1) +#define RTE_SAI2_SCK_B_PIN 1 +#define RTE_SAI2_SCK_B_PORT GPIOA +#define RTE_SAI2_SCK_B_BIT 2 +#elif (RTE_SAI2_SCK_B_PORT_ID == 2) +#define RTE_SAI2_SCK_B_PIN 1 +#define RTE_SAI2_SCK_B_PORT GPIOE +#define RTE_SAI2_SCK_B_BIT 12 +#elif (RTE_SAI2_SCK_B_PORT_ID == 3) +#define RTE_SAI2_SCK_B_PIN 1 +#define RTE_SAI2_SCK_B_PORT GPIOH +#define RTE_SAI2_SCK_B_BIT 2 +#else +#error "Invalid SAI2_SCK_B Pin Configuration!" +#endif + +// SAI2_MCLK_B Pin <0=>Not Used <1=>PA1 <2=>PE6 <3=>PE14 <4=>PH3 +#define RTE_SAI2_MCLK_B_PORT_ID 0 +#if (RTE_SAI2_MCLK_B_PORT_ID == 0) +#define RTE_SAI2_MCLK_B_PIN 0 +#elif (RTE_SAI2_MCLK_B_PORT_ID == 1) +#define RTE_SAI2_MCLK_B_PIN 1 +#define RTE_SAI2_MCLK_B_PORT GPIOA +#define RTE_SAI2_MCLK_B_BIT 1 +#elif (RTE_SAI2_MCLK_B_PORT_ID == 2) +#define RTE_SAI2_MCLK_B_PIN 1 +#define RTE_SAI2_MCLK_B_PORT GPIOE +#define RTE_SAI2_MCLK_B_BIT 6 +#elif (RTE_SAI2_MCLK_B_PORT_ID == 3) +#define RTE_SAI2_MCLK_B_PIN 1 +#define RTE_SAI2_MCLK_B_PORT GPIOE +#define RTE_SAI2_MCLK_B_BIT 14 +#elif (RTE_SAI2_MCLK_B_PORT_ID == 4) +#define RTE_SAI2_MCLK_B_PIN 1 +#define RTE_SAI2_MCLK_B_PORT GPIOH +#define RTE_SAI2_MCLK_B_BIT 3 +#else +#error "Invalid SAI2_MCLK_B Pin Configuration!" +#endif + +// DMA SAI2_A +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <4=>4 +// Selects DMA Stream (only Stream 4 can be used) +// Channel <3=>3 +// Selects DMA Channel (only Channel 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SAI2_A_DMA 0 +#define RTE_SAI2_A_DMA_NUMBER 2 +#define RTE_SAI2_A_DMA_STREAM 4 +#define RTE_SAI2_A_DMA_CHANNEL 3 +#define RTE_SAI2_A_DMA_PRIORITY 0 + +// DMA SAI2_B +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <6=>6 <7=>7 +// Selects DMA Stream (only Stream 6 or 7 can be used) +// Channel <0=>0 <3=>3 +// Selects DMA Channel (only Channel 0 or 3 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SAI2_B_DMA 0 +#define RTE_SAI2_B_DMA_NUMBER 2 +#define RTE_SAI2_B_DMA_STREAM 7 +#define RTE_SAI2_B_DMA_CHANNEL 0 +#define RTE_SAI2_B_DMA_PRIORITY 0 + +// + + +// SDMMC1 (SD/SDIO/MMC card host interface 1) [Driver_MCI0] +// Configuration settings for Driver_MCI0 in component ::CMSIS Driver:MCI +#define RTE_SDMMC1 0 + +// SDMMC Peripheral Bus +// SDMMC1_CK Pin <0=>PC12 +#define RTE_SDMMC1_CK_PORT_ID 0 +#if (RTE_SDMMC1_CK_PORT_ID == 0) + #define RTE_SDMMC1_CK_PORT GPIOC + #define RTE_SDMMC1_CK_PIN GPIO_PIN_12 +#else + #error "Invalid SDMMC1_CLK Pin Configuration!" +#endif +// SDMMC1_CMD Pin <0=>PD2 +#define RTE_SDMMC1_CMD_PORT_ID 0 +#if (RTE_SDMMC1_CMD_PORT_ID == 0) + #define RTE_SDMMC1_CMD_PORT GPIOD + #define RTE_SDMMC1_CMD_PIN GPIO_PIN_2 +#else + #error "Invalid SDMMC1_CMD Pin Configuration!" +#endif +// SDMMC1_D0 Pin <0=>PC8 +#define RTE_SDMMC1_D0_PORT_ID 0 +#if (RTE_SDMMC1_D0_PORT_ID == 0) + #define RTE_SDMMC1_D0_PORT GPIOC + #define RTE_SDMMC1_D0_PIN GPIO_PIN_8 +#else + #error "Invalid SDMMC1_D0 Pin Configuration!" +#endif +// SDMMC1_D[1 .. 3] +#define RTE_SDMMC1_BUS_WIDTH_4 1 +// SDMMC1_D1 Pin <0=>PC9 +#define RTE_SDMMC1_D1_PORT_ID 0 +#if (RTE_SDMMC1_D1_PORT_ID == 0) + #define RTE_SDMMC1_D1_PORT GPIOC + #define RTE_SDMMC1_D1_PIN GPIO_PIN_9 +#else + #error "Invalid SDMMC1_D1 Pin Configuration!" +#endif +// SDMMC1_D2 Pin <0=>PC10 +#define RTE_SDMMC1_D2_PORT_ID 0 +#if (RTE_SDMMC1_D2_PORT_ID == 0) + #define RTE_SDMMC1_D2_PORT GPIOC + #define RTE_SDMMC1_D2_PIN GPIO_PIN_10 +#else + #error "Invalid SDMMC1_D2 Pin Configuration!" +#endif +// SDMMC1_D3 Pin <0=>PC11 +#define RTE_SDMMC1_D3_PORT_ID 0 +#if (RTE_SDMMC1_D3_PORT_ID == 0) + #define RTE_SDMMC1_D3_PORT GPIOC + #define RTE_SDMMC1_D3_PIN GPIO_PIN_11 +#else + #error "Invalid SDMMC1_D3 Pin Configuration!" +#endif +// SDMMC1_D[1 .. 3] +// SDMMC1_D[4 .. 7] +#define RTE_SDMMC1_BUS_WIDTH_8 0 +// SDMMC1_D4 Pin <0=>PB8 +#define RTE_SDMMC1_D4_PORT_ID 0 +#if (RTE_SDMMC1_D4_PORT_ID == 0) + #define RTE_SDMMC1_D4_PORT GPIOB + #define RTE_SDMMC1_D4_PIN GPIO_PIN_8 +#else + #error "Invalid SDMMC1_D4 Pin Configuration!" +#endif +// SDMMC1_D5 Pin <0=>PB9 +#define RTE_SDMMC1_D5_PORT_ID 0 +#if (RTE_SDMMC1_D5_PORT_ID == 0) + #define RTE_SDMMC1_D5_PORT GPIOB + #define RTE_SDMMC1_D5_PIN GPIO_PIN_9 +#else + #error "Invalid SDMMC1_D5 Pin Configuration!" +#endif +// SDMMC1_D6 Pin <0=>PC6 +#define RTE_SDMMC1_D6_PORT_ID 0 +#if (RTE_SDMMC1_D6_PORT_ID == 0) + #define RTE_SDMMC1_D6_PORT GPIOC + #define RTE_SDMMC1_D6_PIN GPIO_PIN_6 +#else + #error "Invalid SDMMC1_D6 Pin Configuration!" +#endif +// SDMMC1_D7 Pin <0=>PC7 +#define RTE_SDMMC1_D7_PORT_ID 0 +#if (RTE_SDMMC1_D7_PORT_ID == 0) + #define RTE_SDMMC1_D7_PORT GPIOC + #define RTE_SDMMC1_D7_PIN GPIO_PIN_7 +#else + #error "Invalid SDMMC1_D7 Pin Configuration!" +#endif +// SDMMC1_D[4 .. 7] +// SDMMC Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// Pull Resistor <0=>Inactive <1=>Pull-up <2=>Pull-down +// Select Pin Pull Resistor function +// +#define RTE_SDMMC1_CD_PIN_EN 0 +#define RTE_SDMMC1_CD_ACTIVE 0 +#define RTE_SDMMC1_CD_PORT GPIO_PORT(0) +#define RTE_SDMMC1_CD_PIN 0 +#define RTE_SDMMC1_CD_PULL 1 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// Pull Resistor <0=>Inactive <1=>Pull-up <2=>Pull-down +// Select Pin Pull Resistor function +// +#define RTE_SDMMC1_WP_EN 0 +#define RTE_SDMMC1_WP_ACTIVE 0 +#define RTE_SDMMC1_WP_PORT GPIO_PORT(0) +#define RTE_SDMMC1_WP_PIN 0 +#define RTE_SDMMC1_WP_PULL 1 + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDMMC1_RX_DMA 1 +#define RTE_SDMMC1_RX_DMA_NUMBER 2 +#define RTE_SDMMC1_RX_DMA_STREAM 3 +#define RTE_SDMMC1_RX_DMA_CHANNEL 4 +#define RTE_SDMMC1_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <3=>3 <6=>6 +// Selects DMA Stream (only Stream 3 or 6 can be used) +// Channel <4=>4 +// Selects DMA Channel (only Channel 4 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDMMC1_TX_DMA 1 +#define RTE_SDMMC1_TX_DMA_NUMBER 2 +#define RTE_SDMMC1_TX_DMA_STREAM 6 +#define RTE_SDMMC1_TX_DMA_CHANNEL 4 +#define RTE_SDMMC1_TX_DMA_PRIORITY 0 + +// + + +// SDMMC2 (SD/SDIO/MMC card host interface 2) [Driver_MCI1] +// Configuration settings for Driver_MCI1 in component ::CMSIS Driver:MCI +#define RTE_SDMMC2 0 + +// SDMMC Peripheral Bus +// SDMMC2_CK Pin <0=>PD6 +#define RTE_SDMMC2_CK_PORT_ID 0 +#if (RTE_SDMMC2_CK_PORT_ID == 0) + #define RTE_SDMMC2_CK_PORT GPIOD + #define RTE_SDMMC2_CK_PIN GPIO_PIN_6 + #define RTE_SDMMC2_CK_AF GPIO_AF11_SDMMC2 +#else + #error "Invalid SDMMC2_CLK Pin Configuration!" +#endif +// SDMMC2_CMD Pin <0=>PD7 +#define RTE_SDMMC2_CMD_PORT_ID 0 +#if (RTE_SDMMC2_CMD_PORT_ID == 0) + #define RTE_SDMMC2_CMD_PORT GPIOD + #define RTE_SDMMC2_CMD_PIN GPIO_PIN_7 + #define RTE_SDMMC2_CMD_AF GPIO_AF11_SDMMC2 +#else + #error "Invalid SDMMC2_CMD Pin Configuration!" +#endif +// SDMMC2_D0 Pin <0=>PB14 <1=>PG9 +#define RTE_SDMMC2_D0_PORT_ID 0 +#if (RTE_SDMMC2_D0_PORT_ID == 0) + #define RTE_SDMMC2_D0_PORT GPIOB + #define RTE_SDMMC2_D0_PIN GPIO_PIN_14 + #define RTE_SDMMC2_D0_AF GPIO_AF10_SDMMC2 +#elif (RTE_SDMMC2_D0_PORT_ID == 1) + #define RTE_SDMMC2_D0_PORT GPIOG + #define RTE_SDMMC2_D0_PIN GPIO_PIN_9 + #define RTE_SDMMC2_D0_AF GPIO_AF11_SDMMC2 +#else + #error "Invalid SDMMC2_D0 Pin Configuration!" +#endif +// SDMMC2_D[1 .. 3] +#define RTE_SDMMC2_BUS_WIDTH_4 1 +// SDMMC2_D1 Pin <0=>PB15 <1=>PG10 +#define RTE_SDMMC2_D1_PORT_ID 0 +#if (RTE_SDMMC2_D1_PORT_ID == 0) + #define RTE_SDMMC2_D1_PORT GPIOB + #define RTE_SDMMC2_D1_PIN GPIO_PIN_15 + #define RTE_SDMMC2_D1_AF GPIO_AF10_SDMMC2 +#elif (RTE_SDMMC2_D1_PORT_ID == 1) + #define RTE_SDMMC2_D1_PORT GPIOG + #define RTE_SDMMC2_D1_PIN GPIO_PIN_10 + #define RTE_SDMMC2_D1_AF GPIO_AF11_SDMMC2 +#else + #error "Invalid SDMMC2_D1 Pin Configuration!" +#endif +// SDMMC2_D2 Pin <0=>PB3 <1=>PG11 +#define RTE_SDMMC2_D2_PORT_ID 0 +#if (RTE_SDMMC2_D2_PORT_ID == 0) + #define RTE_SDMMC2_D2_PORT GPIOB + #define RTE_SDMMC2_D2_PIN GPIO_PIN_3 + #define RTE_SDMMC2_D2_AF GPIO_AF10_SDMMC2 +#elif (RTE_SDMMC2_D2_PORT_ID == 1) + #define RTE_SDMMC2_D2_PORT GPIOG + #define RTE_SDMMC2_D2_PIN GPIO_PIN_11 + #define RTE_SDMMC2_D2_AF GPIO_AF10_SDMMC2 +#else + #error "Invalid SDMMC2_D2 Pin Configuration!" +#endif +// SDMMC2_D3 Pin <0=>PB4 <1=>PG12 +#define RTE_SDMMC2_D3_PORT_ID 0 +#if (RTE_SDMMC2_D3_PORT_ID == 0) + #define RTE_SDMMC2_D3_PORT GPIOB + #define RTE_SDMMC2_D3_PIN GPIO_PIN_4 + #define RTE_SDMMC2_D3_AF GPIO_AF10_SDMMC2 +#elif (RTE_SDMMC2_D3_PORT_ID == 1) + #define RTE_SDMMC2_D3_PORT GPIOG + #define RTE_SDMMC2_D3_PIN GPIO_PIN_12 + #define RTE_SDMMC2_D3_AF GPIO_AF11_SDMMC2 +#else + #error "Invalid SDMMC2_D3 Pin Configuration!" +#endif +// SDMMC2_D[1 .. 3] +// SDMMC2_D[4 .. 7] +#define RTE_SDMMC2_BUS_WIDTH_8 0 +// SDMMC2_D4 Pin <0=>PB8 +#define RTE_SDMMC2_D4_PORT_ID 0 +#if (RTE_SDMMC2_D4_PORT_ID == 0) + #define RTE_SDMMC2_D4_PORT GPIOB + #define RTE_SDMMC2_D4_PIN GPIO_PIN_8 + #define RTE_SDMMC2_D4_AF GPIO_AF10_SDMMC2 +#else + #error "Invalid SDMMC2_D4 Pin Configuration!" +#endif +// SDMMC2_D5 Pin <0=>PB9 +#define RTE_SDMMC2_D5_PORT_ID 0 +#if (RTE_SDMMC2_D5_PORT_ID == 0) + #define RTE_SDMMC2_D5_PORT GPIOB + #define RTE_SDMMC2_D5_PIN GPIO_PIN_9 + #define RTE_SDMMC2_D5_AF GPIO_AF10_SDMMC2 +#else + #error "Invalid SDMMC2_D5 Pin Configuration!" +#endif +// SDMMC2_D6 Pin <0=>PC6 +#define RTE_SDMMC2_D6_PORT_ID 0 +#if (RTE_SDMMC2_D6_PORT_ID == 0) + #define RTE_SDMMC2_D6_PORT GPIOC + #define RTE_SDMMC2_D6_PIN GPIO_PIN_6 + #define RTE_SDMMC2_D6_AF GPIO_AF10_SDMMC2 +#else + #error "Invalid SDMMC2_D6 Pin Configuration!" +#endif +// SDMMC2_D7 Pin <0=>PC7 +#define RTE_SDMMC2_D7_PORT_ID 0 +#if (RTE_SDMMC2_D7_PORT_ID == 0) + #define RTE_SDMMC2_D7_PORT GPIOC + #define RTE_SDMMC2_D7_PIN GPIO_PIN_7 + #define RTE_SDMMC2_D7_AF GPIO_AF10_SDMMC2 +#else + #error "Invalid SDMMC2_D7 Pin Configuration!" +#endif +// SDMMC2_D[4 .. 7] +// SDMMC Peripheral Bus + +// Card Detect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// Pull Resistor <0=>Inactive <1=>Pull-up <2=>Pull-down +// Select Pin Pull Resistor function +// +#define RTE_SDMMC2_CD_PIN_EN 1 +#define RTE_SDMMC2_CD_ACTIVE 0 +#define RTE_SDMMC2_CD_PORT GPIO_PORT(2) +#define RTE_SDMMC2_CD_PIN 12 +#define RTE_SDMMC2_CD_PULL 1 + +// Write Protect Pin +// Configure Pin if exists +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// Pull Resistor <0=>Inactive <1=>Pull-up <2=>Pull-down +// Select Pin Pull Resistor function +// +#define RTE_SDMMC2_WP_EN 0 +#define RTE_SDMMC2_WP_ACTIVE 0 +#define RTE_SDMMC2_WP_PORT GPIO_PORT(0) +#define RTE_SDMMC2_WP_PIN 0 +#define RTE_SDMMC2_WP_PULL 1 + +// DMA Rx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <11=>11 +// Selects DMA Channel (only Channel 11 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDMMC2_RX_DMA 1 +#define RTE_SDMMC2_RX_DMA_NUMBER 2 +#define RTE_SDMMC2_RX_DMA_STREAM 0 +#define RTE_SDMMC2_RX_DMA_CHANNEL 11 +#define RTE_SDMMC2_RX_DMA_PRIORITY 0 + +// DMA Tx +// Number <2=>2 +// Selects DMA Number (only DMA2 can be used) +// Stream <0=>0 <5=>5 +// Selects DMA Stream (only Stream 0 or 5 can be used) +// Channel <11=>11 +// Selects DMA Channel (only Channel 11 can be used) +// Priority <0=>Low <1=>Medium <2=>High <3=>Very High +// Selects DMA Priority +// +#define RTE_SDMMC2_TX_DMA 1 +#define RTE_SDMMC2_TX_DMA_NUMBER 2 +#define RTE_SDMMC2_TX_DMA_STREAM 5 +#define RTE_SDMMC2_TX_DMA_CHANNEL 11 +#define RTE_SDMMC2_TX_DMA_PRIORITY 0 + +// + + +// CAN1 (Controller Area Network 1) [Driver_CAN1] +// Configuration settings for Driver_CAN1 in component ::CMSIS Driver:CAN +#define RTE_CAN1 0 + +// CAN1_RX Pin <0=>PA11 <1=>PB8 <2=>PD0 <3=>PI9 <4=>PH14 +#define RTE_CAN1_RX_PORT_ID 0 +#if (RTE_CAN1_RX_PORT_ID == 0) +#define RTE_CAN1_RX_PORT GPIOA +#define RTE_CAN1_RX_BIT GPIO_PIN_11 +#elif (RTE_CAN1_RX_PORT_ID == 1) +#define RTE_CAN1_RX_PORT GPIOB +#define RTE_CAN1_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN1_RX_PORT_ID == 2) +#define RTE_CAN1_RX_PORT GPIOD +#define RTE_CAN1_RX_BIT GPIO_PIN_0 +#elif (RTE_CAN1_RX_PORT_ID == 3) +#define RTE_CAN1_RX_PORT GPIOI +#define RTE_CAN1_RX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_RX_PORT_ID == 4) +#define RTE_CAN1_RX_PORT GPIOH +#define RTE_CAN1_RX_BIT GPIO_PIN_14 +#else +#error "Invalid CAN1_RX Pin Configuration!" +#endif + +// CAN1_TX Pin <0=>PA12 <1=>PB9 <2=>PD1 <3=>PH13 +#define RTE_CAN1_TX_PORT_ID 0 +#if (RTE_CAN1_TX_PORT_ID == 0) +#define RTE_CAN1_TX_PORT GPIOA +#define RTE_CAN1_TX_BIT GPIO_PIN_12 +#elif (RTE_CAN1_TX_PORT_ID == 1) +#define RTE_CAN1_TX_PORT GPIOB +#define RTE_CAN1_TX_BIT GPIO_PIN_9 +#elif (RTE_CAN1_TX_PORT_ID == 2) +#define RTE_CAN1_TX_PORT GPIOD +#define RTE_CAN1_TX_BIT GPIO_PIN_1 +#elif (RTE_CAN1_TX_PORT_ID == 3) +#define RTE_CAN1_TX_PORT GPIOH +#define RTE_CAN1_TX_BIT GPIO_PIN_13 +#else +#error "Invalid CAN1_TX Pin Configuration!" +#endif + +// + + +// CAN2 (Controller Area Network 2) [Driver_CAN2] +// Configuration settings for Driver_CAN2 in component ::CMSIS Driver:CAN +#define RTE_CAN2 0 + +// CAN2_RX Pin <0=>PB5 <1=>PB12 +#define RTE_CAN2_RX_PORT_ID 0 +#if (RTE_CAN2_RX_PORT_ID == 0) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_5 +#elif (RTE_CAN2_RX_PORT_ID == 1) +#define RTE_CAN2_RX_PORT GPIOB +#define RTE_CAN2_RX_BIT GPIO_PIN_12 +#else +#error "Invalid CAN2_RX Pin Configuration!" +#endif + +// CAN2_TX Pin <0=>PB6 <1=>PB13 +#define RTE_CAN2_TX_PORT_ID 0 +#if (RTE_CAN2_TX_PORT_ID == 0) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_6 +#elif (RTE_CAN2_TX_PORT_ID == 1) +#define RTE_CAN2_TX_PORT GPIOB +#define RTE_CAN2_TX_BIT GPIO_PIN_13 +#else +#error "Invalid CAN2_TX Pin Configuration!" +#endif + +// + + +// CAN3 (Controller Area Network 3) [Driver_CAN3] +// Configuration settings for Driver_CAN3 in component ::CMSIS Driver:CAN +// Available only on STM32F76x and STM32F77x device series +#define RTE_CAN3 0 + +// CAN3_RX Pin <0=>PA8 <1=>PB3 +#define RTE_CAN3_RX_PORT_ID 0 +#if (RTE_CAN3_RX_PORT_ID == 0) +#define RTE_CAN3_RX_PORT GPIOA +#define RTE_CAN3_RX_BIT GPIO_PIN_8 +#elif (RTE_CAN3_RX_PORT_ID == 1) +#define RTE_CAN3_RX_PORT GPIOB +#define RTE_CAN3_RX_BIT GPIO_PIN_3 +#else +#error "Invalid CAN3_RX Pin Configuration!" +#endif + +// CAN3_TX Pin <0=>PA15 <1=>PB4 +#define RTE_CAN3_TX_PORT_ID 0 +#if (RTE_CAN3_TX_PORT_ID == 0) +#define RTE_CAN3_TX_PORT GPIOA +#define RTE_CAN3_TX_BIT GPIO_PIN_15 +#elif (RTE_CAN3_TX_PORT_ID == 1) +#define RTE_CAN3_TX_PORT GPIOB +#define RTE_CAN3_TX_BIT GPIO_PIN_4 +#else +#error "Invalid CAN3_TX Pin Configuration!" +#endif + +// + + +// ETH (Ethernet Interface) [Driver_ETH_MAC0] +// Configuration settings for Driver_ETH_MAC0 in component ::CMSIS Driver:Ethernet MAC +#define RTE_ETH 0 + +// MII (Media Independent Interface) +#define RTE_ETH_MII 1 + +// ETH_MII_TX_CLK Pin <0=>PC3 +#define RTE_ETH_MII_TX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_TX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_TX_CLK_PORT GPIOC +#define RTE_ETH_MII_TX_CLK_PIN 3 +#else +#error "Invalid ETH_MII_TX_CLK Pin Configuration!" +#endif +// ETH_MII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_MII_TXD0_PORT_ID 0 +#if (RTE_ETH_MII_TXD0_PORT_ID == 0) +#define RTE_ETH_MII_TXD0_PORT GPIOB +#define RTE_ETH_MII_TXD0_PIN 12 +#elif (RTE_ETH_MII_TXD0_PORT_ID == 1) +#define RTE_ETH_MII_TXD0_PORT GPIOG +#define RTE_ETH_MII_TXD0_PIN 13 +#else +#error "Invalid ETH_MII_TXD0 Pin Configuration!" +#endif +// ETH_MII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_MII_TXD1_PORT_ID 0 +#if (RTE_ETH_MII_TXD1_PORT_ID == 0) +#define RTE_ETH_MII_TXD1_PORT GPIOB +#define RTE_ETH_MII_TXD1_PIN 13 +#elif (RTE_ETH_MII_TXD1_PORT_ID == 1) +#define RTE_ETH_MII_TXD1_PORT GPIOG +#define RTE_ETH_MII_TXD1_PIN 14 +#else +#error "Invalid ETH_MII_TXD1 Pin Configuration!" +#endif +// ETH_MII_TXD2 Pin <0=>PC2 +#define RTE_ETH_MII_TXD2_PORT_ID 0 +#if (RTE_ETH_MII_TXD2_PORT_ID == 0) +#define RTE_ETH_MII_TXD2_PORT GPIOC +#define RTE_ETH_MII_TXD2_PIN 2 +#else +#error "Invalid ETH_MII_TXD2 Pin Configuration!" +#endif +// ETH_MII_TXD3 Pin <0=>PB8 <1=>PE2 +#define RTE_ETH_MII_TXD3_PORT_ID 0 +#if (RTE_ETH_MII_TXD3_PORT_ID == 0) +#define RTE_ETH_MII_TXD3_PORT GPIOB +#define RTE_ETH_MII_TXD3_PIN 8 +#elif (RTE_ETH_MII_TXD3_PORT_ID == 1) +#define RTE_ETH_MII_TXD3_PORT GPIOE +#define RTE_ETH_MII_TXD3_PIN 2 +#else +#error "Invalid ETH_MII_TXD3 Pin Configuration!" +#endif +// ETH_MII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_MII_TX_EN_PORT_ID 0 +#if (RTE_ETH_MII_TX_EN_PORT_ID == 0) +#define RTE_ETH_MII_TX_EN_PORT GPIOB +#define RTE_ETH_MII_TX_EN_PIN 11 +#elif (RTE_ETH_MII_TX_EN_PORT_ID == 1) +#define RTE_ETH_MII_TX_EN_PORT GPIOG +#define RTE_ETH_MII_TX_EN_PIN 11 +#else +#error "Invalid ETH_MII_TX_EN Pin Configuration!" +#endif +// ETH_MII_RX_CLK Pin <0=>PA1 +#define RTE_ETH_MII_RX_CLK_PORT_ID 0 +#if (RTE_ETH_MII_RX_CLK_PORT_ID == 0) +#define RTE_ETH_MII_RX_CLK_PORT GPIOA +#define RTE_ETH_MII_RX_CLK_PIN 1 +#else +#error "Invalid ETH_MII_RX_CLK Pin Configuration!" +#endif +// ETH_MII_RXD0 Pin <0=>PC4 +#define RTE_ETH_MII_RXD0_PORT_ID 0 +#if (RTE_ETH_MII_RXD0_PORT_ID == 0) +#define RTE_ETH_MII_RXD0_PORT GPIOC +#define RTE_ETH_MII_RXD0_PIN 4 +#else +#error "Invalid ETH_MII_RXD0 Pin Configuration!" +#endif +// ETH_MII_RXD1 Pin <0=>PC5 +#define RTE_ETH_MII_RXD1_PORT_ID 0 +#if (RTE_ETH_MII_RXD1_PORT_ID == 0) +#define RTE_ETH_MII_RXD1_PORT GPIOC +#define RTE_ETH_MII_RXD1_PIN 5 +#else +#error "Invalid ETH_MII_RXD1 Pin Configuration!" +#endif +// ETH_MII_RXD2 Pin <0=>PB0 <1=>PH6 +#define RTE_ETH_MII_RXD2_PORT_ID 0 +#if (RTE_ETH_MII_RXD2_PORT_ID == 0) +#define RTE_ETH_MII_RXD2_PORT GPIOB +#define RTE_ETH_MII_RXD2_PIN 0 +#elif (RTE_ETH_MII_RXD2_PORT_ID == 1) +#define RTE_ETH_MII_RXD2_PORT GPIOH +#define RTE_ETH_MII_RXD2_PIN 6 +#else +#error "Invalid ETH_MII_RXD2 Pin Configuration!" +#endif +// ETH_MII_RXD3 Pin <0=>PB1 <1=>PH7 +#define RTE_ETH_MII_RXD3_PORT_ID 0 +#if (RTE_ETH_MII_RXD3_PORT_ID == 0) +#define RTE_ETH_MII_RXD3_PORT GPIOB +#define RTE_ETH_MII_RXD3_PIN 1 +#elif (RTE_ETH_MII_RXD3_PORT_ID == 1) +#define RTE_ETH_MII_RXD3_PORT GPIOH +#define RTE_ETH_MII_RXD3_PIN 7 +#else +#error "Invalid ETH_MII_RXD3 Pin Configuration!" +#endif +// ETH_MII_RX_DV Pin <0=>PA7 +#define RTE_ETH_MII_RX_DV_PORT_ID 0 +#if (RTE_ETH_MII_RX_DV_PORT_ID == 0) +#define RTE_ETH_MII_RX_DV_PORT GPIOA +#define RTE_ETH_MII_RX_DV_PIN 7 +#else +#error "Invalid ETH_MII_RX_DV Pin Configuration!" +#endif +// ETH_MII_RX_ER Pin <0=>Not Used <1=>PB10 <2=>PI10 +#define RTE_ETH_MII_RX_ER_PORT_ID 0 +#if (RTE_ETH_MII_RX_ER_PORT_ID == 0) +#define RTE_ETH_MII_RX_ER_PORT NULL +#elif (RTE_ETH_MII_RX_ER_PORT_ID == 1) +#define RTE_ETH_MII_RX_ER_PORT GPIOB +#define RTE_ETH_MII_RX_ER_PIN 10 +#elif (RTE_ETH_MII_RX_ER_PORT_ID == 2) +#define RTE_ETH_MII_RX_ER_PORT GPIOI +#define RTE_ETH_MII_RX_ER_PIN 10 +#else +#error "Invalid ETH_MII_RX_ER Pin Configuration!" +#endif +// ETH_MII_CRS Pin <0=>Not Used <1=>PA0 <2=>PH2 +#define RTE_ETH_MII_CRS_PORT_ID 0 +#if (RTE_ETH_MII_CRS_PORT_ID == 0) +#define RTE_ETH_MII_CRS_PORT NULL +#elif (RTE_ETH_MII_CRS_PORT_ID == 1) +#define RTE_ETH_MII_CRS_PORT GPIOA +#define RTE_ETH_MII_CRS_PIN 0 +#elif (RTE_ETH_MII_CRS_PORT_ID == 2) +#define RTE_ETH_MII_CRS_PORT GPIOH +#define RTE_ETH_MII_CRS_PIN 2 +#else +#error "Invalid ETH_MII_CRS Pin Configuration!" +#endif +// ETH_MII_COL Pin <0=>Not Used <1=>PA3 <2=>PH3 +#define RTE_ETH_MII_COL_PORT_ID 0 +#if (RTE_ETH_MII_COL_PORT_ID == 0) +#define RTE_ETH_MII_COL_PORT NULL +#elif (RTE_ETH_MII_COL_PORT_ID == 1) +#define RTE_ETH_MII_COL_PORT GPIOA +#define RTE_ETH_MII_COL_PIN 3 +#elif (RTE_ETH_MII_COL_PORT_ID == 2) +#define RTE_ETH_MII_COL_PORT GPIOH +#define RTE_ETH_MII_COL_PIN 3 +#else +#error "Invalid ETH_MII_COL Pin Configuration!" +#endif + +// + +// RMII (Reduced Media Independent Interface) +#define RTE_ETH_RMII 0 + +// ETH_RMII_TXD0 Pin <0=>PB12 <1=>PG13 +#define RTE_ETH_RMII_TXD0_PORT_ID 0 +#if (RTE_ETH_RMII_TXD0_PORT_ID == 0) +#define RTE_ETH_RMII_TXD0_PORT GPIOB +#define RTE_ETH_RMII_TXD0_PIN 12 +#elif (RTE_ETH_RMII_TXD0_PORT_ID == 1) +#define RTE_ETH_RMII_TXD0_PORT GPIOG +#define RTE_ETH_RMII_TXD0_PIN 13 +#else +#error "Invalid ETH_RMII_TXD0 Pin Configuration!" +#endif +// ETH_RMII_TXD1 Pin <0=>PB13 <1=>PG14 +#define RTE_ETH_RMII_TXD1_PORT_ID 0 +#if (RTE_ETH_RMII_TXD1_PORT_ID == 0) +#define RTE_ETH_RMII_TXD1_PORT GPIOB +#define RTE_ETH_RMII_TXD1_PIN 13 +#elif (RTE_ETH_RMII_TXD1_PORT_ID == 1) +#define RTE_ETH_RMII_TXD1_PORT GPIOG +#define RTE_ETH_RMII_TXD1_PIN 14 +#else +#error "Invalid ETH_RMII_TXD1 Pin Configuration!" +#endif +// ETH_RMII_TX_EN Pin <0=>PB11 <1=>PG11 +#define RTE_ETH_RMII_TX_EN_PORT_ID 0 +#if (RTE_ETH_RMII_TX_EN_PORT_ID == 0) +#define RTE_ETH_RMII_TX_EN_PORT GPIOB +#define RTE_ETH_RMII_TX_EN_PIN 11 +#elif (RTE_ETH_RMII_TX_EN_PORT_ID == 1) +#define RTE_ETH_RMII_TX_EN_PORT GPIOG +#define RTE_ETH_RMII_TX_EN_PIN 11 +#else +#error "Invalid ETH_RMII_TX_EN Pin Configuration!" +#endif +// ETH_RMII_RXD0 Pin <0=>PC4 +#define RTE_ETH_RMII_RXD0_PORT_ID 0 +#if (RTE_ETH_RMII_RXD0_PORT_ID == 0) +#define RTE_ETH_RMII_RXD0_PORT GPIOC +#define RTE_ETH_RMII_RXD0_PIN 4 +#else +#error "Invalid ETH_RMII_RXD0 Pin Configuration!" +#endif +// ETH_RMII_RXD1 Pin <0=>PC5 +#define RTE_ETH_RMII_RXD1_PORT_ID 0 +#if (RTE_ETH_RMII_RXD1_PORT_ID == 0) +#define RTE_ETH_RMII_RXD1_PORT GPIOC +#define RTE_ETH_RMII_RXD1_PIN 5 +#else +#error "Invalid ETH_RMII_RXD1 Pin Configuration!" +#endif +// ETH_RMII_REF_CLK Pin <0=>PA1 +#define RTE_ETH_RMII_REF_CLK_PORT_ID 0 +#if (RTE_ETH_RMII_REF_CLK_PORT_ID == 0) +#define RTE_ETH_RMII_REF_CLK_PORT GPIOA +#define RTE_ETH_RMII_REF_CLK_PIN 1 +#else +#error "Invalid ETH_RMII_REF_CLK Pin Configuration!" +#endif +// ETH_RMII_CRS_DV Pin <0=>PA7 +#define RTE_ETH_RMII_CRS_DV_PORT_ID 0 +#if (RTE_ETH_RMII_CRS_DV_PORT_ID == 0) +#define RTE_ETH_RMII_CRS_DV_PORT GPIOA +#define RTE_ETH_RMII_CRS_DV_PIN 7 +#else +#error "Invalid ETH_RMII_CRS_DV Pin Configuration!" +#endif + +// + +// SMI (Station Management Interface) +// Hardware controlled +// Enable peripheral controlled SMI on dedicated pins +#define RTE_ETH_SMI_HW 1 +// ETH_MDC Pin <0=>PC1 +#define RTE_ETH_SMI_MDC_PORT_ID 0 +#if (RTE_ETH_SMI_MDC_PORT_ID == 0) +#define RTE_ETH_SMI_MDC_PORT GPIOC +#define RTE_ETH_SMI_MDC_PIN 1 +#else +#error "Invalid ETH_MDC Pin Configuration!" +#endif +// ETH_MDIO Pin <0=>PA2 +#define RTE_ETH_SMI_MDIO_PORT_ID 0 +#if (RTE_ETH_SMI_MDIO_PORT_ID == 0) +#define RTE_ETH_SMI_MDIO_PORT GPIOA +#define RTE_ETH_SMI_MDIO_PIN 2 +#else +#error "Invalid ETH_MDIO Pin Configuration!" +#endif +// + +// Software controlled +// Enable software controlled SMI on arbitrary GPIO pins +#define RTE_ETH_SMI_SW 0 +// ETH_MDC Pin +// Configure arbitrary GPIO as MDC Pin +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +#define RTE_ETH_SMI_SW_MDC_PORT GPIO_PORT(6) +#define RTE_ETH_SMI_SW_MDC_PIN 7 +// + +// ETH_MDIO Pin +// Configure arbitrary GPIO as MDIO Pin +// GPIO Pxy (x = A..H, y = 0..15) or (x = I, y = 0..11) +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH <8=>GPIOI +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +#define RTE_ETH_SMI_SW_MDIO_PORT GPIO_PORT(6) +#define RTE_ETH_SMI_SW_MDIO_PIN 6 +// +// +// +// DMA Descriptor/Buffer Memory Address <0x20000000-0xE0000000> +// Configure location of the Ethernet DMA Descriptor and Buffer memory +#define RTE_ETH_DMA_MEM_ADDR 0x2000C000 + +// + + +// USB OTG Full-speed +#define RTE_USB_OTG_FS 0 + +// Device [Driver_USBD0] +// Configuration settings for Driver_USBD0 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_FS_DEVICE 1 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +#define RTE_OTG_FS_VBUS_SENSING_PIN 1 +// + +// Host [Driver_USBH0] +// Configuration settings for Driver_USBH0 in component ::CMSIS Driver:USB Host + +#define RTE_USB_OTG_FS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..J, y = 0..15) or (x = K, y = 0..7) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH +// <8=>GPIOI <8=>GPIOJ <9=>GPIOK +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_VBUS_PIN 0 +#define RTE_OTG_FS_VBUS_ACTIVE 0 +#define RTE_OTG_FS_VBUS_PORT GPIO_PORT(0) +#define RTE_OTG_FS_VBUS_BIT 0 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..J, y = 0..15) or (x = K, y = 0..7) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH +// <8=>GPIOI <8=>GPIOJ <9=>GPIOK +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_FS_OC_PIN 0 +#define RTE_OTG_FS_OC_ACTIVE 0 +#define RTE_OTG_FS_OC_PORT GPIO_PORT(0) +#define RTE_OTG_FS_OC_BIT 0 +// + +// + + +// USB OTG High-speed +#define RTE_USB_OTG_HS 0 + +// PHY (Physical Layer) + +// PHY Interface +// <0=>On-chip full-speed PHY +// <1=>External ULPI high-speed PHY +// <2=>Internal UTMI high-speed PHY +#define RTE_USB_OTG_HS_PHY 1 + +// External ULPI Pins (UTMI+ Low Pin Interface) + +// OTG_HS_ULPI_CK Pin <0=>PA5 +#define RTE_USB_OTG_HS_ULPI_CK_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_CK_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_CK_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_CK_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_CK Pin Configuration!" +#endif +// OTG_HS_ULPI_DIR Pin <0=>PI11 <1=>PC2 +#define RTE_USB_OTG_HS_ULPI_DIR_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOI +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 11 +#elif (RTE_USB_OTG_HS_ULPI_DIR_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_DIR_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_DIR_PIN 2 +#else +#error "Invalid OTG_HS_ULPI_DIR Pin Configuration!" +#endif +// OTG_HS_ULPI_STP Pin <0=>PC0 +#define RTE_USB_OTG_HS_ULPI_STP_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_STP_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_STP_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_STP_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_STP Pin Configuration!" +#endif +// OTG_HS_ULPI_NXT Pin <0=>PC3 <1=>PH4 +#define RTE_USB_OTG_HS_ULPI_NXT_PORT_ID 1 +#if (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOC +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 3 +#elif (RTE_USB_OTG_HS_ULPI_NXT_PORT_ID == 1) +#define RTE_USB_OTG_HS_ULPI_NXT_PORT GPIOH +#define RTE_USB_OTG_HS_ULPI_NXT_PIN 4 +#else +#error "Invalid OTG_HS_ULPI_NXT Pin Configuration!" +#endif +// OTG_HS_ULPI_D0 Pin <0=>PA3 +#define RTE_USB_OTG_HS_ULPI_D0_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D0_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D0_PORT GPIOA +#define RTE_USB_OTG_HS_ULPI_D0_PIN 3 +#else +#error "Invalid OTG_HS_ULPI_D0 Pin Configuration!" +#endif +// OTG_HS_ULPI_D1 Pin <0=>PB0 +#define RTE_USB_OTG_HS_ULPI_D1_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D1_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D1_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D1_PIN 0 +#else +#error "Invalid OTG_HS_ULPI_D1 Pin Configuration!" +#endif +// OTG_HS_ULPI_D2 Pin <0=>PB1 +#define RTE_USB_OTG_HS_ULPI_D2_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D2_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D2_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D2_PIN 1 +#else +#error "Invalid OTG_HS_ULPI_D2 Pin Configuration!" +#endif +// OTG_HS_ULPI_D3 Pin <0=>PB10 +#define RTE_USB_OTG_HS_ULPI_D3_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D3_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D3_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D3_PIN 10 +#else +#error "Invalid OTG_HS_ULPI_D3 Pin Configuration!" +#endif +// OTG_HS_ULPI_D4 Pin <0=>PB11 +#define RTE_USB_OTG_HS_ULPI_D4_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D4_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D4_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D4_PIN 11 +#else +#error "Invalid OTG_HS_ULPI_D4 Pin Configuration!" +#endif +// OTG_HS_ULPI_D5 Pin <0=>PB12 +#define RTE_USB_OTG_HS_ULPI_D5_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D5_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D5_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D5_PIN 12 +#else +#error "Invalid OTG_HS_ULPI_D5 Pin Configuration!" +#endif +// OTG_HS_ULPI_D6 Pin <0=>PB13 +#define RTE_USB_OTG_HS_ULPI_D6_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D6_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D6_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D6_PIN 13 +#else +#error "Invalid OTG_HS_ULPI_D6 Pin Configuration!" +#endif +// OTG_HS_ULPI_D7 Pin <0=>PB5 +#define RTE_USB_OTG_HS_ULPI_D7_PORT_ID 0 +#if (RTE_USB_OTG_HS_ULPI_D7_PORT_ID == 0) +#define RTE_USB_OTG_HS_ULPI_D7_PORT GPIOB +#define RTE_USB_OTG_HS_ULPI_D7_PIN 5 +#else +#error "Invalid OTG_HS_ULPI_D7 Pin Configuration!" +#endif + +// + +// + +// Device [Driver_USBD1] +// Configuration settings for Driver_USBD1 in component ::CMSIS Driver:USB Device + +#define RTE_USB_OTG_HS_DEVICE 0 + +// VBUS Sensing Pin +// Enable or disable VBUS sensing +// Relevant only if PHY Interface On-chip full-speed PHY is selected +#define RTE_OTG_HS_VBUS_SENSING_PIN 0 +// + +// Host [Driver_USBH1] +// Configuration settings for Driver_USBH1 in component ::CMSIS Driver:USB Host +#define RTE_USB_OTG_HS_HOST 0 + +// VBUS Power On/Off Pin +// Configure Pin for driving VBUS +// GPIO Pxy (x = A..J, y = 0..15) or (x = K, y = 0..7) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH +// <8=>GPIOI <8=>GPIOJ <9=>GPIOK +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_VBUS_PIN 0 +#define RTE_OTG_HS_VBUS_ACTIVE 0 +#define RTE_OTG_HS_VBUS_PORT GPIO_PORT(0) +#define RTE_OTG_HS_VBUS_BIT 0 + +// Overcurrent Detection Pin +// Configure Pin for overcurrent detection +// GPIO Pxy (x = A..J, y = 0..15) or (x = K, y = 0..7) +// Active State <0=>Low <1=>High +// Selects Active State Logical Level +// Port <0=>GPIOA <1=>GPIOB <2=>GPIOC <3=>GPIOD +// <4=>GPIOE <5=>GPIOF <6=>GPIOG <7=>GPIOH +// <8=>GPIOI <8=>GPIOJ <9=>GPIOK +// Selects Port Name +// Bit <0-15> +// Selects Port Bit +// +#define RTE_OTG_HS_OC_PIN 0 +#define RTE_OTG_HS_OC_ACTIVE 0 +#define RTE_OTG_HS_OC_PORT GPIO_PORT(0) +#define RTE_OTG_HS_OC_BIT 0 +// + +// DMA +// Use dedicated DMA for transfers +// If DMA is used all USB transfer data buffers have to be 4-byte aligned. +#define RTE_OTG_HS_DMA 0 + +// + + +#endif /* __RTE_DEVICE_H */ diff --git a/RTE/Device/STM32F746NGHx/startup_stm32f746xx.s b/RTE/Device/STM32F746NGHx/startup_stm32f746xx.s new file mode 100644 index 0000000..f8d684b --- /dev/null +++ b/RTE/Device/STM32F746NGHx/startup_stm32f746xx.s @@ -0,0 +1,483 @@ +;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f746xx.s +;* Author : MCD Application Team +;* Description : STM32F746xx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM7 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDMMC1_IRQHandler ; SDMMC1 + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD RNG_IRQHandler ; Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QUADSPI + DCD LPTIM1_IRQHandler ; LPTIM1 + DCD CEC_IRQHandler ; HDMI_CEC + DCD I2C4_EV_IRQHandler ; I2C4 Event + DCD I2C4_ER_IRQHandler ; I2C4 Error + DCD SPDIF_RX_IRQHandler ; SPDIF_RX +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDMMC1_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT I2C4_EV_IRQHandler [WEAK] + EXPORT I2C4_ER_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDMMC1_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +SAI2_IRQHandler +QUADSPI_IRQHandler +LPTIM1_IRQHandler +CEC_IRQHandler +I2C4_EV_IRQHandler +I2C4_ER_IRQHandler +SPDIF_RX_IRQHandler + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE***** diff --git a/RTE/Device/STM32F746NGHx/stm32f7xx_hal_conf.h b/RTE/Device/STM32F746NGHx/stm32f7xx_hal_conf.h new file mode 100644 index 0000000..dbb35f6 --- /dev/null +++ b/RTE/Device/STM32F746NGHx/stm32f7xx_hal_conf.h @@ -0,0 +1,596 @@ +/** + ****************************************************************************** + * @file stm32f7xx_hal_conf.h + * @author MCD Application Team + * @brief HAL configuration file + * + * @note modified by ARM + * The modifications allow to use this file as User Code Template + * within the Device Family Pack. + ****************************************************************************** + * @attention + * + *

© Copyright (c) 2016 STMicroelectronics. + * All rights reserved.

+ * + * This software component is licensed by ST under BSD 3-Clause license, + * the "License"; You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ****************************************************************************** + */ + +/* Define to prevent recursive inclusion -------------------------------------*/ +#ifndef __STM32F7xx_HAL_CONF_H +#define __STM32F7xx_HAL_CONF_H + +#ifdef _RTE_ +#include "RTE_Components.h" // Component selection +#endif + +#ifdef __cplusplus + extern "C" { +#endif + +/* Exported types ------------------------------------------------------------*/ +/* Exported constants --------------------------------------------------------*/ + +/* ########################## Module Selection ############################## */ +/** + * @brief This is the list of modules to be used in the HAL driver + */ +#ifdef RTE_DEVICE_HAL_COMMON +#define HAL_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ADC +#define HAL_ADC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CAN +#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_LEGACY_MODULE_ENABLED */ +#endif +#ifdef RTE_DEVICE_HAL_CEC +#define HAL_CEC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CRC +#define HAL_CRC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CRYP +#define HAL_CRYP_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DAC +#define HAL_DAC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DCMI +#define HAL_DCMI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DMA +#define HAL_DMA_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DMA2D +#define HAL_DMA2D_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_ETH +#define HAL_ETH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_EXTI +#define HAL_EXTI_MODULE_ENABLED +#endif +#if defined (RTE_DEVICE_HAL_FLASH) || defined (RTE_DEVICE_HAL_COMMON) +#define HAL_FLASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_NAND +#define HAL_NAND_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_NOR +#define HAL_NOR_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SRAM +#define HAL_SRAM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SDRAM +#define HAL_SDRAM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_HASH +#define HAL_HASH_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_GPIO +#define HAL_GPIO_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_I2C +#define HAL_I2C_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_I2S +#define HAL_I2S_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IWDG +#define HAL_IWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LPTIM +#define HAL_LPTIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_LTDC +#define HAL_LTDC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_PWR +#define HAL_PWR_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_QSPI +#define HAL_QSPI_MODULE_ENABLED +#endif +#if defined RTE_DEVICE_HAL_RCC +#define HAL_RCC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RNG +#define HAL_RNG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_RTC +#define HAL_RTC_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SAI +#define HAL_SAI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SD +#define HAL_SD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SPDIFRX +#define HAL_SPDIFRX_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SPI +#define HAL_SPI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_TIM +#define HAL_TIM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_UART +#define HAL_UART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_USART +#define HAL_USART_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_IRDA +#define HAL_IRDA_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SMARTCARD +#define HAL_SMARTCARD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_WWDG +#define HAL_WWDG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_CORTEX +#define HAL_CORTEX_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_PCD +#define HAL_PCD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_HCD +#define HAL_HCD_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DFSDM +#define HAL_DFSDM_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_DSI +#define HAL_DSI_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_JPEG +#define HAL_JPEG_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_MDIOS +#define HAL_MDIOS_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_SMBUS +#define HAL_SMBUS_MODULE_ENABLED +#endif +#ifdef RTE_DEVICE_HAL_MMC +#define HAL_MMC_MODULE_ENABLED +#endif + + +/* ########################## HSE/HSI Values adaptation ##################### */ +/** + * @brief Adjust the value of External High Speed oscillator (HSE) used in your application. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSE is used as system clock source, directly or through the PLL). + */ +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSE_STARTUP_TIMEOUT) + #define HSE_STARTUP_TIMEOUT ((uint32_t)100U) /*!< Time out for HSE start up, in ms */ +#endif /* HSE_STARTUP_TIMEOUT */ + +/** + * @brief Internal High Speed oscillator (HSI) value. + * This value is used by the RCC HAL module to compute the system frequency + * (when HSI is used as system clock source, directly or through the PLL). + */ +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @brief Internal Low Speed oscillator (LSI) value. + */ +#if !defined (LSI_VALUE) + #define LSI_VALUE ((uint32_t)32000) /*!< LSI Typical Value in Hz*/ +#endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz + The real value may vary depending on the variations + in voltage and temperature. */ +/** + * @brief External Low Speed oscillator (LSE) value. + */ +#if !defined (LSE_VALUE) + #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */ +#endif /* LSE_VALUE */ +#if !defined (LSE_STARTUP_TIMEOUT) + #define LSE_STARTUP_TIMEOUT ((uint32_t)5000U) /*!< Time out for LSE start up, in ms */ +#endif /* LSE_STARTUP_TIMEOUT */ + +/** + * @brief External clock source for I2S peripheral + * This value is used by the I2S HAL module to compute the I2S clock source + * frequency, this source is inserted directly through I2S_CKIN pad. + */ +#if !defined (EXTERNAL_CLOCK_VALUE) + #define EXTERNAL_CLOCK_VALUE ((uint32_t)12288000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* EXTERNAL_CLOCK_VALUE */ + +/* Tip: To avoid modifying this file each time you need to use different HSE, + === you can define the HSE value in your toolchain compiler preprocessor. */ + +/* ########################### System Configuration ######################### */ +/** + * @brief This is the HAL system configuration section + */ +#define VDD_VALUE ((uint32_t)3300U) /*!< Value of VDD in mv */ +#define TICK_INT_PRIORITY ((uint32_t)0x0FU) /*!< tick interrupt priority */ +#define USE_RTOS 0U +#define PREFETCH_ENABLE 1U +#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ + +#define USE_HAL_ADC_REGISTER_CALLBACKS 0U /* ADC register callback disabled */ +#define USE_HAL_CAN_REGISTER_CALLBACKS 0U /* CAN register callback disabled */ +#define USE_HAL_CEC_REGISTER_CALLBACKS 0U /* CEC register callback disabled */ +#define USE_HAL_CRYP_REGISTER_CALLBACKS 0U /* CRYP register callback disabled */ +#define USE_HAL_DAC_REGISTER_CALLBACKS 0U /* DAC register callback disabled */ +#define USE_HAL_DCMI_REGISTER_CALLBACKS 0U /* DCMI register callback disabled */ +#define USE_HAL_DFSDM_REGISTER_CALLBACKS 0U /* DFSDM register callback disabled */ +#define USE_HAL_DMA2D_REGISTER_CALLBACKS 0U /* DMA2D register callback disabled */ +#define USE_HAL_DSI_REGISTER_CALLBACKS 0U /* DSI register callback disabled */ +#define USE_HAL_ETH_REGISTER_CALLBACKS 0U /* ETH register callback disabled */ +#define USE_HAL_HASH_REGISTER_CALLBACKS 0U /* HASH register callback disabled */ +#define USE_HAL_HCD_REGISTER_CALLBACKS 0U /* HCD register callback disabled */ +#define USE_HAL_I2C_REGISTER_CALLBACKS 0U /* I2C register callback disabled */ +#define USE_HAL_I2S_REGISTER_CALLBACKS 0U /* I2S register callback disabled */ +#define USE_HAL_IRDA_REGISTER_CALLBACKS 0U /* IRDA register callback disabled */ +#define USE_HAL_JPEG_REGISTER_CALLBACKS 0U /* JPEG register callback disabled */ +#define USE_HAL_LPTIM_REGISTER_CALLBACKS 0U /* LPTIM register callback disabled */ +#define USE_HAL_LTDC_REGISTER_CALLBACKS 0U /* LTDC register callback disabled */ +#define USE_HAL_MDIOS_REGISTER_CALLBACKS 0U /* MDIOS register callback disabled */ +#define USE_HAL_MMC_REGISTER_CALLBACKS 0U /* MMC register callback disabled */ +#define USE_HAL_NAND_REGISTER_CALLBACKS 0U /* NAND register callback disabled */ +#define USE_HAL_NOR_REGISTER_CALLBACKS 0U /* NOR register callback disabled */ +#define USE_HAL_PCD_REGISTER_CALLBACKS 0U /* PCD register callback disabled */ +#define USE_HAL_QSPI_REGISTER_CALLBACKS 0U /* QSPI register callback disabled */ +#define USE_HAL_RNG_REGISTER_CALLBACKS 0U /* RNG register callback disabled */ +#define USE_HAL_RTC_REGISTER_CALLBACKS 0U /* RTC register callback disabled */ +#define USE_HAL_SAI_REGISTER_CALLBACKS 0U /* SAI register callback disabled */ +#define USE_HAL_SD_REGISTER_CALLBACKS 0U /* SD register callback disabled */ +#define USE_HAL_SMARTCARD_REGISTER_CALLBACKS 0U /* SMARTCARD register callback disabled */ +#define USE_HAL_SDRAM_REGISTER_CALLBACKS 0U /* SDRAM register callback disabled */ +#define USE_HAL_SRAM_REGISTER_CALLBACKS 0U /* SRAM register callback disabled */ +#define USE_HAL_SPDIFRX_REGISTER_CALLBACKS 0U /* SPDIFRX register callback disabled */ +#define USE_HAL_SMBUS_REGISTER_CALLBACKS 0U /* SMBUS register callback disabled */ +#define USE_HAL_SPI_REGISTER_CALLBACKS 0U /* SPI register callback disabled */ +#define USE_HAL_TIM_REGISTER_CALLBACKS 0U /* TIM register callback disabled */ +#define USE_HAL_UART_REGISTER_CALLBACKS 0U /* UART register callback disabled */ +#define USE_HAL_USART_REGISTER_CALLBACKS 0U /* USART register callback disabled */ +#define USE_HAL_WWDG_REGISTER_CALLBACKS 0U /* WWDG register callback disabled */ + +/* ########################## Assert Selection ############################## */ +/** + * @brief Uncomment the line below to expanse the "assert_param" macro in the + * HAL drivers code + */ +/* #define USE_FULL_ASSERT 1 */ + +/* ################## Ethernet peripheral configuration ##################### */ + +/* Section 1 : Ethernet peripheral configuration */ + +/* MAC ADDRESS: MAC_ADDR0:MAC_ADDR1:MAC_ADDR2:MAC_ADDR3:MAC_ADDR4:MAC_ADDR5 */ +#define MAC_ADDR0 2U +#define MAC_ADDR1 0U +#define MAC_ADDR2 0U +#define MAC_ADDR3 0U +#define MAC_ADDR4 0U +#define MAC_ADDR5 0U + +/* Definition of the Ethernet driver buffers size and count */ +#define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for receive */ +#define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE /* buffer size for transmit */ +#define ETH_RXBUFNB ((uint32_t)4U) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_TXBUFNB ((uint32_t)4U) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* Section 2: PHY configuration section */ + +/* DP83848 PHY Address*/ +#define DP83848_PHY_ADDRESS 0x01U +/* PHY Reset delay these values are based on a 1 ms Systick interrupt*/ +#define PHY_RESET_DELAY ((uint32_t)0x000000FFU) +/* PHY Configuration delay */ +#define PHY_CONFIG_DELAY ((uint32_t)0x00000FFFU) + +#define PHY_READ_TO ((uint32_t)0x0000FFFFU) +#define PHY_WRITE_TO ((uint32_t)0x0000FFFFU) + +/* Section 3: Common PHY Registers */ + +#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ +#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ + +#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ +#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ +#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ + +#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ + +/* Section 4: Extended PHY Registers */ + +#define PHY_SR ((uint16_t)0x10U) /*!< PHY status register Offset */ +#define PHY_MICR ((uint16_t)0x11U) /*!< MII Interrupt Control Register */ +#define PHY_MISR ((uint16_t)0x12U) /*!< MII Interrupt Status and Misc. Control Register */ + +#define PHY_LINK_STATUS ((uint16_t)0x0001U) /*!< PHY Link mask */ +#define PHY_SPEED_STATUS ((uint16_t)0x0002U) /*!< PHY Speed mask */ +#define PHY_DUPLEX_STATUS ((uint16_t)0x0004U) /*!< PHY Duplex mask */ + +#define PHY_MICR_INT_EN ((uint16_t)0x0002U) /*!< PHY Enable interrupts */ +#define PHY_MICR_INT_OE ((uint16_t)0x0001U) /*!< PHY Enable output interrupt events */ + +#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020U) /*!< Enable Interrupt on change of link status */ +#define PHY_LINK_INTERRUPT ((uint16_t)0x2000U) /*!< PHY link status interrupt mask */ + +/* ################## SPI peripheral configuration ########################## */ + +/* CRC FEATURE: Use to activate CRC feature inside HAL SPI Driver +* Activated: CRC code is present inside driver +* Deactivated: CRC code cleaned from driver +*/ + +#define USE_SPI_CRC 1U + +/* Includes ------------------------------------------------------------------*/ +/** + * @brief Include module's header file + */ + +#ifdef HAL_RCC_MODULE_ENABLED + #include "stm32f7xx_hal_rcc.h" +#endif /* HAL_RCC_MODULE_ENABLED */ + +#ifdef HAL_EXTI_MODULE_ENABLED + #include "stm32f7xx_hal_exti.h" +#endif /* HAL_EXTI_MODULE_ENABLED */ + +#ifdef HAL_GPIO_MODULE_ENABLED + #include "stm32f7xx_hal_gpio.h" +#endif /* HAL_GPIO_MODULE_ENABLED */ + +#ifdef HAL_DMA_MODULE_ENABLED + #include "stm32f7xx_hal_dma.h" +#endif /* HAL_DMA_MODULE_ENABLED */ + +#ifdef HAL_CORTEX_MODULE_ENABLED + #include "stm32f7xx_hal_cortex.h" +#endif /* HAL_CORTEX_MODULE_ENABLED */ + +#ifdef HAL_ADC_MODULE_ENABLED + #include "stm32f7xx_hal_adc.h" +#endif /* HAL_ADC_MODULE_ENABLED */ + +#ifdef HAL_CAN_MODULE_ENABLED + #include "stm32f7xx_hal_can.h" +#endif /* HAL_CAN_MODULE_ENABLED */ + +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + +#ifdef HAL_CEC_MODULE_ENABLED + #include "stm32f7xx_hal_cec.h" +#endif /* HAL_CEC_MODULE_ENABLED */ + +#ifdef HAL_CRC_MODULE_ENABLED + #include "stm32f7xx_hal_crc.h" +#endif /* HAL_CRC_MODULE_ENABLED */ + +#ifdef HAL_CRYP_MODULE_ENABLED + #include "stm32f7xx_hal_cryp.h" +#endif /* HAL_CRYP_MODULE_ENABLED */ + +#ifdef HAL_DMA2D_MODULE_ENABLED + #include "stm32f7xx_hal_dma2d.h" +#endif /* HAL_DMA2D_MODULE_ENABLED */ + +#ifdef HAL_DAC_MODULE_ENABLED + #include "stm32f7xx_hal_dac.h" +#endif /* HAL_DAC_MODULE_ENABLED */ + +#ifdef HAL_DCMI_MODULE_ENABLED + #include "stm32f7xx_hal_dcmi.h" +#endif /* HAL_DCMI_MODULE_ENABLED */ + +#ifdef HAL_ETH_MODULE_ENABLED + #include "stm32f7xx_hal_eth.h" +#endif /* HAL_ETH_MODULE_ENABLED */ + +#ifdef HAL_FLASH_MODULE_ENABLED + #include "stm32f7xx_hal_flash.h" +#endif /* HAL_FLASH_MODULE_ENABLED */ + +#ifdef HAL_SRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sram.h" +#endif /* HAL_SRAM_MODULE_ENABLED */ + +#ifdef HAL_NOR_MODULE_ENABLED + #include "stm32f7xx_hal_nor.h" +#endif /* HAL_NOR_MODULE_ENABLED */ + +#ifdef HAL_NAND_MODULE_ENABLED + #include "stm32f7xx_hal_nand.h" +#endif /* HAL_NAND_MODULE_ENABLED */ + +#ifdef HAL_SDRAM_MODULE_ENABLED + #include "stm32f7xx_hal_sdram.h" +#endif /* HAL_SDRAM_MODULE_ENABLED */ + +#ifdef HAL_HASH_MODULE_ENABLED + #include "stm32f7xx_hal_hash.h" +#endif /* HAL_HASH_MODULE_ENABLED */ + +#ifdef HAL_I2C_MODULE_ENABLED + #include "stm32f7xx_hal_i2c.h" +#endif /* HAL_I2C_MODULE_ENABLED */ + +#ifdef HAL_I2S_MODULE_ENABLED + #include "stm32f7xx_hal_i2s.h" +#endif /* HAL_I2S_MODULE_ENABLED */ + +#ifdef HAL_IWDG_MODULE_ENABLED + #include "stm32f7xx_hal_iwdg.h" +#endif /* HAL_IWDG_MODULE_ENABLED */ + +#ifdef HAL_LPTIM_MODULE_ENABLED + #include "stm32f7xx_hal_lptim.h" +#endif /* HAL_LPTIM_MODULE_ENABLED */ + +#ifdef HAL_LTDC_MODULE_ENABLED + #include "stm32f7xx_hal_ltdc.h" +#endif /* HAL_LTDC_MODULE_ENABLED */ + +#ifdef HAL_PWR_MODULE_ENABLED + #include "stm32f7xx_hal_pwr.h" +#endif /* HAL_PWR_MODULE_ENABLED */ + +#ifdef HAL_QSPI_MODULE_ENABLED + #include "stm32f7xx_hal_qspi.h" +#endif /* HAL_QSPI_MODULE_ENABLED */ + +#ifdef HAL_RNG_MODULE_ENABLED + #include "stm32f7xx_hal_rng.h" +#endif /* HAL_RNG_MODULE_ENABLED */ + +#ifdef HAL_RTC_MODULE_ENABLED + #include "stm32f7xx_hal_rtc.h" +#endif /* HAL_RTC_MODULE_ENABLED */ + +#ifdef HAL_SAI_MODULE_ENABLED + #include "stm32f7xx_hal_sai.h" +#endif /* HAL_SAI_MODULE_ENABLED */ + +#ifdef HAL_SD_MODULE_ENABLED + #include "stm32f7xx_hal_sd.h" +#endif /* HAL_SD_MODULE_ENABLED */ + +#ifdef HAL_SPDIFRX_MODULE_ENABLED + #include "stm32f7xx_hal_spdifrx.h" +#endif /* HAL_SPDIFRX_MODULE_ENABLED */ + +#ifdef HAL_SPI_MODULE_ENABLED + #include "stm32f7xx_hal_spi.h" +#endif /* HAL_SPI_MODULE_ENABLED */ + +#ifdef HAL_TIM_MODULE_ENABLED + #include "stm32f7xx_hal_tim.h" +#endif /* HAL_TIM_MODULE_ENABLED */ + +#ifdef HAL_UART_MODULE_ENABLED + #include "stm32f7xx_hal_uart.h" +#endif /* HAL_UART_MODULE_ENABLED */ + +#ifdef HAL_USART_MODULE_ENABLED + #include "stm32f7xx_hal_usart.h" +#endif /* HAL_USART_MODULE_ENABLED */ + +#ifdef HAL_IRDA_MODULE_ENABLED + #include "stm32f7xx_hal_irda.h" +#endif /* HAL_IRDA_MODULE_ENABLED */ + +#ifdef HAL_SMARTCARD_MODULE_ENABLED + #include "stm32f7xx_hal_smartcard.h" +#endif /* HAL_SMARTCARD_MODULE_ENABLED */ + +#ifdef HAL_WWDG_MODULE_ENABLED + #include "stm32f7xx_hal_wwdg.h" +#endif /* HAL_WWDG_MODULE_ENABLED */ + +#ifdef HAL_PCD_MODULE_ENABLED + #include "stm32f7xx_hal_pcd.h" +#endif /* HAL_PCD_MODULE_ENABLED */ + +#ifdef HAL_HCD_MODULE_ENABLED + #include "stm32f7xx_hal_hcd.h" +#endif /* HAL_HCD_MODULE_ENABLED */ + +#ifdef HAL_DFSDM_MODULE_ENABLED + #include "stm32f7xx_hal_dfsdm.h" +#endif /* HAL_DFSDM_MODULE_ENABLED */ + +#ifdef HAL_DSI_MODULE_ENABLED + #include "stm32f7xx_hal_dsi.h" +#endif /* HAL_DSI_MODULE_ENABLED */ + +#ifdef HAL_JPEG_MODULE_ENABLED + #include "stm32f7xx_hal_jpeg.h" +#endif /* HAL_JPEG_MODULE_ENABLED */ + +#ifdef HAL_MDIOS_MODULE_ENABLED + #include "stm32f7xx_hal_mdios.h" +#endif /* HAL_MDIOS_MODULE_ENABLED */ + +#ifdef HAL_SMBUS_MODULE_ENABLED + #include "stm32f7xx_hal_smbus.h" +#endif /* HAL_SMBUS_MODULE_ENABLED */ + +#ifdef HAL_MMC_MODULE_ENABLED + #include "stm32f7xx_hal_mmc.h" +#endif /* HAL_MMC_MODULE_ENABLED */ + +/* Exported macro ------------------------------------------------------------*/ +#ifdef USE_FULL_ASSERT +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr: If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ + #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ + void assert_failed(uint8_t* file, uint32_t line); +#else + #define assert_param(expr) ((void)0U) +#endif /* USE_FULL_ASSERT */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __STM32F7xx_HAL_CONF_H */ + + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTE/Device/STM32F746NGHx/system_stm32f7xx.c b/RTE/Device/STM32F746NGHx/system_stm32f7xx.c new file mode 100644 index 0000000..cb4e566 --- /dev/null +++ b/RTE/Device/STM32F746NGHx/system_stm32f7xx.c @@ -0,0 +1,278 @@ +/** + ****************************************************************************** + * @file system_stm32f7xx.c + * @author MCD Application Team + * @brief CMSIS Cortex-M7 Device Peripheral Access Layer System Source File. + * + * This file provides two functions and one global variable to be called from + * user application: + * - SystemInit(): This function is called at startup just after reset and + * before branch to main program. This call is made inside + * the "startup_stm32f7xx.s" file. + * + * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used + * by the user application to setup the SysTick + * timer or configure other parameters. + * + * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must + * be called whenever the core clock is changed + * during program execution. + * + * + ****************************************************************************** + * @attention + * + *

© COPYRIGHT 2016 STMicroelectronics

+ * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + +/** @addtogroup CMSIS + * @{ + */ + +/** @addtogroup stm32f7xx_system + * @{ + */ + +/** @addtogroup STM32F7xx_System_Private_Includes + * @{ + */ + +#include "stm32f7xx.h" + +#if !defined (HSE_VALUE) + #define HSE_VALUE ((uint32_t)25000000) /*!< Default value of the External oscillator in Hz */ +#endif /* HSE_VALUE */ + +#if !defined (HSI_VALUE) + #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ +#endif /* HSI_VALUE */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_TypesDefinitions + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Defines + * @{ + */ + +/************************* Miscellaneous Configuration ************************/ + +/*!< Uncomment the following line if you need to relocate your vector Table in + Internal SRAM. */ +/* #define VECT_TAB_SRAM */ +#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. + This value must be a multiple of 0x200. */ +/******************************************************************************/ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Macros + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Variables + * @{ + */ + + /* This variable is updated in three ways: + 1) by calling CMSIS function SystemCoreClockUpdate() + 2) by calling HAL API function HAL_RCC_GetHCLKFreq() + 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency + Note: If you use this function to configure the system clock; then there + is no need to call the 2 first functions listed above, since SystemCoreClock + variable is updated automatically. + */ + uint32_t SystemCoreClock = 16000000; + const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; + const uint8_t APBPrescTable[8] = {0, 0, 0, 0, 1, 2, 3, 4}; + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_FunctionPrototypes + * @{ + */ + +/** + * @} + */ + +/** @addtogroup STM32F7xx_System_Private_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system + * Initialize the Embedded Flash Interface, the PLL and update the + * SystemFrequency variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + /* FPU settings ------------------------------------------------------------*/ + #if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ + #endif + /* Reset the RCC clock configuration to the default reset state ------------*/ + /* Set HSION bit */ + RCC->CR |= (uint32_t)0x00000001; + + /* Reset CFGR register */ + RCC->CFGR = 0x00000000; + + /* Reset HSEON, CSSON and PLLON bits */ + RCC->CR &= (uint32_t)0xFEF6FFFF; + + /* Reset PLLCFGR register */ + RCC->PLLCFGR = 0x24003010; + + /* Reset HSEBYP bit */ + RCC->CR &= (uint32_t)0xFFFBFFFF; + + /* Disable all interrupts */ + RCC->CIR = 0x00000000; + + /* Configure the Vector Table location add offset address ------------------*/ +#ifdef VECT_TAB_SRAM + SCB->VTOR = RAMDTCM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ +#else + SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ +#endif +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * The SystemCoreClock variable contains the core clock (HCLK), it can + * be used by the user application to setup the SysTick timer or configure + * other parameters. + * + * @note Each time the core clock (HCLK) changes, this function must be called + * to update SystemCoreClock variable value. Otherwise, any configuration + * based on this variable will be incorrect. + * + * @note - The system frequency computed by this function is not the real + * frequency in the chip. It is calculated based on the predefined + * constant and the selected clock source: + * + * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) + * + * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) + * + * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) + * or HSI_VALUE(*) multiplied/divided by the PLL factors. + * + * (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 16 MHz) but the real value may vary depending on the variations + * in voltage and temperature. + * + * (**) HSE_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value + * 25 MHz), user has to ensure that HSE_VALUE is same as the real + * frequency of the crystal used. Otherwise, this function may + * have wrong result. + * + * - The result of this function could be not correct when using fractional + * value for HSE crystal. + * + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2; + + /* Get SYSCLK source -------------------------------------------------------*/ + tmp = RCC->CFGR & RCC_CFGR_SWS; + + switch (tmp) + { + case 0x00: /* HSI used as system clock source */ + SystemCoreClock = HSI_VALUE; + break; + case 0x04: /* HSE used as system clock source */ + SystemCoreClock = HSE_VALUE; + break; + case 0x08: /* PLL used as system clock source */ + + /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N + SYSCLK = PLL_VCO / PLL_P + */ + pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22; + pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; + + if (pllsource != 0) + { + /* HSE used as PLL clock source */ + pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + else + { + /* HSI used as PLL clock source */ + pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6); + } + + pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2; + SystemCoreClock = pllvco/pllp; + break; + default: + SystemCoreClock = HSI_VALUE; + break; + } + /* Compute HCLK frequency --------------------------------------------------*/ + /* Get HCLK prescaler */ + tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; + /* HCLK frequency */ + SystemCoreClock >>= tmp; +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ diff --git a/RTE/Hesso_pack/ext_led.c b/RTE/Hesso_pack/ext_led.c new file mode 100644 index 0000000..e773038 --- /dev/null +++ b/RTE/Hesso_pack/ext_led.c @@ -0,0 +1,224 @@ + +#include "stm32f7xx_hal.h" +#include "ext_led.h" +#include + + +//------------------------------------------------------------------------------ +static const uint8_t cie1931[101] = +{ + 0, 0, 1, 1, 1, 1, 2, 2, 2, 3, + 3, 3, 4, 4, 4, 5, 5, 6, 6, 7, + 8, 8, 9, 10, 10, 11, 12, 13, 14, 15, + 16, 17, 18, 19, 20, 22, 23, 24, 26, 27, + 29, 30, 32, 34, 35, 37, 39, 41, 43, 45, + 47, 49, 51, 54, 56, 58, 61, 64, 66, 69, + 72, 75, 78, 81, 84, 87, 90, 93, 97, 100, + 104, 108, 111, 115, 119, 123, 127, 131, 136, 140, + 145, 149, 154, 159, 163, 168, 173, 179, 184, 189, + 195, 200, 206, 212, 217, 223, 230, 236, 242, 248, + 255, +}; + +#if LIGHTNESS_PWM_STEP != 100 +#error this cie1931 array supports only 100 steps, feel free to implement your own +#endif + +//------------------------------------------------------------------------------ +uint8_t lightness_to_pwm(uint8_t percentage) +{ + if(percentage > (LIGHTNESS_PWM_STEP-1)) + percentage = (LIGHTNESS_PWM_STEP-1); + + return cie1931[percentage]; +} + + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t Ext_LED_Init(void) { + GPIO_InitTypeDef GPIO_InitStruct; + //---------------------------------------------------------------------------- + // Configure GPIO pin: PA15 (LED0) + __HAL_RCC_GPIOA_CLK_ENABLE(); // enable GPIO timer + __HAL_RCC_TIM2_CLK_ENABLE(); // enable timer 2 clock + GPIO_InitStruct.Pin = GPIO_PIN_15; // used pin is PA15 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; // alternate function use + GPIO_InitStruct.Pull = GPIO_NOPULL; // no pullup + GPIO_InitStruct.Alternate = GPIO_AF1_TIM2;// timer 2 is used + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; // speed is fast + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + TIM2->CCER = TIM_CCER_CC1E; // compare for PWM usage + TIM2->PSC = 16; // timer prescaler + TIM2->ARR = 255; // max count value + TIM2->CCR1 = lightness_to_pwm(0); // duty cycle + TIM2->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; + TIM2->EGR |= TIM_EGR_UG; // update register now + TIM2->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN; // start the timer + //---------------------------------------------------------------------------- + // Configure GPIO pin: PH6 (LED1) + __HAL_RCC_GPIOH_CLK_ENABLE(); // enable GPIO timer + __HAL_RCC_TIM12_CLK_ENABLE(); // enable timer 12 clock + GPIO_InitStruct.Pin = GPIO_PIN_6; // used pin is PH6 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; // alternate function use + GPIO_InitStruct.Pull = GPIO_NOPULL; // no pullup + GPIO_InitStruct.Alternate = GPIO_AF9_TIM12;// timer 12 is used + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; // speed is fast + HAL_GPIO_Init(GPIOH, &GPIO_InitStruct); + + TIM12->CCER = TIM_CCER_CC1E; // compare for PWM usage + TIM12->PSC = 16; // timer prescaler + TIM12->ARR = 255; // max count value + TIM12->CCR1 = lightness_to_pwm(0); // duty cycle + TIM12->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; + TIM12->EGR |= TIM_EGR_UG; // update register now + TIM12->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN; // start the timer + //---------------------------------------------------------------------------- + // Configure GPIO pin: PA8 (LED2) + __HAL_RCC_GPIOA_CLK_ENABLE(); // enable GPIO timer + __HAL_RCC_TIM1_CLK_ENABLE(); // enable timer 1 clock + + GPIO_InitStruct.Pin = GPIO_PIN_8; // used pin is PA8 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; // alternate function use + GPIO_InitStruct.Pull = GPIO_NOPULL; // no pullup + GPIO_InitStruct.Alternate = GPIO_AF1_TIM1;// timer 5 is used + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; // speed is fast + HAL_GPIO_Init(GPIOA, &GPIO_InitStruct); + + TIM1->CCER = TIM_CCER_CC1E; // compare for PWM usage + TIM1->PSC = 16; // timer prescaler + TIM1->ARR = 255; // max count value + TIM1->CCR1 = lightness_to_pwm(0); // duty cycle + TIM1->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; + TIM1->EGR |= TIM_EGR_UG; // update register now + TIM1->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN; // start the timer + TIM1->BDTR = TIM_BDTR_MOE; // master output enable + //---------------------------------------------------------------------------- + // Configure GPIO pin: PB4 (LED3) + __HAL_RCC_GPIOB_CLK_ENABLE(); // enable GPIO timer + __HAL_RCC_TIM3_CLK_ENABLE(); // enable timer 3 clock + GPIO_InitStruct.Pin = GPIO_PIN_4; // used pin is PB4 + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; // alternate function use + GPIO_InitStruct.Pull = GPIO_NOPULL; // no pullup + GPIO_InitStruct.Alternate = GPIO_AF2_TIM3;// timer 3 is used + GPIO_InitStruct.Speed = GPIO_SPEED_FAST; // speed is fast + HAL_GPIO_Init(GPIOB, &GPIO_InitStruct); + + TIM3->CCER = TIM_CCER_CC1E; // compare for PWM usage + TIM3->PSC = 16; // timer prescaler + TIM3->ARR = 255; // max count value + TIM3->CCR1 = lightness_to_pwm(0); // duty cycle + TIM3->CCMR1 = TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1PE; + TIM3->EGR |= TIM_EGR_UG; // update register now + TIM3->CR1 = TIM_CR1_ARPE | TIM_CR1_CEN; // start the timer + return 0; +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t Ext_LED_On (uint32_t num) { + + if((num & 1) != 0) + { + TIM2->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + if((num & 2) != 0) + { + TIM12->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + if((num & 4) != 0) + { + TIM1->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + if((num & 8) != 0) + { + TIM3->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + return 0; +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t Ext_LED_Off (uint32_t num) { + + if((num & 1) != 0) + { + TIM2->CCR1 = lightness_to_pwm(0); + } + if((num & 2) != 0) + { + TIM12->CCR1 = lightness_to_pwm(0); + } + if((num & 4) != 0) + { + TIM1->CCR1 = lightness_to_pwm(0); + } + if((num & 8) != 0) + { + TIM3->CCR1 = lightness_to_pwm(0); + } + return 0; +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t Ext_LED_PWM (uint32_t num, uint32_t duty) { + + if((num & 1) != 0) + { + TIM2->CCR1 = lightness_to_pwm(duty); + } + if((num & 2) != 0) + { + TIM12->CCR1 = lightness_to_pwm(duty); + } + if((num & 4) != 0) + { + TIM1->CCR1 = lightness_to_pwm(duty); + } + if((num & 8) != 0) + { + TIM3->CCR1 = lightness_to_pwm(duty); + } + return 0; +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +int32_t Ext_LEDs(uint32_t num) { + + if((num & 1) != 0) + { + TIM2->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + else + { + TIM2->CCR1 = lightness_to_pwm(0); + } + if((num & 2) != 0) + { + TIM12->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + else + { + TIM12->CCR1 = lightness_to_pwm(0); + } + if((num & 4) != 0) + { + TIM1->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + else + { + TIM1->CCR1 = lightness_to_pwm(0); + } + if((num & 8) != 0) + { + TIM3->CCR1 = lightness_to_pwm(LIGHTNESS_PWM_STEP); + } + else + { + TIM3->CCR1 = lightness_to_pwm(0); + } + return 0; +} diff --git a/RTE/Hesso_pack/ext_led.h b/RTE/Hesso_pack/ext_led.h new file mode 100644 index 0000000..28b8ed9 --- /dev/null +++ b/RTE/Hesso_pack/ext_led.h @@ -0,0 +1,51 @@ +/************************************************************************//** + * \file ext_led.h + * \brief Function to use the extension LEDs + * \author pascal (dot) sartoretti (at) hevs (dot) ch + ***************************************************************************/ + + +#ifndef __EXT_LED_H +#define __EXT_LED_H + +#include + +#define LIGHTNESS_PWM_STEP 100 + + +/************************************************************************//** + * \brief Inits the external Leds usage. + * \return Always #0 + ***************************************************************************/ +extern int32_t Ext_LED_Init (void); + +/************************************************************************//** + * \brief Turn on one led. + * \param num The led to turn on (1,2,4,8) + * \return Always 0 + ***************************************************************************/ +extern int32_t Ext_LED_On (uint32_t num); + +/************************************************************************//** + * \brief Turn off one led. + * \param num The led to turn off (1,2,4,8) + * \return Always 0 + ***************************************************************************/ +extern int32_t Ext_LED_Off (uint32_t num); + +/************************************************************************//** + * \brief Set a power on a led. + * \param num The led to turn set the power (1,2,4,8) + * \param duty The power of the led (0 to 255) + * \return Always 0 + ***************************************************************************/ +extern int32_t Ext_LED_PWM (uint32_t num, uint32_t duty); + +/************************************************************************//** + * \brief Set the state on all leds. + * \param val The binary state of the four leds (example 0b1101). + * \return Always 0 + ***************************************************************************/ +extern int32_t Ext_LEDs(uint32_t val); + +#endif /* __BOARD_LED_H */ diff --git a/RTE/Hesso_pack/ext_uart.c b/RTE/Hesso_pack/ext_uart.c new file mode 100644 index 0000000..adefcf8 --- /dev/null +++ b/RTE/Hesso_pack/ext_uart.c @@ -0,0 +1,57 @@ + +#include "stm32f7xx_hal.h" +#include "ext_uart.h" + +UART_HandleTypeDef ext_uart; // extension uart handler +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +void HAL_UART_MspInit(UART_HandleTypeDef* huart) +{ + + GPIO_InitTypeDef GPIO_InitStruct; + if(huart->Instance==USART6) + { + __HAL_RCC_GPIOC_CLK_ENABLE(); + __HAL_RCC_USART6_CLK_ENABLE(); + + /**USART6 GPIO Configuration + PC7 ------> USART6_RX + PC6 ------> USART6_TX + */ + GPIO_InitStruct.Pin = GPIO_PIN_7|GPIO_PIN_6; + GPIO_InitStruct.Mode = GPIO_MODE_AF_PP; + GPIO_InitStruct.Pull = GPIO_PULLUP; + GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH; + GPIO_InitStruct.Alternate = GPIO_AF8_USART6; + HAL_GPIO_Init(GPIOC, &GPIO_InitStruct); + } +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +void Ext_UART_Init(uint32_t speed) +{ + ext_uart.Instance = USART6; + ext_uart.Init.BaudRate = speed; + ext_uart.Init.WordLength = UART_WORDLENGTH_8B; + ext_uart.Init.StopBits = UART_STOPBITS_1; + ext_uart.Init.Parity = UART_PARITY_NONE; + ext_uart.Init.Mode = UART_MODE_TX_RX; + ext_uart.Init.HwFlowCtl = UART_HWCONTROL_NONE; + ext_uart.Init.OverSampling = UART_OVERSAMPLING_16; + ext_uart.Init.OneBitSampling = UART_ONE_BIT_SAMPLE_DISABLE; + ext_uart.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_NO_INIT; + HAL_UART_Init(&ext_uart); + /* USART6 interrupt Init */ + HAL_NVIC_SetPriority(USART6_IRQn, 0, 0); + HAL_NVIC_EnableIRQ(USART6_IRQn); +} + +//------------------------------------------------------------------------------ +//------------------------------------------------------------------------------ +void USART6_IRQHandler(void) +{ + HAL_UART_IRQHandler(&ext_uart); +} + + diff --git a/RTE/Hesso_pack/ext_uart.h b/RTE/Hesso_pack/ext_uart.h new file mode 100644 index 0000000..a892f70 --- /dev/null +++ b/RTE/Hesso_pack/ext_uart.h @@ -0,0 +1,44 @@ +/************************************************************************//** + * \file ext_uart.h + * \brief Function to use the extension uart + * \author pascal (dot) sartoretti (at) hevs (dot) ch + ***************************************************************************/ + + +#ifndef __EXT_UART_H +#define __EXT_UART_H + +#include +#include "stm32f7xx_hal.h" + +extern UART_HandleTypeDef ext_uart; // extension uart handle + +/************************************************************************//** + * \brief Inits the extension uart + * \param speed This si the uart speed selected for example 115200. + * The extension uart could be use with or without interrupts. + * + * Without interrupts: + * ------------------- + * To send something on the uart, you have to use HAL_UART_Transmit function + * as the example below. + * error = HAL_UART_Transmit(&ext_uart, msg, sizeof(msg),50); + * To receive you have to use HAL_UART_Receive as example below. + * error = HAL_UART_Receive(&ext_uart, msg, sizeof(msg),HAL_MAX_DELAY); + * The HAL_MAX_DELAY waits until receive is finished. + * + * With interrupts: + * ---------------- + * The functions below have to be used: + * HAL_UART_Transmit_IT(&ext_uart," Welcome\n\r", 10); + * HAL_UART_Receive_IT(&ext_uart,data,8); + * + * The callback functions above could be implemented for usage on interrupt + * mode when the full size is transmitted (or received). + * void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) + * void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) + * + ***************************************************************************/ +extern void Ext_UART_Init(uint32_t speed); + +#endif /* __BOARD_LED_H */ diff --git a/RTE/_Target_1/RTE_Components.h b/RTE/_Target_1/RTE_Components.h new file mode 100644 index 0000000..c793458 --- /dev/null +++ b/RTE/_Target_1/RTE_Components.h @@ -0,0 +1,49 @@ + +/* + * Auto generated Run-Time-Environment Configuration File + * *** Do not modify ! *** + * + * Project: 'lab04-queue' + * Target: 'Target 1' + */ + +#ifndef RTE_COMPONENTS_H +#define RTE_COMPONENTS_H + + +/* + * Define the Device Header File: + */ +#define CMSIS_device_header "stm32f7xx.h" + +/* ARM::CMSIS:RTOS2:Keil RTX5:Source:5.5.4 */ +#define RTE_CMSIS_RTOS2 /* CMSIS-RTOS2 */ + #define RTE_CMSIS_RTOS2_RTX5 /* CMSIS-RTOS2 Keil RTX5 */ + #define RTE_CMSIS_RTOS2_RTX5_SOURCE /* CMSIS-RTOS2 Keil RTX5 Source */ +/* Keil.ARM Compiler::Compiler:Event Recorder:DAP:1.5.1 */ +#define RTE_Compiler_EventRecorder + #define RTE_Compiler_EventRecorder_DAP +/* Keil.ARM Compiler::Compiler:I/O:STDOUT:ITM:1.2.0 */ +#define RTE_Compiler_IO_STDOUT /* Compiler I/O: STDOUT */ + #define RTE_Compiler_IO_STDOUT_ITM /* Compiler I/O: STDOUT ITM */ +/* Keil::Device:STM32Cube Framework:Classic:1.2.7 */ +#define RTE_DEVICE_FRAMEWORK_CLASSIC +/* Keil::Device:STM32Cube HAL:Common:1.2.7 */ +#define RTE_DEVICE_HAL_COMMON +/* Keil::Device:STM32Cube HAL:Cortex:1.2.7 */ +#define RTE_DEVICE_HAL_CORTEX +/* Keil::Device:STM32Cube HAL:DMA:1.2.7 */ +#define RTE_DEVICE_HAL_DMA +/* Keil::Device:STM32Cube HAL:GPIO:1.2.7 */ +#define RTE_DEVICE_HAL_GPIO +/* Keil::Device:STM32Cube HAL:PWR:1.2.7 */ +#define RTE_DEVICE_HAL_PWR +/* Keil::Device:STM32Cube HAL:RCC:1.2.7 */ +#define RTE_DEVICE_HAL_RCC +/* Keil::Device:STM32Cube HAL:UART:1.2.7 */ +#define RTE_DEVICE_HAL_UART +/* Keil::Device:Startup:1.2.4 */ +#define RTE_DEVICE_STARTUP_STM32F7XX /* Device Startup for STM32F7 */ + + +#endif /* RTE_COMPONENTS_H */ diff --git a/lab04-queue.uvprojx b/lab04-queue.uvprojx new file mode 100644 index 0000000..82caec7 --- /dev/null +++ b/lab04-queue.uvprojx @@ -0,0 +1,608 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + Target 1 + 0x4 + ARM-ADS + 6160000::V6.16::ARMCLANG + 1 + + + STM32F746NGHx + STMicroelectronics + Keil.STM32F7xx_DFP.2.12.0 + http://www.keil.com/pack/ + IRAM(0x20010000,0x40000) IRAM2(0x20000000,0x10000) IROM(0x08000000,0x100000) IROM2(0x00200000,0x100000) CPUTYPE("Cortex-M7") FPU3(SFPU) CLOCK(12000000) ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD20010000 -FC1000 -FN2 -FF0STM32F7x_1024 -FS08000000 -FL0100000 -FF1STM32F7xTCM_1024 -FS1200000 -FL1100000 -FP0($$Device:STM32F746NGHx$CMSIS\Flash\STM32F7x_1024.FLM) -FP1($$Device:STM32F746NGHx$CMSIS\Flash\STM32F7xTCM_1024.FLM)) + 0 + $$Device:STM32F746NGHx$Drivers\CMSIS\Device\ST\STM32F7xx\Include\stm32f7xx.h + + + + + + + + + + $$Device:STM32F746NGHx$CMSIS\SVD\STM32F7x6_v1r1.svd + 0 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\Objects\ + lab01-rtx5 + 1 + 0 + 0 + 1 + 1 + .\Listings\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -REMAP -MPU + DCM.DLL + -pCM7 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM7 + + + + 1 + 0 + 0 + 0 + 16 + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M7" + + 1 + 0 + 0 + 1 + 1 + 0 + 0 + 2 + 0 + 0 + 1 + 1 + 8 + 0 + 0 + 0 + 0 + 3 + 4 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 1 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 1 + 0x8000000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x8000000 + 0x100000 + + + 1 + 0x200000 + 0x100000 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x20010000 + 0x40000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 2 + 0 + 0 + 0 + 0 + 0 + 3 + 3 + 1 + 1 + 0 + 0 + 0 + + + + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + + + + + + + + + 1 + 0 + 0 + 0 + 1 + 0 + 0x08000000 + 0x20010000 + + + + + + + + + + + + + Source Group 1 + + + main.c + 1 + .\main.c + + + + + ::CMSIS + + + ::Compiler + + + ::Device + + + ::Hesso pack + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + RTE\CMSIS\RTX_Config.c + + + + + + + + RTE\CMSIS\RTX_Config.h + + + + + + + + RTE\Compiler\EventRecorderConf.h + + + + + + + + RTE\Device\STM32F746NGHx\RTE_Device.h + + + + + + + + RTE\Device\STM32F746NGHx\startup_stm32f746xx.s + + + + + + + + RTE\Device\STM32F746NGHx\stm32f7xx_hal_conf.h + + + + + + + + RTE\Device\STM32F746NGHx\system_stm32f7xx.c + + + + + + + + RTE\Hesso_pack\ext_led.c + + + + + + + + RTE\Hesso_pack\ext_led.h + + + + + + + + RTE\Hesso_pack\ext_uart.c + + + + + + + + RTE\Hesso_pack\ext_uart.h + + + + + + + + + + diff --git a/main.c b/main.c new file mode 100644 index 0000000..05dbf50 --- /dev/null +++ b/main.c @@ -0,0 +1,135 @@ +/*---------------------------------------------------------------------------- + * CMSIS-RTOS 'main' function template + *---------------------------------------------------------------------------*/ + #include "stm32f7xx_hal.h" +#include "RTE_Components.h" +#include CMSIS_device_header +#include "cmsis_os2.h" +#include "ext_led.h" +#include "ext_uart.h" +#include "ext_buttons.h" +#include "ext_keyboard.h" +#include "string.h" +#include +#include + +#ifdef RTE_Compiler_EventRecorder +#include "EventRecorder.h" +#endif + +osThreadId_t thread1,thread2; +osMessageQueueId_t msgQueue; + + const osThreadAttr_t thread1_attr = { + .stack_size = 1024, // Create the thread stack size + .priority = osPriorityNormal, //Set initial thread priority to high + .name = "Producer", +}; + const osThreadAttr_t thread2_attr = { + .stack_size = 1024, // Create the thread stack size + .priority = osPriorityNormal, //Set initial thread priority to high + .name = "Consumer", +}; + +const osMessageQueueAttr_t msgQueue_attr = { + .name = "MsgQueue", +}; + + +//------------------------------------------------------------------------------ +// Setup system clock to 216MHz +//------------------------------------------------------------------------------ +void SystemClock_Config (void) { + RCC_ClkInitTypeDef RCC_ClkInitStruct; + RCC_OscInitTypeDef RCC_OscInitStruct; + + /* Enable HSE Oscillator and activate PLL with HSE as source */ + RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE; + RCC_OscInitStruct.HSEState = RCC_HSE_ON; + RCC_OscInitStruct.HSIState = RCC_HSI_OFF; + RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; + RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; + RCC_OscInitStruct.PLL.PLLM = 25; + RCC_OscInitStruct.PLL.PLLN = 432; + RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; + RCC_OscInitStruct.PLL.PLLQ = 9; + HAL_RCC_OscConfig(&RCC_OscInitStruct); + + /* Activate the OverDrive to reach the 216 MHz Frequency */ + HAL_PWREx_EnableOverDrive(); + + /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ + RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); + RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; + RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; + RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV4; + RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV2; + HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_7); +} + + + +/*---------------------------------------------------------------------------- + * Thread Producer + *---------------------------------------------------------------------------*/ +__NO_RETURN static void Thread_Producer (void *argument) { + osMessageQueueId_t* queue = (osMessageQueueId_t*)argument; + uint32_t counter = 0; + + for(;;) { + osStatus_t statusQueue = osMessageQueuePut(*queue, &counter, 1, 0); + if(statusQueue != osOK) { + // TODO generate error + } + counter++; + osDelay(100); + } + +} + +/*---------------------------------------------------------------------------- + * Thread Consumer + *---------------------------------------------------------------------------*/ +__NO_RETURN static void Thread_Consumer (void *argument) { + osMessageQueueId_t* queue = (osMessageQueueId_t*)argument; + uint8_t counter = 1; + + for(;;) { + uint32_t msg; + osStatus_t statusQueue; + + do { + statusQueue = osMessageQueueGet(*queue, &msg, NULL, 0); + printf("Value is %d\r\n", msg); + } while(statusQueue != osErrorResource); + if(++counter > 10) counter = 1; + osDelay(counter*100); + } +} + + +int main (void) { + + // System Initialization + SystemClock_Config(); + SystemCoreClockUpdate(); +#ifdef RTE_Compiler_EventRecorder + // Initialize and start Event Recorder +// Ext_UART_Init(9600); + EventRecorderInitialize(EventRecordAll, 1U); +#endif + + osKernelInitialize(); // Initialize CMSIS-RTOS + msgQueue = osMessageQueueNew(8, 4, &msgQueue_attr); + thread1 = osThreadNew(Thread_Producer, &msgQueue, &thread1_attr); + thread2 = osThreadNew(Thread_Consumer, &msgQueue, &thread2_attr); + + //---------------------------------------------------------------------------------------------- + // get names are placed for TraceAlyzer visualisation + //---------------------------------------------------------------------------------------------- + osThreadGetName(thread1); + osThreadGetName(thread2); + osMessageQueueGetName(msgQueue); + osKernelStart(); // Start thread execution + for (;;) {} +}