23 lines
465 B
VHDL
23 lines
465 B
VHDL
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architecture studentVersion of ex_24_1_1 is
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signal counter : unsigned(counterBitNb-1 downto 0);
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begin
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process(clock, reset) begin
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if reset = '1' then
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counter <= (others => '0');
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elsif rising_edge(clock) then
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if en = '1' then
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if up_down = '1' then
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counter <= counter + 1;
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else
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counter <= counter -1;
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end if;
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end if;
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end if;
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end process;
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position <= counter;
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end studentVersion;
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