102 lines
2.3 KiB
Plaintext
102 lines
2.3 KiB
Plaintext
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--
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-- VHDL Architecture VHD_test.tb_19_1_4.struct
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 12:59:54 03/27/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY VHD;
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ARCHITECTURE struct OF tb_19_1_4 IS
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-- Architecture declarations
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constant positionBitNb : positive := 8;
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constant clockFrequency : real := 100.0E6;
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constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
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signal sClock : std_uLogic := '1';
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signal position_int : integer := 0;
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-- Internal signal declarations
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SIGNAL A : std_ulogic;
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SIGNAL B : std_ulogic;
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SIGNAL clock : std_ulogic;
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SIGNAL dir : std_ulogic;
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SIGNAL en : std_ulogic;
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SIGNAL reset : std_ulogic;
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-- Component Declarations
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COMPONENT ex_19_1_4
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PORT (
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A : IN std_ulogic ;
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B : IN std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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en : OUT std_ulogic ;
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dir : OUT std_ulogic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : ex_19_1_4 USE ENTITY VHD.ex_19_1_4;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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reset <= '1', '0' after 2*clockPeriod;
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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process
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constant stepDelay: time := 1 us;
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begin
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wait for stepDelay;
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for index in 0 to 10 loop
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position_int <= position_int + 1;
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wait for stepDelay;
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end loop;
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for index in 10 downto 0 loop
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position_int <= position_int - 1;
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wait for stepDelay;
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end loop;
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wait;
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end process;
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process(position_int)
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begin
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case to_integer(to_unsigned(position_int, 2)) is
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when 0 => A <= '0'; B <= '0';
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when 1 => A <= '1'; B <= '0';
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when 2 => A <= '1'; B <= '1';
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when 3 => A <= '0'; B <= '1';
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when others => null;
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end case;
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end process;
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-- Instance port mappings.
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I_dut : ex_19_1_4
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PORT MAP (
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A => A,
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B => B,
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clock => clock,
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reset => reset,
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en => en,
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dir => dir
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);
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END struct;
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