1
0
This repository has been archived on 2024-10-30. You can view files and clone it, but cannot push or open issues or pull requests.
SEm-ExamMidterm2024/Prefs/hds_user/v2005.1/templates/verilog_include/verilog_include.v

15 lines
367 B
Coq
Raw Normal View History

2024-03-22 12:16:48 +00:00
FILE_NAMING_RULE: include_filename.v
DESCRIPTION_START
This is the default template used for the creation of Verilog Include files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Include file %(library)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//