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SEm-ExamMidterm2024/Prefs/hds_user/v2019.2/templates/verilog_module/module_migrated.v

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2024-03-22 12:16:48 +00:00
FILE_NAMING_RULE: %(module_name).v
DESCRIPTION_START
Template for the creation of Verilog Module files.
This template was migrated from header preferences created in a
previous version of HDL Designer.
DESCRIPTION_END
//
//
// Module %(library).%(unit).%(view)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// Generated by Mentor Graphics' HDL Designer(TM) %(version)
//
//
%(moduleBody)
//
// ### Please start your Verilog code here ###
endmodule