SEm-ExamMidterm2024/VHD/hdl/ex_24_1_3_studentVersion.vhd

architecture studentVersion of ex_24_1_3 is

  signal counter : unsigned(timerBitNb-1 downto 0);

begin

  process(reset, clock) begin
    if reset = '1' then 
      counter <= (others => '0');
    elsif rising_edge(clock) then 
      if testMode = '0' then
        counter <= counter - 1;
      else
        counter <= counter - 2**(timerBitNb - testModeBitNb);
      end if;
    end if;
  end process;

  process(counter)
  begin
    if counter = 0 then
      pwmEn <= '1';
    else
      pwmEn <= '0';
    end if;
  end process;

end studentVersion;