97 lines
2.3 KiB
VHDL
97 lines
2.3 KiB
VHDL
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--
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-- VHDL Architecture VHD_test.tb_24_1_1.struct
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--
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-- Created:
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-- by - remy.borgeat.UNKNOWN (WE10993)
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-- at - 15:02:54 20.03.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY VHD;
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ARCHITECTURE struct OF tb_24_1_1 IS
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-- Architecture declarations
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constant positionBitNb : positive := 8;
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constant clockFrequency : real := 100.0E6;
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constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
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signal sClock : std_uLogic := '1';
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signal position_int : integer := 0;
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-- Internal signal declarations
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SIGNAL clock : std_ulogic;
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SIGNAL en : std_ulogic;
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SIGNAL position : unsigned(positionBitNb-1 DOWNTO 0);
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SIGNAL reset : std_ulogic;
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SIGNAL up_down : std_ulogic;
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-- Component Declarations
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COMPONENT ex_24_1_1
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GENERIC (
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counterBitNb : positive := 8
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);
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PORT (
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en : IN std_ulogic ;
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position : OUT unsigned (counterBitNb-1 DOWNTO 0);
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up_down : IN std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : ex_24_1_1 USE ENTITY VHD.ex_24_1_1;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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reset <= '1', '0' after 2*clockPeriod;
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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process
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constant stepDelay: time := 1 us;
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begin
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en <= '0';
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up_down <= '1';
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wait for stepDelay;
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for index in 0 to 10 loop
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en <= '1', '0' after clockPeriod;
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position_int <= position_int + 1;
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wait for stepDelay;
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end loop;
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up_down <= '0';
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for index in 10 downto 0 loop
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en <= '1', '0' after clockPeriod;
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position_int <= position_int - 1;
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wait for stepDelay;
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end loop;
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wait;
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end process;
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-- Instance port mappings.
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I_dut : ex_24_1_1
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GENERIC MAP (
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counterBitNb => positionBitNb
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)
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PORT MAP (
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en => en,
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position => position,
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up_down => up_down,
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clock => clock,
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reset => reset
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);
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END struct;
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