SEm-ExamMidterm2024/VHD_test/hdl/tb_24_1_2_struct.vhd

--
-- VHDL Architecture VHD_test.tb_24_1_2.struct
--
-- Created:
--          by - remy.borgeat.UNKNOWN (WE10993)
--          at - 15:01:25 20.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY VHD;

ARCHITECTURE struct OF tb_24_1_2 IS

   -- Architecture declarations
   constant pwmFrequency : real := 1.0E6;
   constant pwmPeriod : time := (1.0/pwmFrequency) * 1 sec;
   signal sPwm :  std_uLogic := '1';

   -- Internal signal declarations
   SIGNAL motorOn    : std_ulogic;
   SIGNAL pwm        : std_ulogic;
   SIGNAL right_left : std_ulogic;
   SIGNAL side1      : std_ulogic;
   SIGNAL side2      : std_ulogic;


   -- Component Declarations
   COMPONENT ex_24_1_2
   PORT (
      motorOn    : IN     std_ulogic ;
      side1      : OUT    std_ulogic ;
      right_left : IN     std_ulogic ;
      pwm        : IN     std_ulogic ;
      side2      : OUT    std_ulogic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ex_24_1_2 USE ENTITY VHD.ex_24_1_2;
   -- pragma synthesis_on


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   sPwm <= not sPwm after pwmPeriod/2;
   pwm <= sPwm;
   
   process
     constant testDelay: time := 10 us;
   begin
     motorOn <= '0';
     right_left <= '1';
     wait for testDelay;
   
     motorOn <= '1';
     wait for testDelay;
   
     right_left <= '0';
     wait for testDelay;
   
     motorOn <= '0';
     wait for testDelay;
   
     wait;
   end process;
   


   -- Instance port mappings.
   I_dut : ex_24_1_2
      PORT MAP (
         motorOn    => motorOn,
         side1      => side1,
         right_left => right_left,
         pwm        => pwm,
         side2      => side2
      );

END struct;