SEm-ExamMidterm2024/VHD_test/hdl/tb_24_1_3_struct.vhg

--
-- VHDL Architecture VHD_test.tb_19_1_3.struct
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 12:43:24 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY VHD;

ARCHITECTURE struct OF tb_19_1_3 IS

   -- Architecture declarations
   constant positionBitNb : positive := 8;
   
   constant clockFrequency : real := 100.0E6;
   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
   signal sClock :  std_uLogic := '1';
   
   signal position_int : integer := 0;

   -- Internal signal declarations
   SIGNAL clock    : std_ulogic;
   SIGNAL pwmEn    : std_ulogic;
   SIGNAL reset    : std_ulogic;
   SIGNAL testMode : std_ulogic;


   -- Component Declarations
   COMPONENT ex_19_1_3
   GENERIC (
      timerBitNb    : positive := 8;
      testModeBitNb : positive := 1
   );
   PORT (
      testMode : IN     std_ulogic ;
      clock    : IN     std_ulogic ;
      reset    : IN     std_ulogic ;
      pwmEn    : OUT    std_ulogic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ex_19_1_3 USE ENTITY VHD.ex_19_1_3;
   -- pragma synthesis_on


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   reset <= '1', '0' after 2*clockPeriod;
   sClock <= not sClock after clockPeriod/2;
   clock <= transport sClock after clockPeriod*9/10;
   
   testMode <= '1', '0' after 100*clockPeriod;


   -- Instance port mappings.
   I_dut : ex_19_1_3
      GENERIC MAP (
         timerBitNb    => 8,
         testModeBitNb => 1
      )
      PORT MAP (
         testMode => testMode,
         clock    => clock,
         reset    => reset,
         pwmEn    => pwmEn
      );

END struct;