SEm-ExamMidterm2024/VHD_test/hdl/tb_24_1_5_struct.vhg

--
-- VHDL Architecture VHD_test.tb_19_1_5.struct
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 13:50:24 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY VHD;

ARCHITECTURE struct OF tb_19_1_5 IS

   -- Architecture declarations
   constant speedBitNb : positive := 8;
   
   constant clockFrequency : real := 100.0E6;
   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
   signal sClock :  std_uLogic := '1';
   
   signal position_int : integer := 0;

   -- Internal signal declarations
   SIGNAL clock : std_ulogic;
   SIGNAL done  : std_ulogic;
   SIGNAL reset : std_ulogic;
   SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0);
   SIGNAL start : std_ulogic;


   -- Component Declarations
   COMPONENT ex_19_1_5
   GENERIC (
      speedBitNb : positive
   );
   PORT (
      start : IN     std_ulogic ;
      clock : IN     std_ulogic ;
      reset : IN     std_ulogic ;
      done  : OUT    std_ulogic ;
      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ex_19_1_5 USE ENTITY VHD.ex_19_1_5;
   -- pragma synthesis_on


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   reset <= '1', '0' after 2*clockPeriod;
   sClock <= not sClock after clockPeriod/2;
   clock <= transport sClock after clockPeriod*9/10;
   
   process
     constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod;
   begin
     start <= '0';
   
     wait for testDelay;
     start <= '1', '0' after clockPeriod;
   
     wait for testDelay;
     start <= '1', '0' after clockPeriod;
   
     wait;
   end process;
   
   
   
   


   -- Instance port mappings.
   I_dut : ex_19_1_5
      GENERIC MAP (
         speedBitNb => speedBitNb
      )
      PORT MAP (
         start => start,
         clock => clock,
         reset => reset,
         done  => done,
         speed => speed
      );

END struct;