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SEm-ExamMidterm2024/Prefs/hds_user/v2007.1a/templates/verilog_Interface/interface.sv

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2024-03-22 12:16:48 +00:00
FILE_NAMING_RULE: %(interface_name).sv
DESCRIPTION_START
This is the default template used for the creation of Interface files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog interface %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(interfaceBody)
// ### Please start your Verilog code here ###
endinterface