SEm-ExamMidterm2024/VHD/hdl/ex_24_1_4_studentVersion.vhd

architecture studentVersion of ex_24_1_4 is

  signal oldA: std_ulogic;
  signal oldB: std_ulogic;

begin

  process(reset, clock) begin
    if reset = '1' then 
      en <= '0';
      dir <= '0';
      oldA <= '0';
      oldA <= '0';
    elsif rising_edge(clock) then 
      oldA <= a;
      oldB <= b;

      if (a='1' and oldA='0') then
        en <= '1';
        if b = '0' then
          dir <= '1';
        else 
          dir <= '0';
        end if;
      elsif (b='1' and oldB='0') then
        en <= '1';
        if a = '0' then
          dir <= '0';
        else 
          dir <= '1';
        end if;
      elsif (a='0' and oldA='1') then
        en <= '1';
        if b = '1' then
          dir <= '1';
        else 
          dir <= '0';
        end if;
      elsif (b='0' and oldB='1') then
        en <= '1';
        if a = '1' then
          dir <= '0';
        else 
          dir <= '1';
        end if;
      else
        en <= '0';
      end if;
    end if;
  end process;

end studentVersion;