29 lines
611 B
VHDL
29 lines
611 B
VHDL
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-- VHDL Entity VHD.ex_24_1_1.symbol
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--
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-- Created:
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-- by - remy.borgeat.UNKNOWN (WE10993)
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-- at - 15:02:45 20.03.2024
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY ex_24_1_1 IS
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GENERIC(
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counterBitNb : positive := 8
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);
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PORT(
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en : IN std_ulogic;
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position : OUT unsigned (counterBitNb-1 DOWNTO 0);
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up_down : IN std_ulogic;
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clock : IN std_ulogic;
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reset : IN std_ulogic
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);
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-- Declarations
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END ex_24_1_1 ;
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