From 62378116732f5a095e96d9878cc1eb9dec88b204 Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 22 Mar 2024 14:04:21 +0100 Subject: [PATCH] exercice 4 --- VHD/hdl/ex_24_1_4_entity.vhd | 26 ++++++++ VHD/hdl/ex_24_1_4_studentVersion.vhd | 51 +++++++++++++- VHD_test/hdl/tb_24_1_4_entity.vhd | 15 +++++ VHD_test/hdl/tb_24_1_4_struct.vhd | 99 ++++++++++++++++++++++++++++ 4 files changed, 189 insertions(+), 2 deletions(-) create mode 100644 VHD/hdl/ex_24_1_4_entity.vhd create mode 100644 VHD_test/hdl/tb_24_1_4_entity.vhd create mode 100644 VHD_test/hdl/tb_24_1_4_struct.vhd diff --git a/VHD/hdl/ex_24_1_4_entity.vhd b/VHD/hdl/ex_24_1_4_entity.vhd new file mode 100644 index 0000000..8f74187 --- /dev/null +++ b/VHD/hdl/ex_24_1_4_entity.vhd @@ -0,0 +1,26 @@ +-- VHDL Entity VHD.ex_24_1_4.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 12:57:27 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_24_1_4 IS + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : OUT std_ulogic; + dir : OUT std_ulogic + ); + +-- Declarations + +END ex_24_1_4 ; + diff --git a/VHD/hdl/ex_24_1_4_studentVersion.vhd b/VHD/hdl/ex_24_1_4_studentVersion.vhd index 2c7362b..89f4325 100644 --- a/VHD/hdl/ex_24_1_4_studentVersion.vhd +++ b/VHD/hdl/ex_24_1_4_studentVersion.vhd @@ -1,5 +1,52 @@ architecture studentVersion of ex_24_1_4 is + + signal oldA: std_ulogic; + signal oldB: std_ulogic; + begin - en <= '0'; - dir <= '0'; + + process(reset, clock) begin + if reset = '1' then + en <= '0'; + dir <= '0'; + oldA <= '0'; + oldA <= '0'; + elsif rising_edge(clock) then + oldA <= a; + oldB <= b; + + if (a='1' and oldA='0') then + en <= '1'; + if b = '0' then + dir <= '1'; + else + dir <= '0'; + end if; + elsif (b='1' and oldB='0') then + en <= '1'; + if a = '0' then + dir <= '0'; + else + dir <= '1'; + end if; + elsif (a='0' and oldA='1') then + en <= '1'; + if b = '1' then + dir <= '1'; + else + dir <= '0'; + end if; + elsif (b='0' and oldB='1') then + en <= '1'; + if a = '1' then + dir <= '0'; + else + dir <= '1'; + end if; + else + en <= '0'; + end if; + end if; + end process; + end studentVersion; diff --git a/VHD_test/hdl/tb_24_1_4_entity.vhd b/VHD_test/hdl/tb_24_1_4_entity.vhd new file mode 100644 index 0000000..e0f5342 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_4_entity.vhd @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_24_1_4.symbol +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:24 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY tb_24_1_4 IS +-- Declarations + +END tb_24_1_4 ; + diff --git a/VHD_test/hdl/tb_24_1_4_struct.vhd b/VHD_test/hdl/tb_24_1_4_struct.vhd new file mode 100644 index 0000000..11a1c81 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_4_struct.vhd @@ -0,0 +1,99 @@ +-- +-- VHDL Architecture VHD_test.tb_24_1_4.struct +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:25 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_24_1_4 IS + + -- Architecture declarations + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL A : std_ulogic; + SIGNAL B : std_ulogic; + SIGNAL clock : std_ulogic; + SIGNAL dir : std_ulogic; + SIGNAL en : std_ulogic; + SIGNAL reset : std_ulogic; + + + -- Component Declarations + COMPONENT ex_24_1_4 + PORT ( + A : IN std_ulogic ; + B : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : OUT std_ulogic ; + dir : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_24_1_4 USE ENTITY VHD.ex_24_1_4; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + process + constant stepDelay: time := 1 us; + begin + wait for stepDelay; + for index in 0 to 10 loop + position_int <= position_int + 1; + wait for stepDelay; + end loop; + for index in 10 downto 0 loop + position_int <= position_int - 1; + wait for stepDelay; + end loop; + wait; + end process; + + process(position_int) + begin + case to_integer(to_unsigned(position_int, 2)) is + when 0 => A <= '0'; B <= '0'; + when 1 => A <= '1'; B <= '0'; + when 2 => A <= '1'; B <= '1'; + when 3 => A <= '0'; B <= '1'; + when others => null; + end case; + end process; + + + + + -- Instance port mappings. + I_dut : ex_24_1_4 + PORT MAP ( + A => A, + B => B, + clock => clock, + reset => reset, + en => en, + dir => dir + ); + +END struct;