From 8b2f630f7bda38ee1c60b15ba0a84a5392dd38f6 Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 22 Mar 2024 13:16:48 +0100 Subject: [PATCH] Initial commit --- .gitignore | 110 + .unorderedFilePath | 1 + .../policies/v2007_1a/My_Altera_Policy_policy | 11 + .../v2007_1a/My_Essentials_Policy_policy | 11 + .../policies/v2007_1a/My_RMM_Policy_policy | 11 + .../policies/v2007_1a/My_Xilinx_Policy_policy | 11 + .../policies/v2019_2/My_Altera_Policy_policy | 13 + .../v2019_2/My_Checklist_Policy_policy | 13 + .../policies/v2019_2/My_DO-254_Policy_policy | 13 + .../v2019_2/My_Essentials_Policy_policy | 13 + .../policies/v2019_2/My_RMM_Policy_policy | 13 + .../v2019_2/My_Safety-Critical_Policy_policy | 13 + .../policies/v2019_2/My_Xilinx_Policy_policy | 13 + .../v2019_2/Verification_OVM_Policy_policy | 14 + .../v2019_2/Verification_UVM_Policy_policy | 14 + .../rulesets/v2007_1a/Essentials_ruleset | 2419 ++++++ .../rulesets/v2019_2/Essentials_ruleset | 2563 +++++++ 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+*.log +*.bld +*.chk +*.cmd_log +*.cxt +*.gise +*.gyd +*.jed +*.lso +*.mfd +*.nga +*.ngc +*.ngd +*.ngr +*.pad +*.pnx +*.prj +*.rpt +*.stx +*.syr +*.tim +*.tspec +*.vm6 +*.xst +*.html +*.xrpt +*.err +*_html +*.sld +*.txt +*.qsys +*.csv +xst +netgen +iseconfig +xlnx_auto* +_ngo +_xmsgs +component.xml +*.jou +xgui +*.runs +*.srcs +*.sdk +.Xil +*_INFO.txt +*_dump.txt +db +*.asm.rpt +*.done +*.eda.rpt +*.fit.* +*.map.* +*.sta.* +*.qsf +*.qpf +*.qws +*.sof +*.rbf +system_qsys_script.tcl +hc_output +hps_isw_handoff +hps_sdram_*.csv +incremental_db +system_bd/ +reconfig_mif +*.sopcinfo +*.jdi +*.pin +*.os +*webtalk* +*.xml +*.hw +gui +.timestamp_intel +temporary_case_dependencies.mk +*.zip +*.str +*.vcd +*.wlf +transcript +tags +boot_bin +_info +_vmake +*.qdb +*.qpg +*.qtl +*.xpe +*.gen* +*.xsa +*.pdi +library/**/bd/bd.tcl +*.syn.smsg +*.syn.summary +qdb +tmp-clearbox +*.bin +__pycache__ +_build +.qsys_edit +.github/CODEOWNERS +.github/PULL_REQUEST_TEMPLATE.md +library/**/.lock \ No newline at end of file diff --git a/.unorderedFilePath b/.unorderedFilePath new file mode 100644 index 0000000..fb83269 --- /dev/null +++ b/.unorderedFilePath @@ -0,0 +1 @@ +C:\Users\REMY~1.BOR\AppData\Local\Temp\rtlc2/rtlc_files_vhdl \ No newline at end of file diff --git a/Prefs/dc_user/policies/v2007_1a/My_Altera_Policy_policy b/Prefs/dc_user/policies/v2007_1a/My_Altera_Policy_policy new file mode 100644 index 0000000..53f43d4 --- /dev/null +++ b/Prefs/dc_user/policies/v2007_1a/My_Altera_Policy_policy @@ -0,0 +1,11 @@ +version "4.2" +Policy (Policy +name "My_Altera_Policy" +build "DesignChecker 2007.1a (Build 13) +Built on Mon Feb 25 2008 at 12:14" +RuleSets [ +"Altera" +] +DisabledConfiguredRules [ +] +) diff --git a/Prefs/dc_user/policies/v2007_1a/My_Essentials_Policy_policy b/Prefs/dc_user/policies/v2007_1a/My_Essentials_Policy_policy new file mode 100644 index 0000000..9141e7d --- /dev/null +++ b/Prefs/dc_user/policies/v2007_1a/My_Essentials_Policy_policy @@ -0,0 +1,11 @@ +version "4.2" +Policy (Policy +name "My_Essentials_Policy" +build "DesignChecker 2007.1a (Build 13) +Built on Mon Feb 25 2008 at 12:14" +RuleSets [ +"Essentials" +] +DisabledConfiguredRules [ +] +) diff --git a/Prefs/dc_user/policies/v2007_1a/My_RMM_Policy_policy b/Prefs/dc_user/policies/v2007_1a/My_RMM_Policy_policy new file mode 100644 index 0000000..2afa905 --- /dev/null +++ b/Prefs/dc_user/policies/v2007_1a/My_RMM_Policy_policy @@ -0,0 +1,11 @@ +version "4.2" +Policy (Policy +name "My_RMM_Policy" +build "DesignChecker 2007.1a (Build 13) +Built on Mon Feb 25 2008 at 12:14" +RuleSets [ +"RMM" +] +DisabledConfiguredRules [ +] +) diff --git a/Prefs/dc_user/policies/v2007_1a/My_Xilinx_Policy_policy b/Prefs/dc_user/policies/v2007_1a/My_Xilinx_Policy_policy new file mode 100644 index 0000000..f544c94 --- /dev/null +++ b/Prefs/dc_user/policies/v2007_1a/My_Xilinx_Policy_policy @@ -0,0 +1,11 @@ +version "4.2" +Policy (Policy +name "My_Xilinx_Policy" +build "DesignChecker 2007.1a (Build 13) +Built on Mon Feb 25 2008 at 12:14" +RuleSets [ +"Xilinx" +] +DisabledConfiguredRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_Altera_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_Altera_Policy_policy new file mode 100644 index 0000000..88b7e0b --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_Altera_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_Altera_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Altera" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_Checklist_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_Checklist_Policy_policy new file mode 100644 index 0000000..2a7cc69 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_Checklist_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_Checklist_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Checklist" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_DO-254_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_DO-254_Policy_policy new file mode 100644 index 0000000..c9e8450 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_DO-254_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_DO-254_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"DO-254" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_Essentials_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_Essentials_Policy_policy new file mode 100644 index 0000000..5bad6a9 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_Essentials_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_Essentials_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Essentials" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_RMM_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_RMM_Policy_policy new file mode 100644 index 0000000..c24177e --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_RMM_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_RMM_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"RMM" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_Safety-Critical_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_Safety-Critical_Policy_policy new file mode 100644 index 0000000..4d81fd3 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_Safety-Critical_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_Safety-Critical_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Safety-Critical" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/My_Xilinx_Policy_policy b/Prefs/dc_user/policies/v2019_2/My_Xilinx_Policy_policy new file mode 100644 index 0000000..48d1389 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/My_Xilinx_Policy_policy @@ -0,0 +1,13 @@ +version "19.2" +Policy (Policy +name "My_Xilinx_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Xilinx" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/Verification_OVM_Policy_policy b/Prefs/dc_user/policies/v2019_2/Verification_OVM_Policy_policy new file mode 100644 index 0000000..e9316a1 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/Verification_OVM_Policy_policy @@ -0,0 +1,14 @@ +version "19.2" +Policy (Policy +name "Verification_OVM_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Verification_OVM" +"Verification_SV" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/policies/v2019_2/Verification_UVM_Policy_policy b/Prefs/dc_user/policies/v2019_2/Verification_UVM_Policy_policy new file mode 100644 index 0000000..82f28e2 --- /dev/null +++ b/Prefs/dc_user/policies/v2019_2/Verification_UVM_Policy_policy @@ -0,0 +1,14 @@ +version "19.2" +Policy (Policy +name "Verification_UVM_Policy" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +RuleSets [ +"Verification_UVM" +"Verification_SV" +] +DisabledConfiguredRules [ +] +JustificationForDisabledRules [ +] +) diff --git a/Prefs/dc_user/rulesets/v2007_1a/Essentials_ruleset b/Prefs/dc_user/rulesets/v2007_1a/Essentials_ruleset new file mode 100644 index 0000000..e5a299e --- /dev/null +++ b/Prefs/dc_user/rulesets/v2007_1a/Essentials_ruleset @@ -0,0 +1,2419 @@ +version "4.2" +EngineDLLVersion "2.1" +TopRuleSet (RuleSet +name "Essentials" +build "DesignChecker 2007.1a (Build 13) +Built on Mon Feb 25 2008 at 12:14" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +isDefaultLevel 1 +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +isDefaultLevel 0 +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +isDefaultLevel 0 +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +(RuleSet +name "Coding Practices" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +isDefaultLevel 1 +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +isDefaultLevel 0 +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +isDefaultLevel 0 +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +] +Rules [ +(ConfiguredRule +BaseRuleName "Unknown Objects" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unknown Objects" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Objects must be declared before being used." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for objects which are used, but have not been declared." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unknown" +"objects" +"identifiers" +"dependencies" +] +) +(Params +ParamName "Detect" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unused Declarations" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unused Declarations" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"The object has been declared but not used (read from or assigned to)." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for objects which have been declared, but are never used." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unused" +"declarations" +"unread" +"unwritten" +"uncalled" +"identifiers" +] +) +(Params +ParamName "Detect" +ParamValues [ +"Identifiers: Read but not Written" +"Identifiers: Written but not Read" +"Identifiers: Neither Read nor Written" +"Generics: Not Used" +"Functions: Not Called" +"Procedures: Not Called" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unassigned Objects" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unassigned Objects" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Objects should be assigned values before they are used." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks objects are assigned values before they are used." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unassigned" +"objects" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unconnected Ports" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unconnected Ports" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"All output ports should be connected. All input ports should be driven by another signal or constant '0 or '1' value." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that input and/or output ports are connected." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unconnected" +"ports" +"input" +"output" +"bi-directional" +] +) +(Params +ParamName "Detect" +ParamValues [ +"All Unconnected Ports" +] +) +] +) +(ConfiguredRule +BaseRuleName "Gated Clocks" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Gated Clocks" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid gated clocks." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of gated clocks." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"gated" +"gating" +"synchronous" +"enable" +"load" +"register" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow if Using Synchronous Load Registers" +] +) +] +) +(ConfiguredRule +BaseRuleName "Internally Generated Clocks" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Internally Generated Clocks" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Internally generated clocks should be isolated at the top-level." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks any internally generated clocks are isolated at the top-level." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"generated" +"internally" +"isolation" +"isolated" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow if isolated at Top-Level" +] +) +] +) +(ConfiguredRule +BaseRuleName "Internally Generated Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Internally Generated Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Internally generated resets should be isolated at the top-level." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks any internally generated resets are isolated at the top-level." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"asynchronous" +"generated" +"internally" +"isolation" +"isolated" +"resets" +"synchronous" +"style" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow if isolated at Top-Level" +] +) +(Params +ParamName "Reset Style" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Mixed Clocks Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Mixed Clocks Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not use the same signal as a clock and reset." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for signals being used as both clock and reset." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"mixed" +"resets" +] +) +] +) +(ConfiguredRule +BaseRuleName "Consistent Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Consistent Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not use the same reset signal with mixed styles or polarities within the same process/block." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks the reset signal is used consistently." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"asynchronous" +"consistent" +"mixed" +"polarity" +"resets" +"synchronous" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Disallow" +ParamValues [ +"Mixed Synchronous/Asynchronous Styles" +"Mixed Polarities" +] +) +(Params +ParamName "Hierarchy Level" +ParamValues [ +"Process" +] +) +] +) +(ConfiguredRule +BaseRuleName "Multiple Drivers" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Multiple Drivers" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not assign to the same signal/variable in more than one sequential block." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for multiple drivers." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"drivers" +"multiple" +] +) +] +) +(ConfiguredRule +BaseRuleName "Matching Range" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Matching Range" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure bit widths on both sides of an assignment/comparison match. Ensure Port & Net declarations match." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for compatible bit widths." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"assignments" +"associations" +"comparisons" +"declarations" +"explicit" +"port" +"net" +"widths" +"out-of-boud" +"index" +] +) +(Params +ParamName "Match" +ParamValues [ +"Explicit Widths in Assignments" +"Explicit Widths in Comparisons" +"Explicit Widths in Associations" +"Port & Net Declarations" +] +) +] +) +(ConfiguredRule +BaseRuleName "FSM Transitions" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"FSM Transitions" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure unused states transition directly to the initialization state." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that unused states can transition to a recovery state and that all states transition to a known state." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"FSM" +"states" +"transitions" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Detect Transitions" +ParamValues [ +"" +] +) +(Params +ParamName "State Variables" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Logical and Bitwise Operators" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Logical and Bitwise Operators" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Use logical and bit-wise operators correctly." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the correct usage of Verilog logical and bit-wise operators." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"bitwise" +"logical" +"operators" +] +) +] +) +(ConfiguredRule +BaseRuleName "Sub-Program Body" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Sub-Program Body" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure the sub-program has only one exit point and is not recursive." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks if the sub-program has a single exit point and is not recursive." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"subprogram" +"functions" +"procedures" +"local" +"variables" +"non-local" +] +) +(Params +ParamName "Sub-Program" +ParamValues [ +"Functions" +"Procedures" +"Tasks" +] +) +(Params +ParamName "Allow Assign To" +ParamValues [ +"" +] +) +(Params +ParamName "Disallow" +ParamValues [ +"Multiple exit points/return statements" +"Missing exit point/return statement" +"Recursion" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unique Names" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unique Names" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Use unique FSM states names throughout the design." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that FSM states names are unique throughout the design." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"names" +"unique" +"FSM" +"instance" +] +) +(Params +ParamName "Unique" +ParamValues [ +"FSM state names" +] +) +] +) +] +) +(RuleSet +name "Downstream Checks" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +isDefaultLevel 1 +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +isDefaultLevel 0 +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +isDefaultLevel 0 +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +] +Rules [ +(ConfiguredRule +BaseRuleName "Sensitivity List" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Sensitivity List" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Sensitivity list should contain only the signals needed by the process/block." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that sensitivity lists are complete and do not include unnecessary signals." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"missing" +"sensitivity" +"sliced" +"unneeded" +] +) +(Params +ParamName "Check For" +ParamValues [ +"Missing Signals" +"Unneeded Signals" +"Sliced Signals" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unsynthesizable Event Controls" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unsynthesizable Event Controls" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid the use of non-synthesizable Event Controls." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for unsynthesizable event controls in sensitivity lists." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"synthesizable" +"event" +"controls" +] +) +] +) +(ConfiguredRule +BaseRuleName "Clock Used As Data" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Clock Used As Data" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid using clock signals as data." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for clock signals being used as data." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clock" +"condition" +"data" +"race" +"Verilog" +"VHDL" +] +) +] +) +(ConfiguredRule +BaseRuleName "Latch Inference" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Latch Inference" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid latch inference." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the possible inference of latches." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"latch" +"inference" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"All Block Types" +] +) +] +) +(ConfiguredRule +BaseRuleName "Register IO" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Register IO" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"All outputs of each process/block of a hierarchical design should be registered." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that process/block and FSM output ports are registered." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"register" +"input" +"output" +"IO" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"Block Outputs" +"FSM Outputs" +] +) +(Params +ParamName "Check Non-Clocked Blocks" +ParamValues [ +"No" +] +) +] +) +(ConfiguredRule +BaseRuleName "Eliminate Glue Logic" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Eliminate Glue Logic" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure Verilog built-in primitives are isolated into separate modules." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks any instances of Verilog built-in primitives and UDPs are isolated into separate modules." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"glue-logic" +"eliminate" +"UDPs" +"Primitives" +] +) +(Params +ParamName "Logic Type" +ParamValues [ +"Primitives" +"UDPs" +] +) +(Params +ParamName "Hierarchy Level" +ParamValues [ +"Top-Level" +] +) +(Params +ParamName "Isolation" +ParamValues [ +"Isolate Gates in Separate Modules" +] +) +] +) +(ConfiguredRule +BaseRuleName "Initialization Assignments" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Initialization Assignments" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid using default initialization." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of initialization assignments rather than explicit resets." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"assignments" +"initializations" +] +) +] +) +(ConfiguredRule +BaseRuleName "Allowed Constructs" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Non Synthesizable Constructs" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid constructs which make the code non-synthesizable." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of non-synthesizable language constructs (except delays)" +] +) +(Params +ParamName "Keywords" +ParamValues [ +"allowed" +"constructs" +"non-portable" +"non-synthesizable" +"portable" +"synthesizable" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Disallowed Constructs" +ParamValues [ +"Functions Returning Type Real" +"while Loops" +"Multiple Wait Statements on Same Clock" +"Real Types" +"Zero Delayed Assignments" +"Incomplete Types" +"Infinite Loops" +"Global Signals" +"ALIAS" +"BUFFER" +"Enumeration Type as Array Index" +"FILE" +"INERTIAL Delay" +"POSTPONED" +"PURE FUNCTION" +"TRANSPORT Delay" +"VARIABLE" +"WAIT" +"WAIT with Timeout" +"`timescale" +"Array of Integers" +"casex" +"casez" +"deassign" +"defparam" +"event" +"force" +"fork join" +"Hierarchical Names" +"initial Blocks" +"Net Strengths" +"Procedural Continuous assign" +"forever Loops" +"repeat Loops" +"release" +"specify" +"String Literals" +"System Functions" +"System Tasks" +"$finish" +"$stop" +"time" +"User Defined Primitives" +] +) +] +) +(ConfiguredRule +BaseRuleName "Untested Edge Trigger" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Untested Edge Trigger" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Synthesis requires a single, untested edge trigger in order to identify the clock." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for a single untested edge trigger in Verilog event control logic." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"edge" +"triggers" +] +) +] +) +(ConfiguredRule +BaseRuleName "Constrained Ranges & Bounds" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Constrained Ranges & Bounds" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"VHDL Integer, and Real number types must have ranges. Vector types must have bounds" +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that all VHDL numbers have specified ranges and all vectors have specified bounds." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"bounds" +"constrained" +"ranges" +"vector" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"" +] +) +(Params +ParamName "Range / Bound" +ParamValues [ +"" +] +) +(Params +ParamName "Range Type" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Asynchronous Block" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Asynchronous Block" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Asynchronous always block contains more than one sequential statement, this may be not synthesizable" +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks the synthesizability of asynchronous Verilog always blocks." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"asynchronous" +"block" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Detect" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Allowed Operators" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Non Synthesizable Operators" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not use disallowed operators." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for disallowed operators usage." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"Operators" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Scope" +ParamValues [ +"" +"" +"" +] +) +(Params +ParamName "Disallowed Operators" +ParamValues [ +"Case Equality ( === )" +"Case Inequality ( !== )" +] +) +] +) +] +) +(RuleSet +name "Code Reuse" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +isDefaultLevel 1 +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +isDefaultLevel 0 +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +isDefaultLevel 0 +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +] +Rules [ +(ConfiguredRule +BaseRuleName "Allowed Constructs" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Non-Portable Constructs" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid constructs which make the code non-portable." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of non-portable language constructs." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"allowed" +"constructs" +"non-portable" +"non-synthesizable" +"portable" +"synthesizable" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Disallowed Constructs" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Allowed Pragmas" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Allowed Pragmas" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid embedded, tool-specific pragmas/commands." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of pragmas other than translate_on/off, synthesis_on/off" +] +) +(Params +ParamName "Keywords" +ParamValues [ +"pragmas" +"synthesis" +] +) +(Params +ParamName "Disallowed Pragmas" +ParamValues [ +"Other Specific Pragmas" +] +) +] +) +(ConfiguredRule +BaseRuleName "Vector Order" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Vector Order" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure all vector dimensions are ordered high to low and the low index bound is 0." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks all vector dimensions are ordered high to low and the low index bound is 0." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"order" +"vector" +] +) +(Params +ParamName "Style" +ParamValues [ +"Descending" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"Vector Bounds" +"Integer Range Constraints" +"Real Range Constraints" +] +) +(Params +ParamName "Low Index Bound" +ParamValues [ +"0" +] +) +] +) +(ConfiguredRule +BaseRuleName "VITAL Port Types" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"VITAL Port Types" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Top level ports must use STD_LOGIC_1164 types only." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that top-level ports use types from Std_Logic_1164 only." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"VITAL" +"port" +"type" +] +) +(Params +ParamName "Scalar Ports Types" +ParamValues [ +"std_logic" +"std_ulogic" +"Any subtype of std_ulogic" +] +) +(Params +ParamName "Array Ports Types" +ParamValues [ +"std_logic_vector" +"std_ulogic_vector" +] +) +] +) +(ConfiguredRule +BaseRuleName "Allowed Constructs" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Reserved Words" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid the use of VHDL reserved words in Verilog designs and vice-versa" +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of VHDL reserved words in Verilog and vice-versa" +] +) +(Params +ParamName "Keywords" +ParamValues [ +"allowed" +"constructs" +"non-portable" +"non-synthesizable" +"portable" +"synthesizable" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Disallowed Constructs" +ParamValues [ +"" +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Allowed Types" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Use IEEE types only" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Use IEEE types only. Subtypes must be based on IEEE standard types." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks all types are IEEE types or subtypes based on IEEE standard types." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"allowed" +"enumeration" +"IEEE" +"types" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow" +] +) +(Params +ParamName "Packages" +ParamValues [ +"ieee.*" +] +) +(Params +ParamName "Types" +ParamValues [ +"" +] +) +(Params +ParamName "Excluded Types" +ParamValues [ +"FSM State Variables Enum Type" +] +) +] +) +] +) +] +Rules [ +] +) diff --git a/Prefs/dc_user/rulesets/v2019_2/Essentials_ruleset b/Prefs/dc_user/rulesets/v2019_2/Essentials_ruleset new file mode 100644 index 0000000..5ccbbde --- /dev/null +++ b/Prefs/dc_user/rulesets/v2019_2/Essentials_ruleset @@ -0,0 +1,2563 @@ +version "19.2" +EngineDLLVersion "19.2" +TopRuleSet (RuleSet +name "Essentials" +build "DesignChecker 2019.2 (Build 5) +Built on Sat Apr 20 2019 at 23:04" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +(RuleSet +name "Coding Practices" +UserDefinedSeverity "Default SeveritySet" +SeverityClassDefinition (SeverityClass +SeverityClassName "Default SeveritySet" +SeverityLevels [ +(SeverityLevel +LevelName "Error" +Red 255 +Green 0 +Blue 0 +Score 5 +Weight 2 +) +(SeverityLevel +LevelName "Warning" +Red 0 +Green 0 +Blue 255 +Score 2 +Weight 1 +) +(SeverityLevel +LevelName "Note" +Red 0 +Green 255 +Blue 0 +Score 1 +Weight 1 +) +] +) +RuleSets [ +] +Rules [ +(ConfiguredRule +BaseRuleName "Unused Declarations" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unused Declarations" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"The object has been declared but not used (read from or assigned to)." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for objects which have been declared, but are never used." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unused" +"declarations" +"unread" +"unwritten" +"uncalled" +"identifiers" +] +) +(Params +ParamName "Detect" +ParamValues [ +"Identifiers: Read but not Written" +"Identifiers: Written but not Read" +"Identifiers: Neither Read nor Written" +"Generics: Not Used" +"Functions: Not Called" +"Procedures: Not Called" +] +) +(Params +ParamName "Consider Identifiers Slices" +ParamValues [ +"Yes" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unassigned Objects" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unassigned Objects" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Objects should be assigned values before they are used." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks objects are assigned values before they are used." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unassigned" +"objects" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unconnected Ports" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unconnected Ports" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"All output ports should be connected. All input ports should be driven by another signal or constant '0 or '1' value." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that input and/or output ports are connected." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"unconnected" +"ports" +"input" +"output" +"bi-directional" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"Input Ports" +"Output Ports" +"Bidirectional Ports" +] +) +(Params +ParamName "Detect Floating Connection" +ParamValues [ +"No" +] +) +] +) +(ConfiguredRule +BaseRuleName "Gated Clocks" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Gated Clocks" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Avoid gated clocks." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the use of gated clocks." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"gated" +"gating" +"synchronous" +"enable" +"load" +"register" +] +) +(Params +ParamName "Ignore" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Internally Generated Clocks" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Internally Generated Clocks" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Internally generated clocks should be isolated at the top-level." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks any internally generated clocks are isolated at the top-level." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"generated" +"internally" +"isolation" +"isolated" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow if isolated at Top-Level" +] +) +] +) +(ConfiguredRule +BaseRuleName "Internally Generated Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Internally Generated Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Internally generated resets should be isolated at the top-level." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks any internally generated resets are isolated at the top-level." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"asynchronous" +"generated" +"internally" +"isolation" +"isolated" +"resets" +"synchronous" +"style" +] +) +(Params +ParamName "Action" +ParamValues [ +"Allow if isolated at Top-Level" +] +) +(Params +ParamName "Reset Style" +ParamValues [ +"" +] +) +(Params +ParamName "Ignore" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Mixed Clocks Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Mixed Clocks Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not use the same signal as a clock and reset." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for signals being used as both clock and reset." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"clocks" +"mixed" +"resets" +] +) +] +) +(ConfiguredRule +BaseRuleName "Consistent Resets" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Consistent Resets" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not use the same reset signal with mixed styles or polarities within the same process/block." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks the reset signal is used consistently." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"asynchronous" +"consistent" +"mixed" +"polarity" +"resets" +"synchronous" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Disallow" +ParamValues [ +"Mixed Synchronous/Asynchronous Styles" +"Mixed Polarities" +] +) +(Params +ParamName "Hierarchy Level" +ParamValues [ +"Process" +] +) +(Params +ParamName "Applies To" +ParamValues [ +"FSM State Variable Registers" +"Other Registers" +] +) +(Params +ParamName "Consistency" +ParamValues [ +"Single Reset" +] +) +] +) +(ConfiguredRule +BaseRuleName "Multiple Drivers" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Multiple Drivers" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Do not assign to the same signal/variable in more than one sequential block." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for multiple drivers." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"drivers" +"multiple" +] +) +] +) +(ConfiguredRule +BaseRuleName "Matching Range" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Matching Range" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure bit widths on both sides of an assignment/comparison match. Ensure Port & Net declarations match." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for compatible bit widths." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"assignments" +"associations" +"comparisons" +"declarations" +"explicit" +"port" +"net" +"widths" +"out-of-boud" +"index" +] +) +(Params +ParamName "Match" +ParamValues [ +"Explicit Widths in Assignments" +"Operands of comparison operators" +"Explicit Widths in Associations" +"Port & Net Declarations" +] +) +(Params +ParamName "Ignore" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "FSM Transitions" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"FSM Transitions" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure unused states transition directly to the initialization state." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that unused states can transition to a recovery state and that all states transition to a known state." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"FSM" +"states" +"transitions" +"Verilog" +"VHDL" +] +) +(Params +ParamName "Detect" +ParamValues [ +"Transitions Without Default Handling" +"States Without Incoming Transitions" +"States Without Outgoing Transitions" +] +) +(Params +ParamName "State Variables" +ParamValues [ +"" +] +) +] +) +(ConfiguredRule +BaseRuleName "Logical and Bitwise Operators" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Logical and Bitwise Operators" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Use logical and bit-wise operators correctly." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for the correct usage of Verilog logical and bit-wise operators." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"bitwise" +"logical" +"operators" +] +) +] +) +(ConfiguredRule +BaseRuleName "Sub-Program Body" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Sub-Program Body" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Ensure the sub-program has only one exit point and is not recursive." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks if the sub-program has a single exit point and is not recursive." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"subprogram" +"functions" +"procedures" +"local" +"variables" +"non-local" +] +) +(Params +ParamName "Sub-Program" +ParamValues [ +"Functions" +"Procedures / Tasks" +] +) +(Params +ParamName "Allow Assign To" +ParamValues [ +"" +] +) +(Params +ParamName "Disallow" +ParamValues [ +"Multiple exit points/return statements" +"Missing exit point/return statement" +"Recursion" +] +) +] +) +(ConfiguredRule +BaseRuleName "Unique Names" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unique Names" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Warning" +] +) +(Params +ParamName "Score" +ParamValues [ +"2" +] +) +(Params +ParamName "Weight" +ParamValues [ +"1" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Use unique FSM states names throughout the design." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks that FSM states names are unique throughout the design." +] +) +(Params +ParamName "Keywords" +ParamValues [ +"names" +"unique" +"FSM" +"instance" +] +) +(Params +ParamName "Unique" +ParamValues [ +"FSM state names" +] +) +] +) +(ConfiguredRule +BaseRuleName "Undefined Design Units" +UserDefinedSeverity "Default SeveritySet" +Params [ +(Params +ParamName "Name" +ParamValues [ +"Unknown Objects" +] +) +(Params +ParamName "Severity" +ParamValues [ +"Error" +] +) +(Params +ParamName "Score" +ParamValues [ +"5" +] +) +(Params +ParamName "Weight" +ParamValues [ +"2" +] +) +(Params +ParamName "Language" +ParamValues [ +"VHDL Any" +"Verilog Any" +] +) +(Params +ParamName "Hint" +ParamValues [ +"Objects must be declared before being used." +] +) +(Params +ParamName "Short Description" +ParamValues [ +"Checks for objects which are used, but have not been declared." +] +) +(Params +ParamName "Keywords" +ParamValues [ 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+showGettingStarted 1 +masterClocks [ +] +masterResets [ +] +vhdlExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogExtensions [ +"v" +"vlg" +"verilog" +"vo" +] +verilogSearchPath "" +verilogLibraryOrder "" +verilogDefaultLibrary "verilog" +vhdlDefaultLibrary "vhdl" +rulesetLocation "" +lastOpenProject "" +autoDetectDesignRoot 1 +recentProjects [ +] +Viewpoints_V2 [ +(Viewpoint_v2 +name "All: (No Groups)" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Rule Severity" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Category" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Ruleset" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Severity, Ruleset and Rule" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Design Unit Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Scope" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Library, Design Unit and Scope" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Filename" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Leaf Filename" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "File and Line" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Full Message" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Message" +width 24 +alignment 1 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "List: (No Groups)" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Rule Severity" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Category" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Ruleset" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Design Unit Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Scope" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Filename" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Leaf Filename" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Hint" +width 394 +alignment 0 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "Severity & File" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 64 +alignment 0 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +"Rule Severity" +"Leaf Filename" +"Rule Name" +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "Severity & Ruleset" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 64 +alignment 0 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +"Rule Severity" +"Severity, Ruleset and Rule" +"Library, Design Unit and Scope" +] +disableFilters 1 +) +] +layoutExpression "" +) +] +activeViewpoint 3 +shortcutViewpoints [ +"All: (No Groups)" +"List: (No Groups)" +"Severity & File" +"Severity & Ruleset" +] +summaryExpandCollapseState [ +1 +1 +0 +0 +0 +0 +] +defaultPolicyName "My_Essentials_Policy" +expandedFolders [ +] +selectedFolder [ +] +selectedItem "" +searchPattern "" +searchMatchAllWords 0 +searchIncludeSynonyms 0 +searchMatchWholeWordOnly 0 +searchMatchCase 0 +searchUseRegularExpression 0 +searchSelectedParams [ +] +searchSelectedNodes [ +] +searchExpandedNodes [ +] +checkedExampleRulesets [ +] +SeverityClasses [ +] +ActiveSeverityClass -1 +ActiveSeverityClassName "" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +enableScoring 1 +includeDisabledRules 0 +) +] diff --git a/Prefs/dc_user/v2019_2/dc_user_prefs b/Prefs/dc_user/v2019_2/dc_user_prefs new file mode 100644 index 0000000..a36f5f7 --- /dev/null +++ b/Prefs/dc_user/v2019_2/dc_user_prefs @@ -0,0 +1,507 @@ +version "19.2" +Lint [ +(LintPreferences +version "1.1" +xPos 100 +yPos 100 +width 820 +height 650 +unixHTMLViewer "" +showGettingStarted 1 +masterClocks [ +] +masterResets [ +] +vhdlExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogSearchPath "" +verilogLibraryOrder "" +verilogDefaultLibrary "work" +vhdlDefaultLibrary "work" +rulesetLocation "" +lastOpenProject "" +autoDetectDesignRoot 1 +recentProjects [ +] +Viewpoints_V2 [ +(Viewpoint_v2 +name "All: (No Groups)" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Rule Severity" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Category" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Ruleset" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Severity, Ruleset and Rule" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Design Unit Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Scope" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Library, Design Unit and Scope" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Filename" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Leaf Filename" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "File and Line" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Full Message" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Message" +width 24 +alignment 1 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +"SV Packages" +"Interfaces" +"Program Blocks" +"Classes" +"Contexts" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "List: (No Groups)" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Rule Severity" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Category" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Ruleset" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Rule Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Library" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Design Unit Name" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Scope" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Filename" +width 200 +alignment 0 +) +(SmartTableVPData_Column +name "Leaf Filename" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 100 +alignment 0 +) +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Hint" +width 394 +alignment 0 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +"SV Packages" +"Interfaces" +"Program Blocks" +"Classes" +"Contexts" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "Severity & File" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 64 +alignment 0 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +"SV Packages" +"Interfaces" +"Program Blocks" +"Classes" +"Contexts" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +"Rule Severity" +"Leaf Filename" +"Rule Name" +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "Severity & Ruleset" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Message" +width 593 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 64 +alignment 0 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Configurations" +"Entities" +"Files" +"Modules" +"Package Bodies" +"Package Headers" +"Syntax Errors" +"SV Packages" +"Interfaces" +"Program Blocks" +"Classes" +"Contexts" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +"Rule Severity" +"Severity, Ruleset and Rule" +"Library, Design Unit and Scope" +] +disableFilters 1 +) +] +layoutExpression "" +) +(Viewpoint_v2 +name "Severity & Rule Path" +TreeListVPDatas [ +] +SmartTableVPDatas [ +(SmartTableVPData +theList "" +columns [ +(SmartTableVPData_Column +name "Message" +width 556 +alignment 0 +) +(SmartTableVPData_Column +name "Line Number" +width 64 +alignment 0 +) +(SmartTableVPData_Column +name "Code Snippet" +width 80 +alignment 1 +) +(SmartTableVPData_Column +name "Hint" +width 21 +alignment 1 +) +] +filterNames [ +"Architectures" +"Classes" +"Configurations" +"Contexts" +"Entities" +"Files" +"Interfaces" +"Modules" +"Package Bodies" +"Package Headers" +"Program Blocks" +"SV Packages" +"Syntax Errors" +] +filterString "" +filterColumn "" +matchCase 0 +matchWholeWordOnly 0 +regularExpression 1 +groupNames [ +"Rule Severity" +"Severity and Rule Path" +"Library, Design Unit and Scope" +] +disableFilters 1 +) +] +layoutExpression "" +) +] +activeViewpoint 3 +shortcutViewpoints [ +"All: (No Groups)" +"List: (No Groups)" +"Severity & File" +"Severity & Ruleset" +"Severity & Rule Path" +] +summaryExpandCollapseState [ +1 +1 +0 +0 +0 +0 +] +defaultPolicyName "My_Essentials_Policy" +expandedFolders [ +] +selectedFolder [ +] +selectedItem "" +searchPattern "" +searchMatchAllWords 0 +searchIncludeSynonyms 0 +searchMatchWholeWordOnly 0 +searchMatchCase 0 +searchUseRegularExpression 0 +searchSelectedParams [ +] +reportMissingDeclarations 0 +reportMissingDeclarationsLocation "" +generateMissingDeclarations 0 +generateMissingDeclarationsOption "" +generatedMissingDeclarationsLocation "" +copyBeforeOverwriteGeneratedFiles 0 +treatDonttouchAsMissingDeclarations 0 +generateMissingBuffer 0 +copyBeforeOverwritePrefix "" +promptJustification 1 +displayWaivers 0 +allowSynthPragmasToDisableParsing 0 +enableSummaryExtraInfo 1 +searchSelectedNodes [ +] +searchExpandedNodes [ +] +checkedExampleRulesets [ +] +SeverityClasses [ +] +ActiveSeverityClass -1 +ActiveSeverityClassName "" +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +enableScoring 1 +includeDisabledRules 0 +) +] diff --git a/Prefs/dp_user/v2_61/dp_user_prefs b/Prefs/dp_user/v2_61/dp_user_prefs new file mode 100644 index 0000000..fb1de26 --- /dev/null +++ b/Prefs/dp_user/v2_61/dp_user_prefs @@ -0,0 +1,40 @@ +[Editor] +mark.lineImage=yellowball +[LexParser] +[Printer] +[DND] +TrackerBg=SystemHighlight +signalAcceptDropBg=white +signalRefuseDropBg=red +[General] +[Browser] +normalTextBg=white +normalTextFg=black +[Replace] +historyMax=4 +atomicReplaceAll=No +[Console] +[Templates] +Visibility=No +[SearchInFiles] +SearchAsRegExp=0 +MatchCase=0 +LookInSubfolders=0 +historyMax=4 +[VDiff] +[R72] +indentType=spaces +indentString=\#\#\# +[TCOM] +logTCOMActivity=No +afterIdleHandlerTimeSlice=300 +[ToolbarFrames] +Group1=Standard Search +Group2=Edit Bookmarks View Macros DocumentTools Windows +Group3=VersionManagement Tasks +[Help] +default=te_guide +[Plugins] +userLanguages= +[Search] +historyMax=4 diff --git a/Prefs/dp_user/v2_72/dp_user_prefs b/Prefs/dp_user/v2_72/dp_user_prefs new file mode 100644 index 0000000..04bf800 --- /dev/null +++ b/Prefs/dp_user/v2_72/dp_user_prefs @@ -0,0 +1,70 @@ +[LexParser] +[Editor] +mark.lineImage=yellowball +recentFile0=/media/francois/Transfer/math_real.vhdl +lastFilter=vhdl +recentFile1=/usr/opt/HDS/hdl_libs/ieee/hdl/math_real.vhdl +recentFile2=/media/francois/Transfer/std_logic_1164.vhdl +recentFile3=/usr/opt/HDS/hdl_libs/ieee/hdl/std_logic_1164.vhdl +[Printer] +ENSCRIPT_LIBRARY=/usr/opt/HDS/resources/enscript/share/enscript +[ToolbarFrames] +geom0Group1=top H +geom0Group2=top H +geom0Group3=top H +state0Search=1 +Num=0 +state0VersionManagement=1 +state0Tasks=1 +state0View=1 +state0Standard=1 +state0Edit=1 +Group1=Standard Search +Group2=Edit Bookmarks View Macros DocumentTools Windows +Group3=VersionManagement Tasks +state0Macros=1 +state0Bookmarks=1 +state0Windows=1 +state0DocumentTools=1 +[DND] +TrackerBg=#c3c3c3 +signalAcceptDropBg=white +signalRefuseDropBg=red +[General] +[Browser] +normalTextBg=white +normalTextFg=black +[Replace] +historyMax=4 +atomicReplaceAll=No +[Console] +[Templates] +Visibility=No +[SearchInFiles] +SearchAsRegExp=0 +MatchCase=0 +LookInSubfolders=0 +historyMax=4 +[VDiff] +[R72] +indentType=spaces +indentString=\#\#\# +[TCOM] +logTCOMActivity=No +afterIdleHandlerTimeSlice=300 +[Menus] +DocAndVis= +[Geometry] +FrameSupp0,0=165 +TopWindow0=1168x947+72+19 +FrameSupp0,1=165 +FrameSupp0,2=165 +[Help] +default=te_guide +[Plugins] +userLanguages= +[Search] +historyMax=4 +[LexParser.LexVHDL'93] +[LexParser.LexPSL] +[LexParser.LexVHDL2008] diff --git a/Prefs/hds.hdp b/Prefs/hds.hdp new file mode 100644 index 0000000..470c3b6 --- /dev/null +++ b/Prefs/hds.hdp @@ -0,0 +1,17 @@ +[DesignChecker] +VHD_test = $HDS_PROJECT_DIR\..\VHD_test\designcheck +[ModelSim] +VHD = $SCRATCH_DIR/Exam/VHD/work +VHD_test = $SCRATCH_DIR/Exam/VHD_test/work +[hdl] +VHD = $HDS_PROJECT_DIR/../VHD/hdl +VHD_test = $HDS_PROJECT_DIR/../VHD_test/hdl +[hds] +VHD = $HDS_PROJECT_DIR/../VHD/hds +VHD_test = $HDS_PROJECT_DIR/../VHD_test/hds +[library_type] +ieee = standard +moduleware = standard +std = standard +[shared] +others = $HDS_TEAM_HOME/shared.hdp diff --git a/Prefs/hds.info/pll.lpf b/Prefs/hds.info/pll.lpf new file mode 100644 index 0000000..df0b0f3 --- /dev/null +++ b/Prefs/hds.info/pll.lpf @@ -0,0 +1,3 @@ +version "1.0" +pathExcludes [ +] diff --git a/Prefs/hds.info/xilinx_xc3s200an.lpf b/Prefs/hds.info/xilinx_xc3s200an.lpf new file mode 100644 index 0000000..df0b0f3 --- /dev/null +++ b/Prefs/hds.info/xilinx_xc3s200an.lpf @@ -0,0 +1,3 @@ +version "1.0" +pathExcludes [ +] diff --git a/Prefs/hds.info/xilinxcorelib.lpf b/Prefs/hds.info/xilinxcorelib.lpf new file mode 100644 index 0000000..df0b0f3 --- /dev/null +++ b/Prefs/hds.info/xilinxcorelib.lpf @@ -0,0 +1,3 @@ +version "1.0" +pathExcludes [ +] diff --git a/Prefs/hds_team/shared.hdp b/Prefs/hds_team/shared.hdp new file mode 100644 index 0000000..3864365 --- /dev/null +++ b/Prefs/hds_team/shared.hdp @@ -0,0 +1,15 @@ +[hdl] +ieee = $HDS_HOME/hdl_libs/ieee/hdl +std = $HDS_HOME/hdl_libs/std/hdl +vital2000 = $HDS_HOME/hdl_libs/vital2000/hdl +[hds] +ieee = $HDS_HOME/hdl_libs/ieee/hds +std = $HDS_HOME/hdl_libs/std/hds +vital2000 = $HDS_HOME/hdl_libs/vital2000/hds +[hds_settings] +project_description = The standard HDS shared project +version = 2 +[library_type] +ieee = standard +std = standard +vital2000 = standard diff --git a/Prefs/hds_team/v2009.2/hds_team_prefs b/Prefs/hds_team/v2009.2/hds_team_prefs new file mode 100644 index 0000000..bc95c6a --- /dev/null +++ b/Prefs/hds_team/v2009.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "7.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2009.2/title_block.tmpl b/Prefs/hds_team/v2009.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2009.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/Prefs/hds_team/v2015.2/hds_team_prefs b/Prefs/hds_team/v2015.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2015.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2015.2/title_block.tmpl b/Prefs/hds_team/v2015.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2015.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/Prefs/hds_team/v2018.1/hds_team_prefs b/Prefs/hds_team/v2018.1/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2018.1/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2018.1/title_block.tmpl b/Prefs/hds_team/v2018.1/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2018.1/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,66000,39000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,66000,37800,67000" +st " +Project:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,68000,35000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,68000,27800,69000" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,68000,18000,69000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,68000,15900,69000" +st " +Title:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "35000,67000,55000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "35200,67200,44000,68200" +st " +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*6 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "39000,66000,55000,67000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "39200,66000,48900,67000" +st "%project_name" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*7 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,66000,35000,68000" +) +text (MLText +va (VaSet +fg "32768,0,0" +) +xt "19950,66350,29050,67650" +st " +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,69000,18000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,69000,15900,70000" +st " +Path:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "14000,70000,18000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "14200,70000,16500,71000" +st " +Edited:" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,69000,35000,70000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,69000,25400,70000" +st " +%library/%unit/%view" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "14000,66000,55000,71000" +) +) +) diff --git a/Prefs/hds_team/v2019.2/hds_team_prefs b/Prefs/hds_team/v2019.2/hds_team_prefs new file mode 100644 index 0000000..6eeab5f --- /dev/null +++ b/Prefs/hds_team/v2019.2/hds_team_prefs @@ -0,0 +1,55 @@ +version "8.0" +RenoirTeamPreferences [ +(BaseTeamPreferences +version "1.1" +verConcat 0 +ttDGProps [ +] +fcDGProps [ +] +smDGProps [ +] +asmDGProps [ +] +bdDGProps [ +] +syDGProps [ +] +) +(VersionControlTeamPreferences +version "1.1" +VMPlugin "" +VMRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMRcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hds_vm" +VMRcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/%(library)/hdl_vm" +VMCvsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCvsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMCVSmkIIHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMCVSmkIIHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository" +VMVssHdsRepository "$/hds_scratch/hds_repository/%(library)/hds_vm" +VMVssHdlRepository "$/hds_scratch/hds_repository/%(library)/hdl_vm" +VMDsHdsRepository "sync://:/hds_scratch/hds_repository/hds_vm" +VMDsHdlRepository "sync://:/hds_scratch/hds_repository/hdl_vm" +VMPvcsHdsRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hds_vm" +VMPvcsHdlRepository "$HDS_HOME/examples/hds_scratch/hds_repository/hdl_vm" +VMSvnHdlRepository "" +VMDefaultView 1 +VMCurrentDesignHierarchyOnly 0 +VMUserData 1 +VMGeneratedHDL 0 +VMVerboseMode 0 +VMAlwaysEmpty 0 +VMSetTZ 1 +VMSymbol 1 +VMCurrentDesignHierarchy 0 +VMMultipleRepositoryMode 0 +VMSnapshotViewMode 0 +backupNameClashes 1 +clearCaseMaster 0 +) +(CustomizeTeamPreferences +version "1.1" +FileTypes [ +] +) +] diff --git a/Prefs/hds_team/v2019.2/title_block.tmpl b/Prefs/hds_team/v2019.2/title_block.tmpl new file mode 100644 index 0000000..12ef16a --- /dev/null +++ b/Prefs/hds_team/v2019.2/title_block.tmpl @@ -0,0 +1,273 @@ +version "4.1" +TitleBlockTemplateRegistrar (TitleBlockTemplate +TitleBlock (Grouping +optionalChildren [ +*1 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "18000,70000,35000,71000" +) +text (MLText +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +font "Arial,8,0" +) +xt "18200,70000,27100,71000" +st " +by %user on %dd %month %year" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*2 (CommentText +shape (Rectangle +sl 0 +va (VaSet +vasetType 1 +fg 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+commentTextShapeVaSet (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +requirementTextFontVaSet (VaSet +fg "0,0,32768" +font "courier,8,0" +) +gridVisible 1 +gridSnapping 1 +gridHorizSpacing 1000 +gridVertSpacing 1000 +gridHorizShown 1 +gridVertShown 1 +gridColor "26368,26368,26368" +diagramBackground "65535,65535,65535" +CompDirLabelVaSet (VaSet +font "courier,8,1" +) +CompDirValueVaSet (VaSet +font "courier,8,0" +) +defaultPanelName "Panel0" +panelShapeVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 3 +) +panelTextVaSet (VaSet +font "courier,8,1" +) +bodyVaSet (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +cptPortVaSet (VaSet +vasetType 1 +fg "0,65535,0" +) +cptPortBufferVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +bodyFontVaSet (VaSet +font "courier,8,1" +) +cptPortFontVaSet (VaSet +font "courier,8,0" +) +genericInterfaceFontVaSet (VaSet +font "courier,8,0" +) +portRowVaSet (VaSet +vasetType 4 +) +groupRowVaSet (VaSet +vasetType 4 +bg "39936,56832,65280" +) +headCellVaSet (VaSet +vasetType 4 +bg "49152,49152,49152" +) +gridVaSet (VaSet +vasetType 4 +fg "49152,49152,49152" +bg "0,49152,49152" +) +propColVaSet (VaSet +vasetType 4 +bg "0,49152,49152" +) +visibilityPrefs [ +(StringToBool +display "Compiler Directives (Verilog)" +status 1 +) +(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk new file mode 100644 index 0000000..ddccec1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/actel_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Actel Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_actel.bmp" +hasBitmap 1 +tooltip "Invokes the Actel Designer Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ActelPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk b/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk new file mode 100644 index 0000000..4ee8298 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/altera_megawizard.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera MegaWizard" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alteramegawizard.bmp" +hasBitmap 1 +tooltip "Creates Altera Megawizard components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraMegaWizard" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk b/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk new file mode 100644 index 0000000..2fca504 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/altera_sopc_builder.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera SOPC Builder" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alterasopc.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Altera SOPC Builder" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraSOPC" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk b/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk new file mode 100644 index 0000000..507d61a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/c_c_wrapper_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "C/C++ Wrapper Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_cwrapper.bmp" +hasBitmap 1 +tooltip "Generates an HDL wrapper for a C/C++ view" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"CWrapperGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk b/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk new file mode 100644 index 0000000..a955548 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/designchecker.tsk @@ -0,0 +1,43 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..2d662f3 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk b/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk new file mode 100644 index 0000000..eedb81a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/fpga_library_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Library Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgalibcomp.bmp" +hasBitmap 1 +tooltip "Compiles Vendor Simulation Libraries" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaLibsComp" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk b/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..ed14e8a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk b/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk new file mode 100644 index 0000000..d248a15 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..58dc665 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk new file mode 100644 index 0000000..e605743 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/lattice_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Lattice Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"LatticePARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..5bb0d55 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..9e6f746 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "/usr/opt/Modelsim/modeltech/bin" +) +(preferedMap +preferedEnum 2 +preferedSetting "MODEL_SIM" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f990623 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk new file mode 100644 index 0000000..870c36e --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Runs Precision data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/PrecisionSynthesisCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Does data preparation for Precision Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"PrecisionSynthesisDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Invokes the Precision Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"PrecisionSynthesisInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk new file mode 100644 index 0000000..4de40b1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/precision_synthesis_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Precision Synthesis flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 1 +) +(preferedMap +preferedEnum 3 +preferedSetting "Precision" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Precision Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Precision Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk new file mode 100644 index 0000000..e0b11cc --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus II Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus II Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk new file mode 100644 index 0000000..20f9ba1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_ii_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus II Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus II Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..fe87958 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk b/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk new file mode 100644 index 0000000..7ca7317 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/quartus_programmer.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Programmer" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_programmer.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Programmer tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPGMInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk b/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk new file mode 100644 index 0000000..c2c17d0 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk b/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk new file mode 100644 index 0000000..1b0b2e6 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/systemverilog_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SystemVerilog Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SystemVerilog Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk new file mode 100644 index 0000000..0cd368a --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_core_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx CORE Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxcoregen.bmp" +hasBitmap 1 +tooltip "Creates Xilinx ISE CORE Generator components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxCoregen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_fpga_configuration_impact.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_fpga_configuration_impact.tsk new file mode 100644 index 0000000..f7972d7 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_fpga_configuration_impact.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx FPGA Configuration (iMPACT)" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_impact.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE FPGA Configuration Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ImpactInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk new file mode 100644 index 0000000..7cda96f --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_import.bmp" +hasBitmap 1 +tooltip "Import Existing Xilinx ISE Project into HDS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..9342cf7 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..02e6f53 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..73d7c51 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx ISE Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..7105fe5 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..62c6379 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..535e3ca --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) (%(unit)) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..b30dd71 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(unit).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) (%(unit)) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2015.2/templates/registered_views/c_file.c b/Prefs/hds_user-linux/v2015.2/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user-linux/v2015.2/templates/registered_views/class.cpp b/Prefs/hds_user-linux/v2015.2/templates/registered_views/class.cpp new file mode 100644 index 0000000..41eac84 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/registered_views/class.cpp @@ -0,0 +1,12 @@ +FILE_NAMING_RULE: afile.cpp +DESCRIPTION_START +This is the default template used for the creation of C++ files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_Class/class.svh b/Prefs/hds_user-linux/v2015.2/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_Interface/interface.sv b/Prefs/hds_user-linux/v2015.2/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_Package/package.sv b/Prefs/hds_user-linux/v2015.2/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_Program/program.sv b/Prefs/hds_user-linux/v2015.2/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_include/verilog_include.v b/Prefs/hds_user-linux/v2015.2/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2015.2/templates/verilog_module/module.v b/Prefs/hds_user-linux/v2015.2/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user-linux/v2015.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2016.1/hds_user_prefs b/Prefs/hds_user-linux/v2016.1/hds_user_prefs new file mode 100644 index 0000000..99f15ae --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/hds_user_prefs @@ -0,0 +1,5259 @@ +version "46.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "sublime '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "gEdit" +second "gedit +%(l) '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second 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+"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"TabularWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +expertUser 0 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +ActelLibraries 1 +LatticeLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Desktop/SEm/Cours/SEm_exams/HDS/my_project/my_project.hdp" +"/home/francois/Desktop/SEm/Cours/SEm_exams/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_exams/Prefs/hds.hdp" +"/media/student/Athena-data/francois/Documents/HEVs/SEm/SEm_exams/Prefs/hds.hdp" +] +libMappingsRootDir "" +teamLibMappingsRootDir "" +defaultUserLibRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.std_logic_arith.all; +" +defaultVerilogPackages "" +defaultFont "courier,10,0" +tableFont "courier,10,0" +pageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +pageSizes [ +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPageSetupInfo (PageSetupInfo +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +exportStdIncludeRefs 1 +exportStdPackageRefs 1 +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ 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+userVariables [ +(pair +first "task_DesignCompilerPath" +second "" +) +(pair +first "task_LeonardoPath" +second "" +) +(pair +first "task_ModelSimPath" +second "/usr/opt/Modelsim/modeltech/bin" +) +(pair +first "task_NC-SimPath" +second "" +) +(pair +first "task_PrecisionRTLPath" +second "" +) +(pair +first "task_QuestaSimPath" +second "" +) +(pair +first "task_VCSPath" +second "" +) +] +tasksOrder [ +"USER:Generate" +"USER:DesignChecker" +"USER:DesignChecker Flow" +"USER:Register Assistant" +"USER:Quartus II Synthesis" +"USER:Quartus II Synthesis Flow" +"USER:Quartus Place and Route" +"USER:Quartus Programmer" +"USER:Altera SOPC Builder" +"USER:Altera MegaWizard" +"USER:Xilinx Synthesis Tool" +"USER:Xilinx Synthesis Tool Flow" +"USER:Xilinx Place and Route" +"USER:Xilinx FPGA Configuration (iMPACT)" +"USER:Xilinx Platform Studio" +"USER:Xilinx CORE Generator" +"USER:Xilinx Import" +"USER:Xilinx Vivado Flow" +"USER:Actel Place and Route" +"USER:Lattice Place and Route" +"USER:FPGA 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"$HDS_HOME/resources/bitmaps/tools/tool_alteramegawizard.bmp" +hasBitmap 1 +tooltip "Creates Altera Megawizard components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraMegaWizard" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/altera_sopc_builder.tsk b/Prefs/hds_user-linux/v2016.1/tasks/altera_sopc_builder.tsk new file mode 100644 index 0000000..2fca504 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/altera_sopc_builder.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera SOPC Builder" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alterasopc.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Altera SOPC Builder" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraSOPC" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/c_c_wrapper_generator.tsk b/Prefs/hds_user-linux/v2016.1/tasks/c_c_wrapper_generator.tsk new file mode 100644 index 0000000..507d61a --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/c_c_wrapper_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "C/C++ Wrapper Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_cwrapper.bmp" +hasBitmap 1 +tooltip "Generates an HDL wrapper for a C/C++ view" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"CWrapperGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/designchecker.tsk b/Prefs/hds_user-linux/v2016.1/tasks/designchecker.tsk new file mode 100644 index 0000000..a955548 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/designchecker.tsk @@ -0,0 +1,43 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/designchecker_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..2d662f3 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/fpga_library_compile.tsk b/Prefs/hds_user-linux/v2016.1/tasks/fpga_library_compile.tsk new file mode 100644 index 0000000..eedb81a --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/fpga_library_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Library Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgalibcomp.bmp" +hasBitmap 1 +tooltip "Compiles Vendor Simulation Libraries" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaLibsComp" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/fpga_technology_setup.tsk b/Prefs/hds_user-linux/v2016.1/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..ed14e8a --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/generate.tsk b/Prefs/hds_user-linux/v2016.1/tasks/generate.tsk new file mode 100644 index 0000000..d248a15 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/i_o_design_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..58dc665 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/lattice_place_and_route.tsk b/Prefs/hds_user-linux/v2016.1/tasks/lattice_place_and_route.tsk new file mode 100644 index 0000000..e605743 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/lattice_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Lattice Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"LatticePARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/modelsim_compile.tsk b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..5bb0d55 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/modelsim_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..9e6f746 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "/usr/opt/Modelsim/modeltech/bin" +) +(preferedMap +preferedEnum 2 +preferedSetting "MODEL_SIM" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/modelsim_simulate.tsk b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f990623 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis.tsk b/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis.tsk new file mode 100644 index 0000000..870c36e --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Runs Precision data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/PrecisionSynthesisCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Does data preparation for Precision Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"PrecisionSynthesisDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Invokes the Precision Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"PrecisionSynthesisInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis_flow.tsk new file mode 100644 index 0000000..4de40b1 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/precision_synthesis_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Precision Synthesis flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 1 +) +(preferedMap +preferedEnum 3 +preferedSetting "Precision" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Precision Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Precision Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis.tsk b/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis.tsk new file mode 100644 index 0000000..e0b11cc --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus II Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus II Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus II Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis_flow.tsk new file mode 100644 index 0000000..20f9ba1 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/quartus_ii_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus II Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus II Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus II Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/quartus_place_and_route.tsk b/Prefs/hds_user-linux/v2016.1/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..fe87958 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/quartus_programmer.tsk b/Prefs/hds_user-linux/v2016.1/tasks/quartus_programmer.tsk new file mode 100644 index 0000000..7ca7317 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/quartus_programmer.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Programmer" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_programmer.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Programmer tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPGMInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/register_assistant.tsk b/Prefs/hds_user-linux/v2016.1/tasks/register_assistant.tsk new file mode 100644 index 0000000..c2c17d0 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/svassistant_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/svassistant_flow.tsk new file mode 100644 index 0000000..466248c --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/svassistant_flow.tsk @@ -0,0 +1,78 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "SVAssistant Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SVAssistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_core_generator.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_core_generator.tsk new file mode 100644 index 0000000..0cd368a --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_core_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx CORE Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxcoregen.bmp" +hasBitmap 1 +tooltip "Creates Xilinx ISE CORE Generator components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxCoregen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_fpga_configuration_impact.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_fpga_configuration_impact.tsk new file mode 100644 index 0000000..f7972d7 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_fpga_configuration_impact.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx FPGA Configuration (iMPACT)" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_impact.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE FPGA Configuration Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ImpactInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_import.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_import.tsk new file mode 100644 index 0000000..7cda96f --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_import.bmp" +hasBitmap 1 +tooltip "Import Existing Xilinx ISE Project into HDS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..9342cf7 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..02e6f53 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..73d7c51 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx ISE Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..7105fe5 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..62c6379 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..535e3ca --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) (%(unit)) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..b30dd71 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(unit).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) (%(unit)) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2016.1/templates/registered_views/c_file.c b/Prefs/hds_user-linux/v2016.1/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user-linux/v2016.1/templates/registered_views/class.cpp b/Prefs/hds_user-linux/v2016.1/templates/registered_views/class.cpp new file mode 100644 index 0000000..41eac84 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/registered_views/class.cpp @@ -0,0 +1,12 @@ +FILE_NAMING_RULE: afile.cpp +DESCRIPTION_START +This is the default template used for the creation of C++ files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_Class/class.svh b/Prefs/hds_user-linux/v2016.1/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_Interface/interface.sv b/Prefs/hds_user-linux/v2016.1/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_Package/package.sv b/Prefs/hds_user-linux/v2016.1/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_Program/program.sv b/Prefs/hds_user-linux/v2016.1/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_include/verilog_include.v b/Prefs/hds_user-linux/v2016.1/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2016.1/templates/verilog_module/module.v b/Prefs/hds_user-linux/v2016.1/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_combined/combined.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_entity/entity.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user-linux/v2016.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2018.1/hds_user_prefs b/Prefs/hds_user-linux/v2018.1/hds_user_prefs new file mode 100644 index 0000000..4195c2d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/hds_user_prefs @@ -0,0 +1,5492 @@ +version "48.1" +SaPreferences [ +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edn" +"edf" +"edif" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "NEdit" +second "nedit +%(l) '%(p)'" +) +(pair +first "Sublime" +second "subl '%(p)':%(l)" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "gEdit" +second "gedit +%(l) '%(p)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "NEdit" +second "nedit -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "notepad.exe \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Builtin" +win32DefaultViewer "Builtin" +unixDefaultEditor "Sublime" +unixDefaultViewer "Builtin" +defaultVerilogDialect 5 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +"vhg" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:FormatText" +"SymbolWindow:FormatText" +"AsmWindow:FormatText" +"FcWindow:FormatText" +"StdWindow:FormatText" +"BdWindow:CommentGraphics" +"SymbolWindow:CommentGraphics" +"AsmWindow:CommentGraphics" +"StdWindow:CommentGraphics" +"FcWindow:CommentGraphics" +"BdWindow:Appearance" +"SymbolWindow:Appearance" +"AsmWindow:Appearance" +"StdWindow:Appearance" +"FcWindow:Appearance" +"FcWindow:Appearance" +"StdTabWindow:Appearance" +"FcTabWindow:Appearance" +"AsmTabWindow:Appearance" +"BdTabWindow:Appearance" +"TtTabWindow:Appearance" +"BdWindow:ArrangeObject" +"SymbolWindow:ArrangeObject" +"AsmWindow:ArrangeObject" +"StdWindow:ArrangeObject" +"FcWindow:ArrangeObject" +] +seperateElseBegincheck 1 +expertUser 0 +ASICDesigner 1 +FPGADesigner 1 +AlteraLibraries 1 +XilinxLibraries 1 +ActelLibraries 1 +LatticeLibraries 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "/tmp" +projectPaths [ +"/home/francois/Desktop/SEm/Cours/SEm_exams/HDS/my_project/my_project.hdp" +"/home/francois/Desktop/SEm/Cours/SEm_exams/Prefs/hds.hdp" +"/home/francois/Documents/HEVs/SEm/SEm_exams/Prefs/hds.hdp" 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+(StringToBool +display "Declarations" +status 1 +) +(StringToBool +display "Package List (VHDL)" +status 1 +) +] +cptPortInName "In0" +cptPortOutName "Out0" +cptPortInOutName "InOut0" +cptPortBufferName "Buffer0" +groupName "Group0" +cptPortVhdlType "std_logic_vector" +cptPortVerilogType "wire" +cptPortVhdlBounds "(15 DOWNTO 0)" +cptPortVerilogLb "15" +cptPortVerilogRb "0" +cptPortVhdlConstraintType 0 +DeclarativeBlockLabelText "Declarations" +DeclarativeBlockLabelVaSet (VaSet +font "courier,8,1" +) +DeclarativeBlockValueVaSet (VaSet +font "courier,8,0" +) +DeclarativeBlockPortVaSet (VaSet +font "courier,8,0" +) +order 0 +editSignalScope 4 +showUpdateWhereUsedPrompt 0 +) +] diff --git a/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk new file mode 100644 index 0000000..ddccec1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/actel_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Actel Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_actel.bmp" +hasBitmap 1 +tooltip "Invokes the Actel Designer Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ActelPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk b/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk new file mode 100644 index 0000000..4ee8298 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/altera_megawizard.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera MegaWizard" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alteramegawizard.bmp" +hasBitmap 1 +tooltip "Creates Altera Megawizard components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraMegaWizard" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk b/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk new file mode 100644 index 0000000..2fca504 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/altera_sopc_builder.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Altera SOPC Builder" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_alterasopc.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Altera SOPC Builder" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"AlteraSOPC" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk b/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk new file mode 100644 index 0000000..507d61a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/c_c_wrapper_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "C/C++ Wrapper Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_cwrapper.bmp" +hasBitmap 1 +tooltip "Generates an HDL wrapper for a C/C++ view" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"CWrapperGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk b/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk new file mode 100644 index 0000000..a955548 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/designchecker.tsk @@ -0,0 +1,43 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..2d662f3 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk b/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk new file mode 100644 index 0000000..eedb81a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/fpga_library_compile.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Library Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgalibcomp.bmp" +hasBitmap 1 +tooltip "Compiles Vendor Simulation Libraries" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaLibsComp" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk b/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..ed14e8a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk b/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk new file mode 100644 index 0000000..d248a15 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/generate.tsk @@ -0,0 +1,41 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..58dc665 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk new file mode 100644 index 0000000..e605743 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/lattice_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Lattice Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_lattice.bmp" +hasBitmap 1 +tooltip "Invokes the Lattice Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"LatticePARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..5bb0d55 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..9e6f746 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "/usr/opt/Modelsim/modeltech/bin" +) +(preferedMap +preferedEnum 2 +preferedSetting "MODEL_SIM" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..f990623 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/modelsim_simulate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk new file mode 100644 index 0000000..870c36e --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis.tsk @@ -0,0 +1,101 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Runs Precision data preparation and invokes tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"$HDS_HOME/resources/tcl/plugins/dialogs/PrecisionSynthesisCombinedDlg.tbc" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Does data preparation for Precision Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"PrecisionSynthesisDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Precision Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Invokes the Precision Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"PrecisionSynthesisInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk new file mode 100644 index 0000000..4de40b1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/precision_synthesis_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Precision Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_precision.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Precision Synthesis flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 1 +) +(preferedMap +preferedEnum 3 +preferedSetting "Precision" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Precision Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Precision Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..fe87958 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk new file mode 100644 index 0000000..232d299 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_prime_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Prime Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_altera_quartus_prime.bmp" +hasBitmap 1 +tooltip "Import IP variations from Quartus Prime" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QuartusPrimeImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk new file mode 100644 index 0000000..7ca7317 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_programmer.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Programmer" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_programmer.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus II Programmer tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPGMInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk new file mode 100644 index 0000000..a40412d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk new file mode 100644 index 0000000..0210e0e --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus Synthesis" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk new file mode 100644 index 0000000..cb4a2bc --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_invoke.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk new file mode 100644 index 0000000..007bff2 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/quartus_synthesis_prepare_data.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk b/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk new file mode 100644 index 0000000..c2c17d0 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk new file mode 100644 index 0000000..466248c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/svassistant_flow.tsk @@ -0,0 +1,78 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "SVAssistant Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SVAssistant" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk new file mode 100644 index 0000000..0cd368a --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_core_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx CORE Generator" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxcoregen.bmp" +hasBitmap 1 +tooltip "Creates Xilinx ISE CORE Generator components" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxCoregen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_fpga_configuration_impact.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_fpga_configuration_impact.tsk new file mode 100644 index 0000000..f7972d7 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_fpga_configuration_impact.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx FPGA Configuration (iMPACT)" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_impact.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE FPGA Configuration Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ImpactInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk new file mode 100644 index 0000000..7cda96f --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Import" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_import.bmp" +hasBitmap 1 +tooltip "Import Existing Xilinx ISE Project into HDS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..9342cf7 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..02e6f53 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..73d7c51 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx ISE Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx ISE Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..7105fe5 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..62c6379 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME/resources/bitmaps/tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..535e3ca --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) (%(unit)) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..b30dd71 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,20 @@ +FILE_NAMING_RULE: %(unit).psl +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) (%(unit)) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user-linux/v2018.1/templates/registered_views/c_file.c b/Prefs/hds_user-linux/v2018.1/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user-linux/v2018.1/templates/registered_views/class.cpp b/Prefs/hds_user-linux/v2018.1/templates/registered_views/class.cpp new file mode 100644 index 0000000..41eac84 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/registered_views/class.cpp @@ -0,0 +1,12 @@ +FILE_NAMING_RULE: afile.cpp +DESCRIPTION_START +This is the default template used for the creation of C++ files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_Class/class.svh b/Prefs/hds_user-linux/v2018.1/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_Interface/interface.sv b/Prefs/hds_user-linux/v2018.1/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_Package/package.sv b/Prefs/hds_user-linux/v2018.1/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_Program/program.sv b/Prefs/hds_user-linux/v2018.1/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_include/verilog_include.v b/Prefs/hds_user-linux/v2018.1/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user-linux/v2018.1/templates/verilog_module/module.v b/Prefs/hds_user-linux/v2018.1/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user-linux/v2018.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2005.1/hds_user_prefs b/Prefs/hds_user/v2005.1/hds_user_prefs new file mode 100644 index 0000000..1dc7962 --- /dev/null +++ b/Prefs/hds_user/v2005.1/hds_user_prefs @@ -0,0 +1,4256 @@ +version "22.1" +SaPreferences [ +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 0 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(CompilationPreferences +) +(GenerationPreferences +automaticTypeConversion 0 +genPackages 1 +genDependants 0 +enableCustomCodeGen 0 +useDefaultCustomCodeGenScript 1 +verilogSpecViewHeaderString "// hds header_start +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// hds header_end +%(moduleBody) +// hds interface_end +// ### Please start your Verilog code here ### + +endmodule" +vhdlConfigsName "%(unit)_config" +vhdlConfigsFileNameTemplate "%(config)" +vhdlConfigsNameTemplate "%(unit)_config" +separateEntity 1 +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edif" +"edn" +"edf" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)' -f vc-toggle-read-only" +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first 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+"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2005.1/tasks/fpga_technology_setup.tsk b/Prefs/hds_user/v2005.1/tasks/fpga_technology_setup.tsk new file mode 100644 index 0000000..dfd8d31 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/fpga_technology_setup.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "FPGA Technology Setup" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_fpgatechsetup.bmp" +hasBitmap 1 +tooltip "Sets the FPGA technology" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"FpgaTechSetup" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2005.1/tasks/generate.tsk b/Prefs/hds_user/v2005.1/tasks/generate.tsk new file mode 100644 index 0000000..7d15ecb --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/generate.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2005.1/tasks/i_o_design_flow.tsk b/Prefs/hds_user/v2005.1/tasks/i_o_design_flow.tsk new file mode 100644 index 0000000..73749b2 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/i_o_design_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "I/O Design Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Generate and runs BoardLink Pro to define pin assignments" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "I/O Design" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_blpro.bmp" +hasBitmap 1 +tooltip "Runs BoardLink Pro to define pin assignments" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"BoardLinkPro" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/migrated_simulation_flow.tsk b/Prefs/hds_user/v2005.1/tasks/migrated_simulation_flow.tsk new file mode 100644 index 0000000..43da570 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/migrated_simulation_flow.tsk @@ -0,0 +1,110 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Migrated Simulation Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_modelsim.bmp" +hasBitmap 1 +tooltip "Migrated Simulation Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/migrated_synthesis_flow.tsk b/Prefs/hds_user/v2005.1/tasks/migrated_synthesis_flow.tsk new file mode 100644 index 0000000..5969c5f --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/migrated_synthesis_flow.tsk @@ -0,0 +1,110 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Migrated Synthesis Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_leonardo.bmp" +hasBitmap 1 +tooltip "Migrated Synthesis Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Prepare Data" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Does data preparation for LeonardoSpectrum" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"SpectrumDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "LeonardoSpectrum Synthesis Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_leonardo.bmp" +hasBitmap 1 +tooltip "Invokes the LeonardoSpectrum Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"SpectrumInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/quartus_place_and_route.tsk b/Prefs/hds_user/v2005.1/tasks/quartus_place_and_route.tsk new file mode 100644 index 0000000..1f15215 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/quartus_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Place and Route" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_altera_quartus.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus QIS Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2005.1/tasks/quartus_qis.tsk b/Prefs/hds_user/v2005.1/tasks/quartus_qis.tsk new file mode 100644 index 0000000..20013f5 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/quartus_qis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus QIS" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus QIS data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus QIS Prepare Data" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus QIS" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus QIS Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus QIS tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/quartus_qis_flow.tsk b/Prefs/hds_user/v2005.1/tasks/quartus_qis_flow.tsk new file mode 100644 index 0000000..b38423f --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/quartus_qis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus QIS Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus QIS" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus QIS" +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/xilinx_place_and_route.tsk b/Prefs/hds_user/v2005.1/tasks/xilinx_place_and_route.tsk new file mode 100644 index 0000000..4ae1ca3 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/xilinx_place_and_route.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Place and Route" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx Place and Route tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ISEPARInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2005.1/tasks/xilinx_platform_studio.tsk b/Prefs/hds_user/v2005.1/tasks/xilinx_platform_studio.tsk new file mode 100644 index 0000000..0653735 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/xilinx_platform_studio.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Platform Studio" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinxplatstudio.bmp" +hasBitmap 1 +tooltip "Invokes and imports files from Xilinx Platform Studio" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XilinxPlatStudio" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool.tsk b/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool.tsk new file mode 100644 index 0000000..746f51d --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Xilinx Synthesis Tool data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Prepare Data" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Xilinx Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XSTDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "XST Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes Xilinx Synthesis Tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"XSTInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool_flow.tsk b/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool_flow.tsk new file mode 100644 index 0000000..d0aa470 --- /dev/null +++ b/Prefs/hds_user/v2005.1/tasks/xilinx_synthesis_tool_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Synthesis Tool Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Xilinx Synthesis Tool flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Xilinx Synthesis Tool" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Xilinx Synthesis Tool" +) +] +) diff --git a/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..c21814e --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) ([%(unit)]) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..9580561 --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) ([%(unit)]) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2005.1/templates/registered_views/c_file.c b/Prefs/hds_user/v2005.1/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user/v2005.1/templates/registered_views/sc_source.cpp b/Prefs/hds_user/v2005.1/templates/registered_views/sc_source.cpp new file mode 100644 index 0000000..24e5d3a --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/registered_views/sc_source.cpp @@ -0,0 +1,59 @@ +FILE_NAMING_RULE: %(unit).cpp +DESCRIPTION_START +This is the default template used for the creation of SystemC source files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +// Filename: %(view) + +#include "systemc.h" +//#include "%(unit).h" + +// Method body for %(unit)_action +void %(unit)::%(unit)_action() +{ + +} + +SC_MODULE_EXPORT(%(unit)); + +// +// It is recommended that the SC_MODULE code is placed in a separate header file +// If required, you can copy/paste the following template code into a header file +// called %(unit).h and uncomment the #include statement above. + +//#ifndef %(unit)_H +//#define %(unit)_H +// +//#include "systemc.h" +// +//SC_MODULE (%(unit)) +//{ +// // Ports +// sc_in clk, +// sc_in in2; +// sc_out out1; +// +// // Methods +// void %(unit)_action(); +// +// // %(unit) Constructor +// SC_CTOR(%(unit)) +// : +// { +// SC_THREAD(%(unit)_action); +// sensitive << clk.pos(); +// } +// +// // %(unit) Destructor +// ~%(unit) +// { +// } +// +//}; diff --git a/Prefs/hds_user/v2005.1/templates/verilog_include/verilog_include.v b/Prefs/hds_user/v2005.1/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user/v2005.1/templates/verilog_module/module.v b/Prefs/hds_user/v2005.1/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2005.1/templates/verilog_module/module_migrated.v b/Prefs/hds_user/v2005.1/templates/verilog_module/module_migrated.v new file mode 100644 index 0000000..9dd72b5 --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/verilog_module/module_migrated.v @@ -0,0 +1,22 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +Template for the creation of Verilog Module files. +This template was migrated from header preferences created in a +previous version of HDL Designer. +DESCRIPTION_END +// +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// +%(moduleBody) +// +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2005.1/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2005.1/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2005.1/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2007.1a/hds_user_prefs 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+componentBrowserWidth 336 +componentBrowserHeight 612 +componentBrowserLibraryNames [ +"Board" +"moduleware" +"cypress_usb_lib" +] +) +] diff --git a/Prefs/hds_user/v2007.1a/tasks/concatenate_hdl.tsk b/Prefs/hds_user/v2007.1a/tasks/concatenate_hdl.tsk new file mode 100644 index 0000000..295c67f --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/concatenate_hdl.tsk @@ -0,0 +1,54 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/designchecker.tsk b/Prefs/hds_user/v2007.1a/tasks/designchecker.tsk new file mode 100644 index 0000000..c69f51e --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/designchecker.tsk @@ -0,0 +1,46 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/designchecker_flow.tsk b/Prefs/hds_user/v2007.1a/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..9a40217 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user/v2007.1a/tasks/designwave_hdl_generator.tsk b/Prefs/hds_user/v2007.1a/tasks/designwave_hdl_generator.tsk new file mode 100644 index 0000000..37bc2d7 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/designwave_hdl_generator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignWave HDL Generator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_eswave_hdl_generation.bmp" +hasBitmap 1 +tooltip "DesignWave HDL Generator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"EZWaveGen" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/designwave_invoke.tsk b/Prefs/hds_user/v2007.1a/tasks/designwave_invoke.tsk new file mode 100644 index 0000000..3e61264 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/designwave_invoke.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignWave Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_eswave.bmp" +hasBitmap 1 +tooltip "DesignWave Invoke" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"RunEZWave" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/generate.tsk b/Prefs/hds_user/v2007.1a/tasks/generate.tsk new file mode 100644 index 0000000..0e4a794 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/generate.tsk @@ -0,0 +1,46 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"generateAlways" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2007.1a/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..e49dbf3 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +"peSe" +"EE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/modelsim_flow.tsk b/Prefs/hds_user/v2007.1a/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..fa659e3 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "C:\\EDA\\Modelsim\\win32" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim SE 6.3g" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2007.1a/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2007.1a/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..fd63b17 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/modelsim_simulate.tsk @@ -0,0 +1,84 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"wave.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"ps" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"Simulate" +"0" +"excludePSL" +"0" +"exepath" +"%task_ModelSimPath" +"saveReplayScript" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/synthesis_flow.tsk b/Prefs/hds_user/v2007.1a/tasks/synthesis_flow.tsk new file mode 100644 index 0000000..505e20d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/synthesis_flow.tsk @@ -0,0 +1,134 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Synthesis Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_leonardo.bmp" +hasBitmap 1 +tooltip "Single file VHDL Synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libs" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl $HDS_PROJECT_DIR/../Board/concat/%(concat_file).vhd $HDS_PROJECT_DIR/../Board/concat/%(concat_file)_trimmed.vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"c:\\eda\\hds2007.1a\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2007.1a/tasks/trim_libraries.tsk b/Prefs/hds_user/v2007.1a/tasks/trim_libraries.tsk new file mode 100644 index 0000000..6587987 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/trim_libraries.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl %(concat_file).vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"%(library_downstream_Concatenation)" +"promptForRunSettings" +"0" +"runnableObject" +"C:\\eda\\hds\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2007.1a/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2007.1a/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..218f68d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"%(task_ISEPath)\\%(concat_file).ise" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"C:\\eda\\Xilinx\\ISE\\bin\\nt\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..c21814e --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) ([%(unit)]) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..9580561 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) ([%(unit)]) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2007.1a/templates/registered_views/c_file.c b/Prefs/hds_user/v2007.1a/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user/v2007.1a/templates/registered_views/sc_source.cpp b/Prefs/hds_user/v2007.1a/templates/registered_views/sc_source.cpp new file mode 100644 index 0000000..24e5d3a --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/registered_views/sc_source.cpp @@ -0,0 +1,59 @@ +FILE_NAMING_RULE: %(unit).cpp +DESCRIPTION_START +This is the default template used for the creation of SystemC source files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +// Filename: %(view) + +#include "systemc.h" +//#include "%(unit).h" + +// Method body for %(unit)_action +void %(unit)::%(unit)_action() +{ + +} + +SC_MODULE_EXPORT(%(unit)); + +// +// It is recommended that the SC_MODULE code is placed in a separate header file +// If required, you can copy/paste the following template code into a header file +// called %(unit).h and uncomment the #include statement above. + +//#ifndef %(unit)_H +//#define %(unit)_H +// +//#include "systemc.h" +// +//SC_MODULE (%(unit)) +//{ +// // Ports +// sc_in clk, +// sc_in in2; +// sc_out out1; +// +// // Methods +// void %(unit)_action(); +// +// // %(unit) Constructor +// SC_CTOR(%(unit)) +// : +// { +// SC_THREAD(%(unit)_action); +// sensitive << clk.pos(); +// } +// +// // %(unit) Destructor +// ~%(unit) +// { +// } +// +//}; diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_Class/class.svh b/Prefs/hds_user/v2007.1a/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_Interface/interface.sv b/Prefs/hds_user/v2007.1a/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_Package/package.sv b/Prefs/hds_user/v2007.1a/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_Program/program.sv b/Prefs/hds_user/v2007.1a/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_include/verilog_include.v b/Prefs/hds_user/v2007.1a/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_module/module.v b/Prefs/hds_user/v2007.1a/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2007.1a/templates/verilog_module/module_migrated.v b/Prefs/hds_user/v2007.1a/templates/verilog_module/module_migrated.v new file mode 100644 index 0000000..9dd72b5 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/verilog_module/module_migrated.v @@ -0,0 +1,22 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +Template for the creation of Verilog Module files. +This template was migrated from header preferences created in a +previous version of HDL Designer. +DESCRIPTION_END +// +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// +%(moduleBody) +// +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_architecture_old/architecture.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_architecture_old/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_architecture_old/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_combined_old/combined.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_combined_old/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_combined_old/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_configuration_old/configuration.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_configuration_old/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_configuration_old/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_entity_old/entity.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_entity_old/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_entity_old/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_package_body_old/package_body.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_package_body_old/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_package_body_old/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2007.1a/templates/vhdl_package_headerù_old/package_header.vhd b/Prefs/hds_user/v2007.1a/templates/vhdl_package_headerù_old/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2007.1a/templates/vhdl_package_headerù_old/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2009.2/hds_user_prefs b/Prefs/hds_user/v2009.2/hds_user_prefs new file mode 100644 index 0000000..d2312e1 --- /dev/null +++ b/Prefs/hds_user/v2009.2/hds_user_prefs @@ -0,0 +1,5915 @@ +version "34.1" +SaPreferences [ +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 0 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(CompilationPreferences +) +(GenerationPreferences +automaticTypeConversion 0 +genPackages 1 +genDependants 0 +verilogSpecViewHeaderString "// hds header_start +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// hds header_end +%(moduleBody) +// hds interface_end +// ### Please start your Verilog code here ### + +endmodule" +vhdlConfigsName "%(unit)_config" +vhdlConfigsFileNameTemplate "%(config)" +vhdlConfigsNameTemplate "%(unit)_config" +separateEntity 1 +ansiParameterStyle 0 +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edif" +"edn" +"edf" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)' " +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "\"C:\\Program Files\\Notepad++\\notepad++.exe\" \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "\"C:\\Program Files\\IDM Computer Solutions\\UltraEdit\\Uedit32.exe\" \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\" " +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "\"C:\\Program Files\\Notepad++\\notepad++.exe\" \"%(p)\"" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "UltraEdit" +win32DefaultViewer "UltraEdit" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:VersionManagement" +"SymbolWindow:VersionManagement" +"TtWindow:VersionManagement" +"FcWindow:VersionManagement" +"StdWindow:VersionManagement" +] +seperateElseBegincheck 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "C:\\eda\\temp" +projectPaths [ +"" +"C:\\eda\\hds2\\examples\\examples.hdp" +"hds.hdp" +"C:\\Labs\\AudioAmp\\Prefs\\hds.hdp" +"C:\\Documents and Settings\\francois\\Desktop\\Examens_HDL\\Prefs\\hds.hdp" +"C:\\Labs\\Examens_HDL\\Prefs\\hds.hdp" +"D:\\Labs\\Examens_HDL\\Prefs\\hds.hdp" +"D:\\Labs\\SEm_examens\\Prefs\\hds.hdp" +"D:\\Labs\\SEm_exams\\Prefs\\hds.hdp" +] +libMappingsRootDir "$HDS_PROJECT_DIR\\..\\" +teamLibMappingsRootDir "" +projectSetupRootDir "" +defaultPackages "LIBRARY ieee; +USE ieee.std_logic_1164.all; +USE ieee.numeric_std.all; + +" +defaultVerilogPackages "" +defaultFont "Arial,8,0" +tableFont "Tahoma,10,0" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +) +printerName "\\\\ipp://ipp.hevs.ch\\PREA309_HPLJP3005DN" +pageSizes [ +(PageSizeInfo +name "A3" +type 8 +width 1077 +height 1523 +) +(PageSizeInfo +name "A4" +type 9 +width 761 +height 1077 +) +(PageSizeInfo +name "A5" +type 11 +width 536 +height 761 +) +(PageSizeInfo +name "B4 (JIS)" +type 12 +width 932 +height 1320 +) +(PageSizeInfo +name "B5 (JIS)" +type 13 +width 660 +height 932 +) +(PageSizeInfo +name "A6" +type 70 +width 380 +height 536 +) +(PageSizeInfo +name "Letter" +type 149 +width 783 +height 1013 +) +(PageSizeInfo +name "Legal" +type 150 +width 783 +height 1290 +) +(PageSizeInfo +name "Executive" +type 151 +width 667 +height 967 +) +(PageSizeInfo +name "Envelope Monarch" +type 177 +width 357 +height 691 +) +(PageSizeInfo +name "Envelope #10" +type 178 +width 380 +height 875 +) +(PageSizeInfo +name "Envelope DL" +type 179 +width 399 +height 798 +) +(PageSizeInfo +name "Envelope C5" +type 180 +width 587 +height 830 +) +(PageSizeInfo +name "Statement" +type 201 +width 506 +height 783 +) +(PageSizeInfo +name "Japanese Postcard" +type 215 +width 362 +height 536 +) +(PageSizeInfo +name "Executive (JIS)" +type 222 +width 783 +height 1196 +) +(PageSizeInfo +name "16K 197x273 mm" +type 225 +width 714 +height 990 +) +(PageSizeInfo +name "8K 273x394 mm" +type 229 +width 990 +height 1428 +) +(PageSizeInfo +name "Oficio 8.5x13" +type 259 +width 783 +height 1198 +) +] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +) +exportHTMLPageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportDirectory "D:\\Workspaces\\HDL-designer\\VerifThin\\HDL_Designer\\Doc\\HTMLExport" +exportedDirectories [ +"D:\\Workspaces\\HDL-designer\\VerifThin\\HDL_Designer\\Doc\\HTMLExport" +"$HDS_PROJECT_DIR/HTMLExport" +] +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "" +includeTitleBlock 0 +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 +color5 16777215 +color6 16777215 +color7 16777215 +color8 16777215 +color9 16777215 +color10 16777215 +color11 16777215 +color12 16777215 +color13 16777215 +color14 16777215 +color15 16777215 +) +userFileNames 1 +commentGraphicShapeVaSet (VaSet +vasetType 1 +fg "49152,49152,49152" +) +pageConnTextVaSet (VaSet +fg "0,0,50000" +font "arial,8,1" +) +teamPrefsPath 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+expandedTemplateNodes [ +] +taskTemplatePage 0 +SplitterClientPrefs [ +"mainSplitter" +(SplitterPreference +hidden 0 +expand 0 +size 201 +) +] +displayHierarchy 1 +xPos 0 +yPos 64 +width 870 +height 788 +activeSidePanelTab 2 +activeLibraryTab 1 +sidePanelSize 224 +showUnixHiddenFiles 0 +componentBrowserXpos 574 +componentBrowserYpos 75 +componentBrowserWidth 336 +componentBrowserHeight 612 +componentBrowserLibraryNames [ +"VHD" +] +) +] diff --git a/Prefs/hds_user/v2009.2/tasks/concatenate_hdl.tsk b/Prefs/hds_user/v2009.2/tasks/concatenate_hdl.tsk new file mode 100644 index 0000000..295c67f --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/concatenate_hdl.tsk @@ -0,0 +1,54 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2009.2/tasks/designchecker.tsk b/Prefs/hds_user/v2009.2/tasks/designchecker.tsk new file mode 100644 index 0000000..c69f51e --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/designchecker.tsk @@ -0,0 +1,46 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2009.2/tasks/designchecker_flow.tsk b/Prefs/hds_user/v2009.2/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..9a40217 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/designchecker_flow.tsk @@ -0,0 +1,57 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user/v2009.2/tasks/generate.tsk b/Prefs/hds_user/v2009.2/tasks/generate.tsk new file mode 100644 index 0000000..3fbbb8e --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/generate.tsk @@ -0,0 +1,46 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"generateAlways" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2009.2/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2009.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..e49dbf3 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/modelsim_compile.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +"peSe" +"EE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2009.2/tasks/modelsim_flow.tsk b/Prefs/hds_user/v2009.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..fa659e3 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "C:\\EDA\\Modelsim\\win32" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim SE 6.3g" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2009.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2009.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..fc6a139 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,86 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/wave_15_2_1.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"fs" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"Simulate" +"1" +"excludePSL" +"0" +"exepath" +"%task_ModelSimPath" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2009.2/tasks/synthesis_flow.tsk b/Prefs/hds_user/v2009.2/tasks/synthesis_flow.tsk new file mode 100644 index 0000000..e844a87 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/synthesis_flow.tsk @@ -0,0 +1,134 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Synthesis Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_leonardo.bmp" +hasBitmap 1 +tooltip "Single file VHDL Synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libs" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl %(concat_file).vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"%(library_downstream_Concatenation)" +"promptForRunSettings" +"0" +"runnableObject" +"%(task_HDSPath)\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2009.2/tasks/trim_libraries.tsk b/Prefs/hds_user/v2009.2/tasks/trim_libraries.tsk new file mode 100644 index 0000000..6587987 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/trim_libraries.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl %(concat_file).vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"%(library_downstream_Concatenation)" +"promptForRunSettings" +"0" +"runnableObject" +"C:\\eda\\hds\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2009.2/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2009.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..02a5de4 --- /dev/null +++ b/Prefs/hds_user/v2009.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"%(designName).xise" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"%(task_ISEPath)" +"promptForRunSettings" +"0" +"runnableObject" +"%(task_ISEBinPath)\\ISE\\bin\\nt\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..c21814e --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) ([%(unit)]) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..9580561 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) ([%(unit)]) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2009.2/templates/registered_views/c_file.c b/Prefs/hds_user/v2009.2/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user/v2009.2/templates/registered_views/sc_source.cpp b/Prefs/hds_user/v2009.2/templates/registered_views/sc_source.cpp new file mode 100644 index 0000000..24e5d3a --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/registered_views/sc_source.cpp @@ -0,0 +1,59 @@ +FILE_NAMING_RULE: %(unit).cpp +DESCRIPTION_START +This is the default template used for the creation of SystemC source files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +// Filename: %(view) + +#include "systemc.h" +//#include "%(unit).h" + +// Method body for %(unit)_action +void %(unit)::%(unit)_action() +{ + +} + +SC_MODULE_EXPORT(%(unit)); + +// +// It is recommended that the SC_MODULE code is placed in a separate header file +// If required, you can copy/paste the following template code into a header file +// called %(unit).h and uncomment the #include statement above. + +//#ifndef %(unit)_H +//#define %(unit)_H +// +//#include "systemc.h" +// +//SC_MODULE (%(unit)) +//{ +// // Ports +// sc_in clk, +// sc_in in2; +// sc_out out1; +// +// // Methods +// void %(unit)_action(); +// +// // %(unit) Constructor +// SC_CTOR(%(unit)) +// : +// { +// SC_THREAD(%(unit)_action); +// sensitive << clk.pos(); +// } +// +// // %(unit) Destructor +// ~%(unit) +// { +// } +// +//}; diff --git a/Prefs/hds_user/v2009.2/templates/verilog_Class/class.svh b/Prefs/hds_user/v2009.2/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user/v2009.2/templates/verilog_Interface/interface.sv b/Prefs/hds_user/v2009.2/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user/v2009.2/templates/verilog_Package/package.sv b/Prefs/hds_user/v2009.2/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user/v2009.2/templates/verilog_Program/program.sv b/Prefs/hds_user/v2009.2/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user/v2009.2/templates/verilog_include/verilog_include.v b/Prefs/hds_user/v2009.2/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user/v2009.2/templates/verilog_module/module.v b/Prefs/hds_user/v2009.2/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v b/Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v new file mode 100644 index 0000000..9dd72b5 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/verilog_module/module_migrated.v @@ -0,0 +1,22 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +Template for the creation of Verilog Module files. +This template was migrated from header preferences created in a +previous version of HDL Designer. +DESCRIPTION_END +// +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// +%(moduleBody) +// +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_architecture_old/architecture.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_architecture_old/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_architecture_old/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_combined_old/combined.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_combined_old/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_combined_old/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_configuration_old/configuration.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_configuration_old/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_configuration_old/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_entity_old/entity.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_entity_old/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_entity_old/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_package_body_old/package_body.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_package_body_old/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_body_old/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2009.2/templates/vhdl_package_headerù_old/package_header.vhd b/Prefs/hds_user/v2009.2/templates/vhdl_package_headerù_old/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2009.2/templates/vhdl_package_headerù_old/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/hds_user_prefs b/Prefs/hds_user/v2019.2/hds_user_prefs new file mode 100644 index 0000000..b904f50 --- /dev/null +++ b/Prefs/hds_user/v2019.2/hds_user_prefs @@ -0,0 +1,6570 @@ +version "49.1" +SaPreferences [ +(AnimPreferences +version "1.1" +startTime 0,0 +trailLength 0 +markEvalOnly 0 +currentVaSet (VaSet +vasetType 1 +fg "65535,0,0" +lineColor "65535,0,0" +) +previousVaSet (VaSet +vasetType 1 +fg "65535,65535,0" +lineColor "65535,65535,0" +) +evalVaSet (VaSet +vasetType 1 +fg "45055,65535,30000" +lineColor "45055,65535,30000" +) +visitedVaSet (VaSet +vasetType 1 +fg "29952,39936,65280" +lineColor "29952,39936,65280" +) +unvisitedVaSet (VaSet +vasetType 1 +fg "65535,65535,65535" +) +probeRadix 0 +) +(CompilationPreferences +) +(GenerationPreferences +automaticTypeConversion 0 +genPackages 1 +genDependants 0 +verilogSpecViewHeaderString "// hds header_start +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// hds header_end +%(moduleBody) +// hds interface_end +// ### Please start your Verilog code here ### + +endmodule" +vhdlConfigsName "%(unit)_config" +vhdlConfigsFileNameTemplate "%(config)" +vhdlConfigsNameTemplate "%(unit)_config" +separateEntity 1 +ansiParameterStyle 0 +) +(BasePreferences +version "1.1" +textFileExtensions [ +"txt" +"ini" +"tcl" +"dcs" +"edif" +"edn" +"edf" +] +textViewPrintingCommands [ +(pair +first "Enscript" +second "$HDS_HOME/resources/misc/printText.pl \"%(p)\" -printer %(P) --copies %(copies) -orientation %(orientation) -paper %(paper) -dest %(destination)" +) +] +win32ExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "Windows Bitmap BMP" +second "$HDS_HOME/resources/misc/export_tgc.pl bmp \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsEnhancedMetaFile EMF" +second "$HDS_HOME/resources/misc/export_tgc.pl emf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixExportCmdMappings [ +(pair +first "CGM Binary" +second "$HDS_HOME/resources/misc/export_tgc.pl cgm \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "FrameMaker MIF" +second "$HDS_HOME/resources/misc/export_tgc.pl mif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "GIF" +second "$HDS_HOME/resources/misc/export_tgc.pl gif \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "TIFF" +second "$HDS_HOME/resources/misc/export_tgc.pl tiff \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +(pair +first "WindowsMetaFile WMF" +second "$HDS_HOME/resources/misc/export_tgc.pl wmf \"%(psfile_p)\" \"%(temp_d)\" %(library) %(unit) %(view)" +) +] +unixEditorCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)'" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)'" +) +(pair +first "Emacs (using server)" +second "emacsclient +%(l) '%(p)'" +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)'" +) +(pair +first "XEmacs" +second "xemacs +%(l) '%(p)'" +) +(pair +first "XEmacs (using server)" +second "gnuclient +%(l) '%(p)'" +) +(pair +first "XTerm with Editor" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e \"${EDITOR:-vi}\" '%(f)'" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi +%(l) '%(f)'" +) +] +unixViewerCmdMappings [ +(pair +first "Dtpad" +second "dtpad '%(p)' -viewonly" +) +(pair +first "Emacs" +second "emacs +%(l) '%(p)' " +) +(pair +first "NEdit" +second "$HDS_HOME/resources/nedit/nedit.sh -read +%(l) '%(p)'" +) +(pair +first "NEdit (using server)" +second "$HDS_HOME/resources/nedit/nc -noask -read +%(l) '%(p)'" +) +(pair +first "Textedit" +second "textedit '%(p)' -read_only" +) +(pair +first "vi" +second "cd '%(d)'; xterm -T '%(p)' -n '%(f)' -e vi -R +%(l) '%(f)'" +) +] +win32EditorCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\"" +) +(pair +first "Emacs (using server)" +second "gnuclientw.exe +%(l) \"%(p)\"" +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -G%(l)" +) +(pair +first "Notepad" +second "\"C:\\Program Files\\Notepad++\\notepad++.exe\" \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "\"C:\\Program Files\\IDM Computer Solutions\\UltraEdit\\Uedit32.exe\" \"%(p)/%(l)\"" +) +(pair +first "WinEdit" +second "WinEdit.exe \"%(p)\" -# %(l)" +) +(pair +first "Wordpad" +second "wordpad.exe \"%(p)\"" +) +] +win32ViewerCmdMappings [ +(pair +first "Emacs" +second "runemacs.exe +%(l) \"%(p)\" " +) +(pair +first "HDL Turbo Writer" +second "TWriter.exe \"%(p)\" -XBufSetReadOnly -G%(l)" +) +(pair +first "Notepad" +second "\"C:\\Program Files\\Notepad++\\notepad++.exe\" \"%(p)\"" +) +(pair +first "Notepad++" +second "notepad++.exe \"%(p)\" -n%(l)" +) +(pair +first "Textpad 3.2" +second "txtpad32.exe -r \"%(p)(%(l))\"" +) +(pair +first "Textpad 4.0" +second "textpad.exe -r \"%(p)(%(l))\"" +) +(pair +first "UltraEdit" +second "uedit32.exe \"%(p)/%(l)\" /r" +) +] +defaultTextPrintingCmd "Enscript" +win32DefaultEditor "Notepad++" +win32DefaultViewer "Notepad++" +unixDefaultEditor "Builtin" +unixDefaultViewer "Builtin" +defaultLanguage 11 +defaultVhdlDialect 11 +verilogSearchPath "" +syscUserIncPath "" +cppIncPath "" +printerCmdString "lp -c" +tabWidth 3 +vhdlEntityExtension "vhd" +vhdlArchitectureExtensions [ +"vhd" +"vhdl" +"vho" +] +verilogArchitectureExtensions [ +"v" +"vlg" +"verilog" +"vo" +"sv" +"svh" +] +verilogDefaultSaveName "untitled" +vhdlDefaultSaveName "untitled" +toolbarVisibility [ +"BdWindow:VersionManagement" +"SymbolWindow:VersionManagement" +"TtWindow:VersionManagement" +"FcWindow:VersionManagement" +"StdWindow:VersionManagement" +] +seperateElseBegincheck 1 +userDefinedSimulatorTasks [ +] +userDefinedSynthesisTasks [ +] +simulator "ModelSim 5.1" +tempDirectory "C:\\eda\\temp" +projectPaths [ +"" +"C:\\eda\\hds2\\examples\\examples.hdp" +"hds.hdp" +"C:\\Labs\\AudioAmp\\Prefs\\hds.hdp" +"C:\\Documents and Settings\\francois\\Desktop\\Examens_HDL\\Prefs\\hds.hdp" +"C:\\Labs\\Examens_HDL\\Prefs\\hds.hdp" +"D:\\Labs\\Examens_HDL\\Prefs\\hds.hdp" +"D:\\Labs\\SEm_examens\\Prefs\\hds.hdp" +"D:\\Labs\\SEm_exams\\Prefs\\hds.hdp" +"c:\\work\\Exam\\Prefs\\hds.hdp" +"c:\\work\\19_1_Exam\\Prefs\\hds.hdp" +"c:\\work\\19_2_Exam\\Prefs\\hds.hdp" +"C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Prefs\\hds.hdp" +"C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\hds.hdp" +"C:\\Users\\remy.borgeat\\Downloads\\Exam_24_1\\Exam_24_1\\Prefs\\hds.hdp" +] +libMappingsRootDir "$HDS_PROJECT_DIR\\..\\" +teamLibMappingsRootDir "" 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+] +exportPageSetupInfo (PageSetupInfo +ptrCmd "FrameMaker MIF" +toPrinter 1 +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +) +exportHTMLPageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +exportDirectory "D:\\Workspaces\\HDL-designer\\VerifThin\\HDL_Designer\\Doc\\HTMLExport" +exportedDirectories [ +"D:\\Workspaces\\HDL-designer\\VerifThin\\HDL_Designer\\Doc\\HTMLExport" +"$HDS_PROJECT_DIR/HTMLExport" +] +) +exportHTMLPrintHierInfo (PrintHierInfo +includeViewTypes [ +] +) +customPaperSizeInfo [ +] +exportImageSizeInfo [ +(StringtoTwoInts +name "A4 (134mm x 110mm)" +width 379 +height 313 +) +(StringtoTwoInts +name "A4 (134mm x 221mm)" +width 379 +height 626 +) +(StringtoTwoInts +name "Letter (5.5\" x 4\")" +width 396 +height 288 +) +(StringtoTwoInts +name "Letter (5.5\" x 8\")" +width 396 +height 576 +) +] +titleBlockPath "" +includeTitleBlock 0 +win32CustomColours (win32CustomColours +color0 16777215 +color1 16777215 +color2 16777215 +color3 16777215 +color4 16777215 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0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "FunctionGenerator" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "VerifThin" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "VerifThin" +primaryName "toplevel" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "VerifThin_TB" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "VerifThin_TB" +primaryName "VerifThin_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "filters" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "filters" +primaryName "highpass_50" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "filters_test" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "filters_test" +primaryName "highpass_50_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "ADC_CS5368" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "ADC_CS5368" +primaryName "adc_interface" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "HESSO" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "cypress_usb_lib" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "cypress_usb_lib" +primaryName "USB_FX2_Interface_Sync_top" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "AudioAmp" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "AudioAmp" +primaryName "toplevel" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "AudioAmp_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "AudioAmp_test" +primaryName "VerifThin_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Modulation" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "Modulation_test" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Modulation_test" +primaryName "sigmaDeltaModulator_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "ADC_CS5368" +showingHierarchy 0 +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "ADC_CS5368" +primaryName "adc_interface" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "ADC_CS5368_test" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "ADC_CS5368_test" +primaryName "ADC_CS5368_tb" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "Board" +openLibs [ +] +declHierarchy [ +(DeclHierarchy +libName "Board" +primaryName "verifThin_ebs" +secondaryName "" +) +] +activeViewpointIdx 0 +) +(WorkTab +name "VHD" +showingHierarchy 0 +openLibs [ +"VHD" +] +declHierarchy [ +] +activeViewpointIdx 0 +) +(WorkTab +name "VHD_test" +showingHierarchy 0 +openLibs [ +"VHD_test" +] +declHierarchy [ +(DeclHierarchy +libName "VHD_test" +primaryName "tb_04_2" +secondaryName "" +) +] +activeViewpointIdx 0 +) +] +ViewpointsOnOutlookBar [ +"Requirements" +] +lastActiveViewpoint "Default Viewpoint" +expandedTemplateNodes [ +] +taskTemplatePage 0 +SplitterClientPrefs [ +"mainSplitter" +(SplitterPreference +hidden 0 +expand 0 +size 201 +) +] +displayHierarchy 1 +xPos 0 +yPos 23 +width 1936 +height 1056 +activeSidePanelTab 2 +activeLibraryTab 1 +sidePanelSize 224 +showUnixHiddenFiles 0 +componentBrowserXpos 574 +componentBrowserYpos 75 +componentBrowserWidth 336 +componentBrowserHeight 612 +componentBrowserLibraryNames [ +"VHD" +] +) +] diff --git a/Prefs/hds_user/v2019.2/tasks/concatenate_hdl.tsk b/Prefs/hds_user/v2019.2/tasks/concatenate_hdl.tsk new file mode 100644 index 0000000..295c67f --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/concatenate_hdl.tsk @@ -0,0 +1,54 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/designchecker.tsk b/Prefs/hds_user/v2019.2/tasks/designchecker.tsk new file mode 100644 index 0000000..8792feb --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/designchecker.tsk @@ -0,0 +1,52 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "DesignChecker" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Runs DesignChecker" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"forceGui" +"NO_FORCE" +"initialDir" +"" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"HdsLintPlugin" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/designchecker_flow.tsk b/Prefs/hds_user/v2019.2/tasks/designchecker_flow.tsk new file mode 100644 index 0000000..5805a97 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/designchecker_flow.tsk @@ -0,0 +1,64 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "DesignChecker Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Generate and runs DesignChecker" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "DesignChecker" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"forceGui" +"NO_FORCE" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Policy" +"My_Essentials_Policy" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:DesignChecker" +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/generate.tsk b/Prefs/hds_user/v2019.2/tasks/generate.tsk new file mode 100644 index 0000000..651aea2 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/generate.tsk @@ -0,0 +1,48 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Generate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_generate.bmp" +hasBitmap 1 +tooltip "Performs generation of graphics files" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"Generator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"generateAlways" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk new file mode 100644 index 0000000..574f7ff --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_compile.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Compile" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_compile.bmp" +hasBitmap 1 +tooltip "Runs ModelSim compilation" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runMethod" +"gui" +"runnableObject" +"ModelSimCompiler" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"exepath" +"%task_ModelSimPath" +"peSe" +"EE" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk new file mode 100644 index 0000000..fa659e3 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_flow.tsk @@ -0,0 +1,74 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "ModelSim Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim.bmp" +hasBitmap 1 +tooltip "Generate and run entire ModelSim flow" +taskSettings [ +] +PreferedTasks [ +(preferedMap +preferedEnum 0 +preferedSetting "C:\\EDA\\Modelsim\\win32" +) +(preferedMap +preferedEnum 2 +preferedSetting "ModelSim SE 6.3g" +) +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "ModelSim Compile" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:ModelSim Compile" +) +(HDSTaskRef +TaskName "ModelSim Simulate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +reffedTaskName "USER:ModelSim Simulate" +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk b/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk new file mode 100644 index 0000000..a04a23e --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/modelsim_simulate.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "ModelSim Simulate" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_modelsim_invoke.bmp" +hasBitmap 1 +tooltip "Invokes the ModelSim Simulator" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runMethod" +"gui" +"runnableObject" +"ModelSimSimulator" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"Arguments" +"" +"Communication" +"1" +"DelaySelection" +"typ" +"GlitchGeneration" +"1" +"InitCmd" +"$SIMULATION_DIR/wave_24_1_1.do" +"LogFile" +"" +"RemoteHost" +"" +"Resolution" +"100fs" +"SdfDelay" +"typ" +"SdfMultiSrcDelay" +"latest" +"SdfReduce" +"0" +"SdfWarnings" +"1" +"TimingChecks" +"1" +"UseBatch" +"0" +"UseCLI" +"0" +"UseGUI" +"1" +"VitalVersion" +"95" +"autoNames" +"1" +"coverage" +"1" +"excludePSL" +"0" +"exepath" +"%task_ModelSimPath" +"minimumSimSetting" +"0" +"saveReplayScript" +"0" +"useCustomSimDir" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/quartus_prime_import.tsk b/Prefs/hds_user/v2019.2/tasks/quartus_prime_import.tsk new file mode 100644 index 0000000..b0fa4e4 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/quartus_prime_import.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Prime Import" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_altera_quartus_prime.bmp" +hasBitmap 1 +tooltip "Import IP variations from Quartus Prime" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"\"%(p)\" %(library)" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QuartusPrimeImport" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/quartus_synthesis.tsk b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis.tsk new file mode 100644 index 0000000..4a3e832 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis.tsk @@ -0,0 +1,94 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Runs Quartus Synthesis data preparation and invokes tool" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_flow.tsk b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_flow.tsk new file mode 100644 index 0000000..ed20b5b --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_flow.tsk @@ -0,0 +1,50 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Quartus Synthesis Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Generate and runs the entire Quartus QIS Synthesis flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTaskRef +TaskName "Quartus Synthesis" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Quartus Synthesis" +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_invoke.tsk b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_invoke.tsk new file mode 100644 index 0000000..eaa7bd8 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_invoke.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Invoke" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Invokes the Quartus Synthesis tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"QISInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_prepare_data.tsk b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_prepare_data.tsk new file mode 100644 index 0000000..3c4b7b2 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/quartus_synthesis_prepare_data.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Quartus Synthesis Prepare Data" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_quartus_synthesis.bmp" +hasBitmap 1 +tooltip "Does data preparation for Quartus Synthesis" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"QISDataPrep" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) diff --git a/Prefs/hds_user/v2019.2/tasks/register_assistant.tsk b/Prefs/hds_user/v2019.2/tasks/register_assistant.tsk new file mode 100644 index 0000000..a63fe73 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/register_assistant.tsk @@ -0,0 +1,45 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Register Assistant" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_registerassistant.bmp" +hasBitmap 1 +tooltip "Invokes Register Assistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"RegisterAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 1 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/svassistant_flow.tsk b/Prefs/hds_user/v2019.2/tasks/svassistant_flow.tsk new file mode 100644 index 0000000..7a04f29 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/svassistant_flow.tsk @@ -0,0 +1,78 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "SVAssistant Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant Flow" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 1 +onPulldownMenu 1 +onToolbar 1 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "SVAssistant" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_svassistant.bmp" +hasBitmap 1 +tooltip "Invokes SVAssistant" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"noNeedForThroughDesignRoot" +"1" +"noNeedForUseViewSpecificSettings" +"1" +"noSettingsDlg" +"1" +"promptForRunSettings" +"0" +"runnableObject" +"SvAssistantInvoke" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/synthesis_flow.tsk b/Prefs/hds_user/v2019.2/tasks/synthesis_flow.tsk new file mode 100644 index 0000000..e844a87 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/synthesis_flow.tsk @@ -0,0 +1,134 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Synthesis Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools\\tool_leonardo.bmp" +hasBitmap 1 +tooltip "Single file VHDL Synthesis Flow" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"flowSettingsDlg" +"" +"taskInvocationScript" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Concatenate HDL" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_designanalyst.bmp" +hasBitmap 1 +tooltip "Appends all HDL files together" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"0" +"runnableObject" +"Concatenation" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +"TaskSetting" +(SettingsMap +settingsMap [ +"outputFileNameRoot" +"%(concat_file)" +"outputVerilogFileExtension" +"v" +"outputVhdlFileExtension" +"vhd" +"place" +"0" +"specifyDir" +"" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libs" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl %(concat_file).vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"%(library_downstream_Concatenation)" +"promptForRunSettings" +"0" +"runnableObject" +"%(task_HDSPath)\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) +] +) diff --git a/Prefs/hds_user/v2019.2/tasks/trim_libraries.tsk b/Prefs/hds_user/v2019.2/tasks/trim_libraries.tsk new file mode 100644 index 0000000..6587987 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/trim_libraries.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Trim libraries" +bitmap "tool_default_tool.bmp" +hasBitmap 1 +tooltip "Comment out library declarations for single file VHDL" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"trimlibs.pl %(concat_file).vhd" +"captureOutput" +"1" +"customPrompt" +"" +"initialDir" +"%(library_downstream_Concatenation)" +"promptForRunSettings" +"0" +"runnableObject" +"C:\\eda\\hds\\resources\\perl\\bin\\perl.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk b/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk new file mode 100644 index 0000000..02a5de4 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/xilinx_project_navigator.tsk @@ -0,0 +1,39 @@ +version "1.1" +HDSTool (HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Project Navigator" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_projnav.bmp" +hasBitmap 1 +tooltip "Invokes the Xilinx ISE tool" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"%(designName).xise" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"%(task_ISEPath)" +"promptForRunSettings" +"0" +"runnableObject" +"%(task_ISEBinPath)\\ISE\\bin\\nt\\ise.exe" +"runnableObjectType" +"executable" +"useViewSpecific" +"0" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 3 +) diff --git a/Prefs/hds_user/v2019.2/tasks/xilinx_vivado_flow.tsk b/Prefs/hds_user/v2019.2/tasks/xilinx_vivado_flow.tsk new file mode 100644 index 0000000..540c8c6 --- /dev/null +++ b/Prefs/hds_user/v2019.2/tasks/xilinx_vivado_flow.tsk @@ -0,0 +1,72 @@ +version "1.1" +HDSFlow (HDSFlow +TaskName "Xilinx Vivado Flow" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "Generate and runs Xilinx Vivado wizard" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +subTasks [ +(HDSTaskRef +TaskName "Generate" +bitmap "" +hasBitmap 1 +tooltip "" +taskSettings [ +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +reffedTaskName "USER:Generate" +) +(HDSTool +hasAssociatedFileExt 0 +associatedFileExt "" +TaskName "Xilinx Vivado" +bitmap "$HDS_HOME\\resources\\bitmaps\\tools/tool_xilinx_vivado.bmp" +hasBitmap 1 +tooltip "HDS integration with Xilinx Vivado" +taskSettings [ +"InternalTaskSetting" +(SettingsMap +settingsMap [ +"additionalToolArgs" +"" +"captureOutput" +"0" +"customPrompt" +"" +"initialDir" +"" +"promptForRunSettings" +"1" +"runnableObject" +"XilinxVivado" +"runnableObjectType" +"tcl_plugin" +"useViewSpecific" +"1" +] +) +] +PreferedTasks [ +] +onShortcutBar 0 +onPulldownMenu 0 +onToolbar 0 +enabled 1 +hierDepth 1 +) +] +) diff --git a/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_VHDL.psl b/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_VHDL.psl new file mode 100644 index 0000000..c21814e --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_VHDL.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (VHDL) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- PSL Vunit(VHDL Syntax) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- + +vunit %(view) ([%(unit)]) +{ + default clock IS ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_Verilog.psl b/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_Verilog.psl new file mode 100644 index 0000000..9580561 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/registered_views/Vunit_Verilog.psl @@ -0,0 +1,19 @@ +DESCRIPTION_START +This is the default template used for the creation of PSL Vunit (Verilog) files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// PSL Vunit(Verilog Syntax) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// + +vunit %(view) ([%(unit)]) +{ + default clock = ClockName; + +} \ No newline at end of file diff --git a/Prefs/hds_user/v2019.2/templates/registered_views/c_file.c b/Prefs/hds_user/v2019.2/templates/registered_views/c_file.c new file mode 100644 index 0000000..44b6986 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/registered_views/c_file.c @@ -0,0 +1,13 @@ +FILE_NAMING_RULE: c_file.c +DESCRIPTION_START +This is the default template used for the creation of C files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +/* + * Created: + * by - %(user).%(group) (%(host)) + * at - %(time) %(date) + * + * using Mentor Graphics HDL Designer(TM) %(version) + */ + diff --git a/Prefs/hds_user/v2019.2/templates/registered_views/sc_source.cpp b/Prefs/hds_user/v2019.2/templates/registered_views/sc_source.cpp new file mode 100644 index 0000000..24e5d3a --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/registered_views/sc_source.cpp @@ -0,0 +1,59 @@ +FILE_NAMING_RULE: %(unit).cpp +DESCRIPTION_START +This is the default template used for the creation of SystemC source files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +// Filename: %(view) + +#include "systemc.h" +//#include "%(unit).h" + +// Method body for %(unit)_action +void %(unit)::%(unit)_action() +{ + +} + +SC_MODULE_EXPORT(%(unit)); + +// +// It is recommended that the SC_MODULE code is placed in a separate header file +// If required, you can copy/paste the following template code into a header file +// called %(unit).h and uncomment the #include statement above. + +//#ifndef %(unit)_H +//#define %(unit)_H +// +//#include "systemc.h" +// +//SC_MODULE (%(unit)) +//{ +// // Ports +// sc_in clk, +// sc_in in2; +// sc_out out1; +// +// // Methods +// void %(unit)_action(); +// +// // %(unit) Constructor +// SC_CTOR(%(unit)) +// : +// { +// SC_THREAD(%(unit)_action); +// sensitive << clk.pos(); +// } +// +// // %(unit) Destructor +// ~%(unit) +// { +// } +// +//}; diff --git a/Prefs/hds_user/v2019.2/templates/verilog_Class/class.svh b/Prefs/hds_user/v2019.2/templates/verilog_Class/class.svh new file mode 100644 index 0000000..a5025df --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_Class/class.svh @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(class_name).svh +DESCRIPTION_START +This is the default template used for the creation of Class files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog class %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(classBody) +// ### Please start your Verilog code here ### + +endclass diff --git a/Prefs/hds_user/v2019.2/templates/verilog_Interface/interface.sv b/Prefs/hds_user/v2019.2/templates/verilog_Interface/interface.sv new file mode 100644 index 0000000..c29c5ba --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_Interface/interface.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(interface_name).sv +DESCRIPTION_START +This is the default template used for the creation of Interface files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog interface %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(interfaceBody) + +// ### Please start your Verilog code here ### +endinterface diff --git a/Prefs/hds_user/v2019.2/templates/verilog_Package/package.sv b/Prefs/hds_user/v2019.2/templates/verilog_Package/package.sv new file mode 100644 index 0000000..9cdc15b --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_Package/package.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(package_name).sv +DESCRIPTION_START +This is the default template used for the creation of Package files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog package %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(packageBody) +// ### Please start your Verilog code here ### + +endpackage diff --git a/Prefs/hds_user/v2019.2/templates/verilog_Program/program.sv b/Prefs/hds_user/v2019.2/templates/verilog_Program/program.sv new file mode 100644 index 0000000..1b6dc84 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_Program/program.sv @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(program_name).sv +DESCRIPTION_START +This is the default template used for the creation of program files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog program %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(programBody) + +// ### Please start your Verilog code here ### +endprogram diff --git a/Prefs/hds_user/v2019.2/templates/verilog_include/verilog_include.v b/Prefs/hds_user/v2019.2/templates/verilog_include/verilog_include.v new file mode 100644 index 0000000..42702ef --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_include/verilog_include.v @@ -0,0 +1,14 @@ +FILE_NAMING_RULE: include_filename.v +DESCRIPTION_START +This is the default template used for the creation of Verilog Include files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Include file %(library) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// diff --git a/Prefs/hds_user/v2019.2/templates/verilog_module/module.v b/Prefs/hds_user/v2019.2/templates/verilog_module/module.v new file mode 100644 index 0000000..2c8283c --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_module/module.v @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +This is the default template used for the creation of Verilog Module files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +// +// Verilog Module %(library).%(unit) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// using Mentor Graphics HDL Designer(TM) %(version) +// +%(moduleBody) +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2019.2/templates/verilog_module/module_migrated.v b/Prefs/hds_user/v2019.2/templates/verilog_module/module_migrated.v new file mode 100644 index 0000000..9dd72b5 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/verilog_module/module_migrated.v @@ -0,0 +1,22 @@ +FILE_NAMING_RULE: %(module_name).v +DESCRIPTION_START +Template for the creation of Verilog Module files. +This template was migrated from header preferences created in a +previous version of HDL Designer. +DESCRIPTION_END +// +// +// Module %(library).%(unit).%(view) +// +// Created: +// by - %(user).%(group) (%(host)) +// at - %(time) %(date) +// +// Generated by Mentor Graphics' HDL Designer(TM) %(version) +// +// +%(moduleBody) +// +// ### Please start your Verilog code here ### + +endmodule diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_architecture/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_architecture_old/architecture.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_architecture_old/architecture.vhd new file mode 100644 index 0000000..faf9041 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_architecture_old/architecture.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Architecture files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_combined/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_combined_old/combined.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_combined_old/combined.vhd new file mode 100644 index 0000000..ba6941d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_combined_old/combined.vhd @@ -0,0 +1,17 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name).vhd +DESCRIPTION_START +This is the default template used for the creation of combined VHDL Architecture and Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Architecture %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) +-- +%(architecture) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_configuration/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_configuration_old/configuration.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_configuration_old/configuration.vhd new file mode 100644 index 0000000..302dffe --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_configuration_old/configuration.vhd @@ -0,0 +1,19 @@ +FILE_NAMING_RULE: %(entity_name)_%(arch_name)_config.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Configuration files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Configuration %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +CONFIGURATION %(entity_name)_config OF %(entity_name) IS + FOR %(arch_name) + END FOR; +END %(entity_name)_config; + diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_entity/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_entity_old/entity.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_entity_old/entity.vhd new file mode 100644 index 0000000..272950c --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_entity_old/entity.vhd @@ -0,0 +1,15 @@ +FILE_NAMING_RULE: %(entity_name)_entity.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Entity files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Entity %(library).%(unit).%(view) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +%(entity) diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_body/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_body_old/package_body.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_body_old/package_body.vhd new file mode 100644 index 0000000..0f95d5d --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_body_old/package_body.vhd @@ -0,0 +1,16 @@ +FILE_NAMING_RULE: %(entity_name)_pkg_body.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Body files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Body %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +PACKAGE BODY %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_header/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Prefs/hds_user/v2019.2/templates/vhdl_package_headerù_old/package_header.vhd b/Prefs/hds_user/v2019.2/templates/vhdl_package_headerù_old/package_header.vhd new file mode 100644 index 0000000..d4257e1 --- /dev/null +++ b/Prefs/hds_user/v2019.2/templates/vhdl_package_headerù_old/package_header.vhd @@ -0,0 +1,18 @@ +FILE_NAMING_RULE: %(entity_name)_pkg.vhd +DESCRIPTION_START +This is the default template used for the creation of VHDL Package Header files. +Template supplied by Mentor Graphics. +DESCRIPTION_END +-- +-- VHDL Package Header %(library).%(unit) +-- +-- Created: +-- by - %(user).%(group) (%(host)) +-- at - %(time) %(date) +-- +-- using Mentor Graphics HDL Designer(TM) %(version) +-- +LIBRARY ieee; +USE ieee.std_logic_1164.all; +PACKAGE %(entity_name) IS +END %(entity_name); diff --git a/Simulation/wave.do b/Simulation/wave.do new file mode 100644 index 0000000..5ca6645 --- /dev/null +++ b/Simulation/wave.do @@ -0,0 +1,25 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_1/reset +add wave -noupdate /tb_24_1_1/clock +add wave -noupdate /tb_24_1_1/up_down +add wave -noupdate /tb_24_1_1/en +add wave -noupdate -radix unsigned -radixshowbase 0 /tb_24_1_1/position +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6660982000 fs} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 155 +configure wave -valuecolwidth 60 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 fs} {23856132075 fs} diff --git a/Simulation/wave_24_1_1.do b/Simulation/wave_24_1_1.do new file mode 100644 index 0000000..52578ad --- /dev/null +++ b/Simulation/wave_24_1_1.do @@ -0,0 +1,25 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_1/reset +add wave -noupdate /tb_24_1_1/clock +add wave -noupdate /tb_24_1_1/up_down +add wave -noupdate /tb_24_1_1/en +add wave -noupdate -radix unsigned -radixshowbase 0 /tb_24_1_1/position +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {6660982 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 155 +configure wave -valuecolwidth 60 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {26250 ns} diff --git a/Simulation/wave_24_1_2.do b/Simulation/wave_24_1_2.do new file mode 100644 index 0000000..c1d805c --- /dev/null +++ b/Simulation/wave_24_1_2.do @@ -0,0 +1,25 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_2/pwm +add wave -noupdate /tb_24_1_2/motorOn +add wave -noupdate /tb_24_1_2/right_left +add wave -noupdate /tb_24_1_2/side1 +add wave -noupdate /tb_24_1_2/side2 +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 156 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {105 us} diff --git a/Simulation/wave_24_1_3.do b/Simulation/wave_24_1_3.do new file mode 100644 index 0000000..091baf4 --- /dev/null +++ b/Simulation/wave_24_1_3.do @@ -0,0 +1,24 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_3/reset +add wave -noupdate /tb_24_1_3/clock +add wave -noupdate /tb_24_1_3/testMode +add wave -noupdate /tb_24_1_3/pwmEn +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 156 +configure wave -valuecolwidth 40 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {10500 ns} diff --git a/Simulation/wave_24_1_4.do b/Simulation/wave_24_1_4.do new file mode 100644 index 0000000..6019be0 --- /dev/null +++ b/Simulation/wave_24_1_4.do @@ -0,0 +1,26 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_4/reset +add wave -noupdate /tb_24_1_4/clock +add wave -noupdate /tb_24_1_4/A +add wave -noupdate /tb_24_1_4/B +add wave -noupdate /tb_24_1_4/en +add wave -noupdate /tb_24_1_4/dir +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {0 ps} 0} +quietly wave cursor active 0 +configure wave -namecolwidth 150 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {26250 ns} diff --git a/Simulation/wave_24_1_5.do b/Simulation/wave_24_1_5.do new file mode 100644 index 0000000..4b8aaf0 --- /dev/null +++ b/Simulation/wave_24_1_5.do @@ -0,0 +1,25 @@ +onerror {resume} +quietly WaveActivateNextPane {} 0 +add wave -noupdate /tb_24_1_5/reset +add wave -noupdate /tb_24_1_5/clock +add wave -noupdate /tb_24_1_5/start +add wave -noupdate -format Analog-Step -height 100 -max 255.0 -radix unsigned -radixshowbase 0 /tb_24_1_5/speed +add wave -noupdate /tb_24_1_5/done +TreeUpdate [SetDefaultTree] +WaveRestoreCursors {{Cursor 1} {826772 ps} 0} +quietly wave cursor active 1 +configure wave -namecolwidth 184 +configure wave -valuecolwidth 100 +configure wave -justifyvalue left +configure wave -signalnamewidth 0 +configure wave -snapdistance 10 +configure wave -datasetprefix 0 +configure wave -rowmargin 4 +configure wave -childrowmargin 2 +configure wave -gridoffset 0 +configure wave -gridperiod 1 +configure wave -griddelta 40 +configure wave -timeline 0 +configure wave -timelineunits us +update +WaveRestoreZoom {0 ps} {4200 ns} diff --git a/VHD/hdl/ex_24_1_1_entity.vhd b/VHD/hdl/ex_24_1_1_entity.vhd new file mode 100644 index 0000000..cb63342 --- /dev/null +++ b/VHD/hdl/ex_24_1_1_entity.vhd @@ -0,0 +1,28 @@ +-- VHDL Entity VHD.ex_24_1_1.symbol +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:02:45 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_24_1_1 IS + GENERIC( + counterBitNb : positive := 8 + ); + PORT( + en : IN std_ulogic; + position : OUT unsigned (counterBitNb-1 DOWNTO 0); + up_down : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic + ); + +-- Declarations + +END ex_24_1_1 ; + diff --git a/VHD/hdl/ex_24_1_1_studentVersion.vhd b/VHD/hdl/ex_24_1_1_studentVersion.vhd new file mode 100644 index 0000000..7affbb2 --- /dev/null +++ b/VHD/hdl/ex_24_1_1_studentVersion.vhd @@ -0,0 +1,22 @@ +architecture studentVersion of ex_24_1_1 is + + signal counter : unsigned(counterBitNb-1 downto 0); + +begin + + process(clock, reset) begin + if reset = '1' then + counter <= (others => '0'); + elsif rising_edge(clock) then + if en = '1' then + if up_down = '1' then + counter <= counter + 1; + else + counter <= counter -1; + end if; + end if; + end if; + end process; + + position <= counter; +end studentVersion; diff --git a/VHD/hdl/ex_24_1_2_entity.vhd b/VHD/hdl/ex_24_1_2_entity.vhd new file mode 100644 index 0000000..0a4670a --- /dev/null +++ b/VHD/hdl/ex_24_1_2_entity.vhd @@ -0,0 +1,25 @@ +-- VHDL Entity VHD.ex_24_1_2.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:18:55 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_24_1_2 IS + PORT( + motorOn : IN std_ulogic; + side1 : OUT std_ulogic; + right_left : IN std_ulogic; + pwm : IN std_ulogic; + side2 : OUT std_ulogic + ); + +-- Declarations + +END ex_24_1_2 ; + diff --git a/VHD/hdl/ex_24_1_2_studentVersion.vhd b/VHD/hdl/ex_24_1_2_studentVersion.vhd new file mode 100644 index 0000000..6b46685 --- /dev/null +++ b/VHD/hdl/ex_24_1_2_studentVersion.vhd @@ -0,0 +1,25 @@ +architecture studentVersion of ex_24_1_2 is + + signal mySignal: std_ulogic; + +begin + + process(motorOn, pwm) begin + if motorOn = '1' then + mySignal <= pwm; + else + mySignal <= '0'; + end if; + end process; + + process(mySignal, right_left) begin + if right_left = '1' then + side1 <= mySignal; + side2 <= '0'; + else + side1 <= '0'; + side2 <= mySignal; + end if; + end process; + +end studentVersion; diff --git a/VHD/hdl/ex_24_1_3_entity.vhg b/VHD/hdl/ex_24_1_3_entity.vhg new file mode 100644 index 0000000..d89012d --- /dev/null +++ b/VHD/hdl/ex_24_1_3_entity.vhg @@ -0,0 +1,28 @@ +-- VHDL Entity VHD.ex_19_1_3.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:40:30 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_19_1_3 IS + GENERIC( + timerBitNb : positive := 8; + testModeBitNb : positive := 1 + ); + PORT( + testMode : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + pwmEn : OUT std_ulogic + ); + +-- Declarations + +END ex_19_1_3 ; + diff --git a/VHD/hdl/ex_24_1_3_studentVersion.vhd b/VHD/hdl/ex_24_1_3_studentVersion.vhd new file mode 100644 index 0000000..e543b91 --- /dev/null +++ b/VHD/hdl/ex_24_1_3_studentVersion.vhd @@ -0,0 +1,4 @@ +architecture studentVersion of ex_24_1_3 is +begin + pwmEn <= '0'; +end studentVersion; diff --git a/VHD/hdl/ex_24_1_4_entity.vhg b/VHD/hdl/ex_24_1_4_entity.vhg new file mode 100644 index 0000000..c0a7e3a --- /dev/null +++ b/VHD/hdl/ex_24_1_4_entity.vhg @@ -0,0 +1,26 @@ +-- VHDL Entity VHD.ex_19_1_4.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 12:57:27 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_19_1_4 IS + PORT( + A : IN std_ulogic; + B : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + en : OUT std_ulogic; + dir : OUT std_ulogic + ); + +-- Declarations + +END ex_19_1_4 ; + diff --git a/VHD/hdl/ex_24_1_4_studentVersion.vhd b/VHD/hdl/ex_24_1_4_studentVersion.vhd new file mode 100644 index 0000000..2c7362b --- /dev/null +++ b/VHD/hdl/ex_24_1_4_studentVersion.vhd @@ -0,0 +1,5 @@ +architecture studentVersion of ex_24_1_4 is +begin + en <= '0'; + dir <= '0'; +end studentVersion; diff --git a/VHD/hdl/ex_24_1_5_entity.vhg b/VHD/hdl/ex_24_1_5_entity.vhg new file mode 100644 index 0000000..a4e6211 --- /dev/null +++ b/VHD/hdl/ex_24_1_5_entity.vhg @@ -0,0 +1,28 @@ +-- VHDL Entity VHD.ex_19_1_5.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:26 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_19_1_5 IS + GENERIC( + speedBitNb : positive + ); + PORT( + start : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + done : OUT std_ulogic; + speed : OUT unsigned (speedBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END ex_19_1_5 ; + diff --git a/VHD/hdl/ex_24_1_5_studentVersion.vhd b/VHD/hdl/ex_24_1_5_studentVersion.vhd new file mode 100644 index 0000000..1626ede --- /dev/null +++ b/VHD/hdl/ex_24_1_5_studentVersion.vhd @@ -0,0 +1,5 @@ +architecture studentVersion of ex_24_1_5 is +begin + speed <= (others => '0'); + done <= '0'; +end studentVersion; diff --git a/VHD/hdl/utils_pkg.vhd b/VHD/hdl/utils_pkg.vhd new file mode 100644 index 0000000..8e8a50b --- /dev/null +++ b/VHD/hdl/utils_pkg.vhd @@ -0,0 +1,5 @@ +PACKAGE utils IS + + function requiredBitNb (val : integer) return integer; + +END utils; diff --git a/VHD/hdl/utils_pkg_body.vhd b/VHD/hdl/utils_pkg_body.vhd new file mode 100644 index 0000000..7602583 --- /dev/null +++ b/VHD/hdl/utils_pkg_body.vhd @@ -0,0 +1,15 @@ +PACKAGE BODY utils IS + + function requiredBitNb (val : integer) return integer is + variable powerOfTwo, bitNb : integer; + begin + powerOfTwo := 1; + bitNb := 0; + while powerOfTwo <= val loop + powerOfTwo := 2 * powerOfTwo; + bitNb := bitNb + 1; + end loop; + return bitNb; + end requiredBitNb; + +END utils; diff --git a/VHD/hds/.hdlsidedata/_ex_10_2_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_10_2_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_10_2_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_10_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_10_4_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_10_4_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_10_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_10_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_10_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_1_1_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_1_1_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_1_1_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_1_3_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_1_3_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_1_3_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_1_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_1_4_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_1_4_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_1_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_1_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_1_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_2_1_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_2_1_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_2_1_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_2_2_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_2_2_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_2_2_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_2_3_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_2_3_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_2_3_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_2_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_2_4_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_2_4_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_13_2_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_13_2_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_13_2_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_1_1_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_1_1_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_1_1_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_1_2_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_1_2_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_1_2_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_1_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_1_4_RTL.vhd._fpf new file mode 100644 index 0000000..19d6635 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_1_4_RTL.vhd._fpf @@ -0,0 +1,4 @@ +INCLUDE list { + DEFAULT atom 1 +} +DIALECT atom VHDL_2002 diff --git a/VHD/hds/.hdlsidedata/_ex_14_1_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_1_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_1_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_2_1_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_2_1_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_2_1_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_2_2_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_2_2_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_2_2_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_2_3_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_2_3_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_2_3_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_2_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_2_4_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_2_4_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_14_2_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_14_2_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_14_2_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_15_2_3_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_15_2_3_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_15_2_3_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_1_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_1_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_1_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_1_studentVersion.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_1_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_2_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_2_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_2_studentVersion.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_2_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_3_entity.vhg._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_3_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_3_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_3_studentVersion.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_3_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_4_entity.vhg._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_4_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_4_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_4_studentVersion.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_4_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_5_entity.vhg._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_5_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_5_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_19_1_5_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_19_1_5_studentVersion.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_19_1_5_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_1_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_1_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_1_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_1_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_1_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_2_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_2_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_2_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_2_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_3_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_3_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_3_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_3_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_3_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_4_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_4_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_4_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_4_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_4_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_4_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_5_entity.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_5_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_5_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD/hds/.hdlsidedata/_ex_24_1_5_studentVersion.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_24_1_5_studentVersion.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_24_1_5_studentVersion.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD/hds/.hdlsidedata/_ex_uart_1_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_uart_1_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_uart_1_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_uart_2_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_uart_2_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_uart_2_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_uart_3_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_uart_3_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_uart_3_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_uart_4_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_uart_4_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_uart_4_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_ex_uart_5_RTL.vhd._fpf b/VHD/hds/.hdlsidedata/_ex_uart_5_RTL.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_ex_uart_5_RTL.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_utils_pkg.vhd._fpf b/VHD/hds/.hdlsidedata/_utils_pkg.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_utils_pkg.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.hdlsidedata/_utils_pkg_body.vhd._fpf b/VHD/hds/.hdlsidedata/_utils_pkg_body.vhd._fpf new file mode 100644 index 0000000..e69b3ef --- /dev/null +++ b/VHD/hds/.hdlsidedata/_utils_pkg_body.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_93 diff --git a/VHD/hds/.xrf/ex_24_1_1_entity.xrf b/VHD/hds/.xrf/ex_24_1_1_entity.xrf new file mode 100644 index 0000000..0b8178b --- /dev/null +++ b/VHD/hds/.xrf/ex_24_1_1_entity.xrf @@ -0,0 +1,30 @@ +DESIGN ex_24_1_1 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 57,0 17 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 89,0 18 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 262,0 19 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 267,0 20 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 272,0 21 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 1,0 24 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 1,0 25 0 diff --git a/VHD/hds/.xrf/ex_24_1_2_entity.xrf b/VHD/hds/.xrf/ex_24_1_2_entity.xrf new file mode 100644 index 0000000..0462a93 --- /dev/null +++ b/VHD/hds/.xrf/ex_24_1_2_entity.xrf @@ -0,0 +1,27 @@ +DESIGN ex_24_1_2 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 57,0 14 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 89,0 15 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 262,0 16 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 267,0 17 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 352,0 18 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 1,0 21 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 1,0 22 0 diff --git a/VHD/hds/.xrf/ex_24_1_3_entity.xrf b/VHD/hds/.xrf/ex_24_1_3_entity.xrf new file mode 100644 index 0000000..10f89ff --- /dev/null +++ b/VHD/hds/.xrf/ex_24_1_3_entity.xrf @@ -0,0 +1,27 @@ +DESIGN ex_24_1_3 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 262,0 18 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 267,0 19 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 272,0 20 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 400,0 21 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 1,0 24 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 1,0 25 0 diff --git a/VHD/hds/.xrf/ex_24_1_4_entity.xrf b/VHD/hds/.xrf/ex_24_1_4_entity.xrf new file mode 100644 index 0000000..f1827e2 --- /dev/null +++ b/VHD/hds/.xrf/ex_24_1_4_entity.xrf @@ -0,0 +1,30 @@ +DESIGN ex_24_1_4 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 57,0 14 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 262,0 15 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 267,0 16 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 272,0 17 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 329,0 18 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 334,0 19 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 1,0 22 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 1,0 23 0 diff --git a/VHD/hds/.xrf/ex_24_1_5_entity.xrf b/VHD/hds/.xrf/ex_24_1_5_entity.xrf new file mode 100644 index 0000000..4566ed2 --- /dev/null +++ b/VHD/hds/.xrf/ex_24_1_5_entity.xrf @@ -0,0 +1,30 @@ +DESIGN ex_24_1_5 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 13,0 13 1 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 262,0 17 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 267,0 18 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 272,0 19 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 334,0 20 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 390,0 21 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 1,0 24 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 1,0 25 0 diff --git a/VHD/hds/_ex_24_1_1._epf b/VHD/hds/_ex_24_1_1._epf new file mode 100644 index 0000000..61557e5 --- /dev/null +++ b/VHD/hds/_ex_24_1_1._epf @@ -0,0 +1,2 @@ +DEFAULT_ARCHITECTURE atom studentVersion +DEFAULT_FILE atom ex_24_1_1_studentVersion.vhd diff --git a/VHD/hds/ex_24_1_1/@r@t@l.vhd b/VHD/hds/ex_24_1_1/@r@t@l.vhd new file mode 100644 index 0000000..5dfae95 --- /dev/null +++ b/VHD/hds/ex_24_1_1/@r@t@l.vhd @@ -0,0 +1,7 @@ +architecture RTL of ex_07_1 is +begin + process(gainIn) + begin + gainOut <= resize(gainIn, gainOut'length) + shift_left(resize(gainIn, gainOut'length), 1); + end process; +end RTL; diff --git a/VHD/hds/ex_24_1_1/@r@t@l.vhd.info/structure.dh b/VHD/hds/ex_24_1_1/@r@t@l.vhd.info/structure.dh new file mode 100644 index 0000000..2c097aa --- /dev/null +++ b/VHD/hds/ex_24_1_1/@r@t@l.vhd.info/structure.dh @@ -0,0 +1,5 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +] +) diff --git a/VHD/hds/ex_24_1_1/default_view b/VHD/hds/ex_24_1_1/default_view new file mode 100644 index 0000000..e363de3 --- /dev/null +++ b/VHD/hds/ex_24_1_1/default_view @@ -0,0 +1,2 @@ +DefaultView = RTL.vhd +Top = false diff --git a/VHD/hds/ex_24_1_1/symbol.sb b/VHD/hds/ex_24_1_1/symbol.sb new file mode 100644 index 0000000..b09fddd --- /dev/null +++ b/VHD/hds/ex_24_1_1/symbol.sb @@ -0,0 +1,1625 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2006,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 151,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "position" +t "unsigned" +b "(counterBitNb-1 downto 0)" +o 2 +suid 2,0 +) +) +uid 152,0 +) +*3 (LogPort +port (LogicalPort +decl (Decl +n "en" +t "std_ulogic" +o 1 +suid 1,0 +) +) +uid 153,0 +) +*4 (RefLabelRowHdr +) +*5 (TitleRowHdr +) +*6 (FilterRowHdr +) +*7 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*8 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*9 (GroupColHdr +tm "GroupColHdrMgr" +) +*10 (NameColHdr +tm "NameColHdrMgr" +) +*11 (ModeColHdr +tm "ModeColHdrMgr" +) +*12 (TypeColHdr +tm "TypeColHdrMgr" +) +*13 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*14 (InitColHdr +tm "InitColHdrMgr" +) +*15 (EolColHdr +tm "EolColHdrMgr" +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "up_down" +t "std_ulogic" +o 3 +suid 2004,0 +) +) +uid 277,0 +) +*17 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 4 +suid 2005,0 +) +) +uid 279,0 +) +*18 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 5 +suid 2006,0 +) +) +uid 281,0 +) +] +) +pdm (PhysicalDM +uid 154,0 +optionalChildren [ +*19 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *20 (MRCItem +litem &1 +pos 5 +dimension 20 +) +uid 95,0 +optionalChildren [ +*21 (MRCItem +litem &4 +pos 0 +dimension 20 +uid 98,0 +) +*22 (MRCItem +litem &5 +pos 1 +dimension 23 +uid 100,0 +) +*23 (MRCItem +litem &6 +pos 2 +hidden 1 +dimension 20 +uid 102,0 +) +*24 (MRCItem +litem &2 +pos 1 +dimension 20 +uid 121,0 +) +*25 (MRCItem +litem &3 +pos 0 +dimension 20 +uid 122,0 +) +*26 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 278,0 +) +*27 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 280,0 +) +*28 (MRCItem +litem &18 +pos 4 +dimension 20 +uid 282,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 96,0 +optionalChildren [ +*29 (MRCItem +litem &7 +pos 0 +dimension 20 +uid 104,0 +) +*30 (MRCItem +litem &9 +pos 1 +dimension 50 +uid 108,0 +) +*31 (MRCItem +litem &10 +pos 2 +dimension 100 +uid 110,0 +) +*32 (MRCItem +litem &11 +pos 3 +dimension 50 +uid 112,0 +) +*33 (MRCItem +litem &12 +pos 4 +dimension 100 +uid 114,0 +) +*34 (MRCItem +litem &13 +pos 5 +dimension 100 +uid 116,0 +) +*35 (MRCItem +litem &14 +pos 6 +dimension 50 +uid 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(MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *51 (MRCItem +litem &37 +pos 1 +dimension 20 +) +uid 124,0 +optionalChildren [ +*52 (MRCItem +litem &38 +pos 0 +dimension 20 +uid 127,0 +) +*53 (MRCItem +litem &39 +pos 1 +dimension 23 +uid 129,0 +) +*54 (MRCItem +litem &40 +pos 2 +hidden 1 +dimension 20 +uid 131,0 +) +*55 (MRCItem +litem &49 +pos 0 +dimension 20 +uid 376,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 125,0 +optionalChildren [ +*56 (MRCItem +litem &41 +pos 0 +dimension 20 +uid 133,0 +) +*57 (MRCItem +litem &43 +pos 1 +dimension 50 +uid 137,0 +) +*58 (MRCItem +litem &44 +pos 2 +dimension 100 +uid 139,0 +) +*59 (MRCItem +litem &45 +pos 3 +dimension 100 +uid 141,0 +) +*60 (MRCItem +litem &46 +pos 4 +dimension 50 +uid 143,0 +) +*61 (MRCItem +litem &47 +pos 5 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+variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD\\hds\\ex_24_1_1" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD\\hds\\ex_24_1_1" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "ex_24_1_1" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value 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+value "/usr/opt/Modelsim/modeltech/bin" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "09:18:55" +) +(vvPair +variable "unit" +value "ex_19_1_1" +) +(vvPair +variable "user" +value "francois" +) +(vvPair +variable "version" +value "2018.1 (Build 12)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2019" +) +(vvPair +variable "yy" +value "19" +) +] +) +LanguageMgr "VhdlLangMgr" +uid 51,0 +optionalChildren [ +*61 (SymbolBody +uid 8,0 +optionalChildren [ +*62 (CptPort +uid 57,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 58,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,15625,32000,16375" +) +tg (CPTG +uid 59,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 60,0 +va (VaSet +font "courier,9,0" +) +xt "33000,15400,36500,16300" +st "motorOn" +blo "33000,16100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 61,0 +va (VaSet +font "courier,8,0" +) +xt "2000,6200,19000,7100" +st "motorOn : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "motorOn" +t "std_ulogic" +o 1 +suid 1,0 +) +) +) +*63 (CptPort +uid 89,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 158,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,15625,48750,16375" +) +tg (CPTG +uid 91,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 92,0 +va (VaSet +font "courier,9,0" +) +xt "44500,15400,47000,16300" +st "side1" +ju 2 +blo "47000,16100" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 93,0 +va (VaSet +font "courier,8,0" +) +xt "2000,7100,19000,8000" +st "side1 : OUT std_ulogic ;" +) +thePort (LogicalPort +m 1 +decl (Decl +n "side1" +t "std_ulogic" +o 2 +suid 2,0 +) +) +) +*64 (CptPort +uid 262,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 263,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,17625,32000,18375" +) +tg (CPTG +uid 264,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 265,0 +va (VaSet +font "courier,9,0" +) +xt "33000,17550,38500,18450" +st "right_left" +blo "33000,18250" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 266,0 +va (VaSet +font "courier,8,0" +) +xt "2000,8000,19000,8900" +st "right_left : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "right_left" +t "std_ulogic" +o 3 +suid 2004,0 +) +) +) +*65 (CptPort +uid 267,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 268,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "31250,19625,32000,20375" +) +tg (CPTG +uid 269,0 +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +uid 270,0 +va (VaSet +font "courier,9,0" +) +xt "33000,19550,34500,20450" +st "pwm" +blo "33000,20250" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 271,0 +va (VaSet +font "courier,8,0" +) +xt "2000,8900,19000,9800" +st "pwm : IN std_ulogic ;" +) +thePort (LogicalPort +decl (Decl +n "pwm" +t "std_ulogic" +o 4 +suid 2005,0 +) +) +) +*66 (CptPort +uid 352,0 +ps "OnEdgeStrategy" +shape (Triangle +uid 353,0 +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "48000,17625,48750,18375" +) +tg (CPTG +uid 354,0 +ps "CptPortTextPlaceStrategy" +stg "RightVerticalLayoutStrategy" +f (Text +uid 355,0 +va (VaSet +font "courier,9,0" +) +xt "44500,17550,47000,18450" +st "side2" +ju 2 +blo "47000,18250" +tm "CptPortNameMgr" +) +) +dt (MLText +uid 356,0 +va (VaSet +font "courier,8,0" +) +xt "2000,9800,18000,10700" +st "side2 : OUT std_ulogic " +) +thePort (LogicalPort +m 1 +decl (Decl +n "side2" +t "std_ulogic" +o 5 +suid 2007,0 +) +) +) +] +shape (Rectangle +uid 88,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +bg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "32000,12000,48000,24000" +) +oxt "15000,6000,35000,26000" +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "courier,9,1" +) +xt "32600,23800,34100,24700" +st "VHD" +blo "32600,24500" +) +second (Text +uid 12,0 +va (VaSet +font "courier,9,1" +) +xt "32600,24700,37100,25600" +st "ex_19_1_1" +blo "32600,25400" +) +) +gi *67 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +font "courier,8,0" +) +xt "32000,27400,42500,28300" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +sTC 0 +) +portVis (PortSigDisplay +sTC 0 +sF 0 +) +) +*68 (Grouping +uid 16,0 +optionalChildren [ +*69 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,52400,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*70 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56800,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*71 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,52400,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*72 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,35800,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*73 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,66400,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*74 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,72800,45000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*75 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "38000,44500,47000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*76 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,35200,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*77 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,35800,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*78 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,48800,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *79 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*80 (Text +uid 49,0 +va (VaSet +font "courier,8,1" +) +xt "0,0,6500,900" +st "Package List" +blo "0,700" +) +*81 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,18600,4000" +st "LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all;" +tm "PackageList" +) +] +) +windowSize "278,91,1536,937" +viewArea "-1100,-1100,68245,44192" +cachedDiagramExtent "0,0,73000,49000" +pageSetupInfo (PageSetupInfo +ptrCmd "" +toPrinter 1 +xMargin 48 +yMargin 48 +paperWidth 595 +paperHeight 842 +unixPaperWidth 595 +unixPaperHeight 842 +windowsPaperWidth 761 +windowsPaperHeight 1077 +paperType "A4 (210mm x 297mm)" +unixPaperName "A4 (210mm x 297mm)" +windowsPaperName "A4" +exportedDirectories [ +"$HDS_PROJECT_DIR/HTMLExport" +] +boundaryWidth 0 +) +hasePageBreakOrigin 1 +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,9,0" +) +xt "200,200,2200,1100" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "courier,8,0" +) +xt "450,2150,1450,3050" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "courier,9,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "courier,9,1" +) +xt "22600,14800,27400,16000" +st "" +blo "22600,15800" +) +second (Text +va (VaSet +font "courier,9,1" +) +xt "22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *82 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,9,0" +) +xt "0,750,1800,1950" +st "In0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +font "courier,9,0" +) +xt "0,750,3600,1950" +st "Buffer0" +blo "0,1750" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "courier,8,0" +) +) +thePort (LogicalPort +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *83 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "courier,8,1" +) +xt "0,4400,6500,5300" +st "Declarations" +blo "0,5100" +) +portLabel (Text +uid 3,0 +va (VaSet +font "courier,8,1" +) +xt "0,5300,3000,6200" +st "Ports:" +blo "0,6000" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "courier,8,1" +) +xt "0,10700,2500,11600" +st "User:" +blo "0,11400" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "courier,8,1" +) +xt "0,4400,7500,5300" +st "Internal User:" +blo "0,5100" +) +externalText (MLText +uid 5,0 +va (VaSet +font "courier,8,0" +) +xt "2000,11600,2000,11600" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "courier,8,0" +) +xt "0,4400,0,4400" +tm "SyDeclarativeTextMgr" +) +) +lastUid 358,0 +activeModelName "Symbol" +) diff --git a/VHD/hds/ex_24_1_3/@r@t@l.vhd b/VHD/hds/ex_24_1_3/@r@t@l.vhd new file mode 100644 index 0000000..5dfae95 --- /dev/null +++ b/VHD/hds/ex_24_1_3/@r@t@l.vhd @@ -0,0 +1,7 @@ +architecture RTL of ex_07_1 is +begin + process(gainIn) + begin + gainOut <= resize(gainIn, gainOut'length) + shift_left(resize(gainIn, gainOut'length), 1); + end process; +end RTL; diff --git a/VHD/hds/ex_24_1_3/@r@t@l.vhd.info/structure.dh b/VHD/hds/ex_24_1_3/@r@t@l.vhd.info/structure.dh new file mode 100644 index 0000000..2c097aa --- /dev/null +++ b/VHD/hds/ex_24_1_3/@r@t@l.vhd.info/structure.dh @@ -0,0 +1,5 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +] +) diff --git a/VHD/hds/ex_24_1_3/default_view b/VHD/hds/ex_24_1_3/default_view new file mode 100644 index 0000000..e363de3 --- /dev/null +++ b/VHD/hds/ex_24_1_3/default_view @@ -0,0 +1,2 @@ +DefaultView = RTL.vhd +Top = false diff --git a/VHD/hds/ex_24_1_3/symbol.sb b/VHD/hds/ex_24_1_3/symbol.sb new file mode 100644 index 0000000..386126e --- /dev/null +++ b/VHD/hds/ex_24_1_3/symbol.sb @@ -0,0 +1,1593 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2007,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 151,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +*14 (LogPort +port (LogicalPort +decl (Decl +n "testMode" +t "std_ulogic" +o 1 +suid 2004,0 +) +) +uid 277,0 +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 2 +suid 2005,0 +) +) +uid 279,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "reset" +t "std_ulogic" +o 3 +suid 2006,0 +) +) +uid 281,0 +) +*17 (LogPort +port (LogicalPort +m 1 +decl (Decl +n "pwmEn" +t "std_ulogic" +o 4 +suid 2007,0 +) +) +uid 405,0 +) +] +) +pdm (PhysicalDM +uid 154,0 +optionalChildren [ +*18 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "courier,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "courier,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "courier,10,0" +) +emptyMRCItem *19 (MRCItem +litem &1 +pos 4 +dimension 20 +) +uid 95,0 +optionalChildren [ +*20 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 98,0 +) +*21 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 100,0 +) +*22 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 102,0 +) +*23 (MRCItem +litem &14 +pos 0 +dimension 20 +uid 278,0 +) +*24 (MRCItem +litem &15 +pos 1 +dimension 20 +uid 280,0 +) +*25 (MRCItem +litem &16 +pos 2 +dimension 20 +uid 282,0 +) +*26 (MRCItem +litem &17 +pos 3 +dimension 20 +uid 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resize(gainIn, gainOut'length) + shift_left(resize(gainIn, gainOut'length), 1); + end process; +end RTL; diff --git a/VHD/hds/ex_24_1_4/@r@t@l.vhd.info/structure.dh b/VHD/hds/ex_24_1_4/@r@t@l.vhd.info/structure.dh new file mode 100644 index 0000000..2c097aa --- /dev/null +++ b/VHD/hds/ex_24_1_4/@r@t@l.vhd.info/structure.dh @@ -0,0 +1,5 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +] +) diff --git a/VHD/hds/ex_24_1_4/default_view b/VHD/hds/ex_24_1_4/default_view new file mode 100644 index 0000000..e363de3 --- /dev/null +++ b/VHD/hds/ex_24_1_4/default_view @@ -0,0 +1,2 @@ +DefaultView = RTL.vhd +Top = false diff --git a/VHD/hds/ex_24_1_4/symbol.sb b/VHD/hds/ex_24_1_4/symbol.sb new file mode 100644 index 0000000..1b1e5de --- /dev/null +++ b/VHD/hds/ex_24_1_4/symbol.sb @@ -0,0 +1,1677 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] +libraryRefs [ +"ieee" +] +) +version "26.1" +appVersion "2018.1 (Build 12)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +ordering 1 +suid 2008,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 151,0 +optionalChildren [ +*2 (LogPort +port (LogicalPort +decl (Decl +n "A" +t "std_ulogic" +o 1 +suid 1,0 +) +) +uid 153,0 +) +*3 (RefLabelRowHdr +) +*4 (TitleRowHdr +) +*5 (FilterRowHdr +) +*6 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*7 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*8 (GroupColHdr +tm "GroupColHdrMgr" +) +*9 (NameColHdr +tm "NameColHdrMgr" +) +*10 (ModeColHdr +tm "ModeColHdrMgr" +) +*11 (TypeColHdr +tm "TypeColHdrMgr" +) +*12 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*13 (InitColHdr +tm "InitColHdrMgr" +) +*14 (EolColHdr +tm "EolColHdrMgr" +) +*15 (LogPort +port (LogicalPort +decl (Decl +n "B" +t "std_ulogic" +o 2 +suid 2004,0 +) +) +uid 277,0 +) +*16 (LogPort +port (LogicalPort +decl (Decl +n "clock" +t "std_ulogic" +o 3 +suid 2005,0 +) +) +uid 279,0 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+(vvPair +variable "HDLDir" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hdl" +) +(vvPair +variable "HDSDir" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds" +) +(vvPair +variable "SideDataDesignDir" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_4/symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_4/symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_%(view)_config" +) +(vvPair +variable "d" +value "/home/francois/Documents/HEVs/SEm/Examens/SEm_exams/Prefs/../VHD/hds/ex_19_1_4" +) +(vvPair +variable "d_logical" +value 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gainOut'length) + shift_left(resize(gainIn, gainOut'length), 1); + end process; +end RTL; diff --git a/VHD/hds/ex_24_1_5/@r@t@l.vhd.info/structure.dh b/VHD/hds/ex_24_1_5/@r@t@l.vhd.info/structure.dh new file mode 100644 index 0000000..2c097aa --- /dev/null +++ b/VHD/hds/ex_24_1_5/@r@t@l.vhd.info/structure.dh @@ -0,0 +1,5 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +packageRefs [ +] +) diff --git a/VHD/hds/ex_24_1_5/default_view b/VHD/hds/ex_24_1_5/default_view new file mode 100644 index 0000000..e363de3 --- /dev/null +++ b/VHD/hds/ex_24_1_5/default_view @@ -0,0 +1,2 @@ +DefaultView = RTL.vhd +Top = false diff --git a/VHD/hds/ex_24_1_5/symbol.sb b/VHD/hds/ex_24_1_5/symbol.sb new file mode 100644 index 0000000..90bfc1f --- /dev/null +++ b/VHD/hds/ex_24_1_5/symbol.sb @@ -0,0 +1,1640 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +) +] 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+-- VHDL Architecture VHD_test.tb_24_1_1.struct +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:02:54 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_24_1_1 IS + + -- Architecture declarations + constant positionBitNb : positive := 8; + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL en : std_ulogic; + SIGNAL position : unsigned(positionBitNb-1 DOWNTO 0); + SIGNAL reset : std_ulogic; + SIGNAL up_down : std_ulogic; + + + -- Component Declarations + COMPONENT ex_24_1_1 + GENERIC ( + counterBitNb : positive := 8 + ); + PORT ( + en : IN std_ulogic ; + position : OUT unsigned (counterBitNb-1 DOWNTO 0); + up_down : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_24_1_1 USE ENTITY VHD.ex_24_1_1; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + process + constant stepDelay: time := 1 us; + begin + en <= '0'; + up_down <= '1'; + wait for stepDelay; + for index in 0 to 10 loop + en <= '1', '0' after clockPeriod; + position_int <= position_int + 1; + wait for stepDelay; + end loop; + up_down <= '0'; + for index in 10 downto 0 loop + en <= '1', '0' after clockPeriod; + position_int <= position_int - 1; + wait for stepDelay; + end loop; + wait; + end process; + + + -- Instance port mappings. + I_dut : ex_24_1_1 + GENERIC MAP ( + counterBitNb => positionBitNb + ) + PORT MAP ( + en => en, + position => position, + up_down => up_down, + clock => clock, + reset => reset + ); + +END struct; diff --git a/VHD_test/hdl/tb_24_1_2_entity.vhd b/VHD_test/hdl/tb_24_1_2_entity.vhd new file mode 100644 index 0000000..99a2f79 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_2_entity.vhd @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_24_1_2.symbol +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:24 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY tb_24_1_2 IS +-- Declarations + +END tb_24_1_2 ; + diff --git a/VHD_test/hdl/tb_24_1_2_struct.vhd b/VHD_test/hdl/tb_24_1_2_struct.vhd new file mode 100644 index 0000000..747163f --- /dev/null +++ b/VHD_test/hdl/tb_24_1_2_struct.vhd @@ -0,0 +1,85 @@ +-- +-- VHDL Architecture VHD_test.tb_24_1_2.struct +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:25 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_24_1_2 IS + + -- Architecture declarations + constant pwmFrequency : real := 1.0E6; + constant pwmPeriod : time := (1.0/pwmFrequency) * 1 sec; + signal sPwm : std_uLogic := '1'; + + -- Internal signal declarations + SIGNAL motorOn : std_ulogic; + SIGNAL pwm : std_ulogic; + SIGNAL right_left : std_ulogic; + SIGNAL side1 : std_ulogic; + SIGNAL side2 : std_ulogic; + + + -- Component Declarations + COMPONENT ex_24_1_2 + PORT ( + motorOn : IN std_ulogic ; + side1 : OUT std_ulogic ; + right_left : IN std_ulogic ; + pwm : IN std_ulogic ; + side2 : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_24_1_2 USE ENTITY VHD.ex_24_1_2; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + sPwm <= not sPwm after pwmPeriod/2; + pwm <= sPwm; + + process + constant testDelay: time := 10 us; + begin + motorOn <= '0'; + right_left <= '1'; + wait for testDelay; + + motorOn <= '1'; + wait for testDelay; + + right_left <= '0'; + wait for testDelay; + + motorOn <= '0'; + wait for testDelay; + + wait; + end process; + + + + -- Instance port mappings. + I_dut : ex_24_1_2 + PORT MAP ( + motorOn => motorOn, + side1 => side1, + right_left => right_left, + pwm => pwm, + side2 => side2 + ); + +END struct; diff --git a/VHD_test/hdl/tb_24_1_3_entity.vhg b/VHD_test/hdl/tb_24_1_3_entity.vhg new file mode 100644 index 0000000..6278ab2 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_3_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_19_1_3.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 09:36:25 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- + + +ENTITY tb_19_1_3 IS +-- Declarations + +END tb_19_1_3 ; + diff --git a/VHD_test/hdl/tb_24_1_3_struct.vhg b/VHD_test/hdl/tb_24_1_3_struct.vhg new file mode 100644 index 0000000..4e3ab46 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_3_struct.vhg @@ -0,0 +1,77 @@ +-- +-- VHDL Architecture VHD_test.tb_19_1_3.struct +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 12:43:24 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_19_1_3 IS + + -- Architecture declarations + constant positionBitNb : positive := 8; + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL pwmEn : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL testMode : std_ulogic; + + + -- Component Declarations + COMPONENT ex_19_1_3 + GENERIC ( + timerBitNb : positive := 8; + testModeBitNb : positive := 1 + ); + PORT ( + testMode : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + pwmEn : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_19_1_3 USE ENTITY VHD.ex_19_1_3; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + testMode <= '1', '0' after 100*clockPeriod; + + + -- Instance port mappings. + I_dut : ex_19_1_3 + GENERIC MAP ( + timerBitNb => 8, + testModeBitNb => 1 + ) + PORT MAP ( + testMode => testMode, + clock => clock, + reset => reset, + pwmEn => pwmEn + ); + +END struct; diff --git a/VHD_test/hdl/tb_24_1_4_entity.vhg b/VHD_test/hdl/tb_24_1_4_entity.vhg new file mode 100644 index 0000000..4326c2b --- /dev/null +++ b/VHD_test/hdl/tb_24_1_4_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_19_1_4.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 12:48:46 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- + + +ENTITY tb_19_1_4 IS +-- Declarations + +END tb_19_1_4 ; + diff --git a/VHD_test/hdl/tb_24_1_4_struct.vhg b/VHD_test/hdl/tb_24_1_4_struct.vhg new file mode 100644 index 0000000..6b3c868 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_4_struct.vhg @@ -0,0 +1,101 @@ +-- +-- VHDL Architecture VHD_test.tb_19_1_4.struct +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 12:59:54 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_19_1_4 IS + + -- Architecture declarations + constant positionBitNb : positive := 8; + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL A : std_ulogic; + SIGNAL B : std_ulogic; + SIGNAL clock : std_ulogic; + SIGNAL dir : std_ulogic; + SIGNAL en : std_ulogic; + SIGNAL reset : std_ulogic; + + + -- Component Declarations + COMPONENT ex_19_1_4 + PORT ( + A : IN std_ulogic ; + B : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + en : OUT std_ulogic ; + dir : OUT std_ulogic + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_19_1_4 USE ENTITY VHD.ex_19_1_4; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + process + constant stepDelay: time := 1 us; + begin + wait for stepDelay; + for index in 0 to 10 loop + position_int <= position_int + 1; + wait for stepDelay; + end loop; + for index in 10 downto 0 loop + position_int <= position_int - 1; + wait for stepDelay; + end loop; + wait; + end process; + + process(position_int) + begin + case to_integer(to_unsigned(position_int, 2)) is + when 0 => A <= '0'; B <= '0'; + when 1 => A <= '1'; B <= '0'; + when 2 => A <= '1'; B <= '1'; + when 3 => A <= '0'; B <= '1'; + when others => null; + end case; + end process; + + + + + -- Instance port mappings. + I_dut : ex_19_1_4 + PORT MAP ( + A => A, + B => B, + clock => clock, + reset => reset, + en => en, + dir => dir + ); + +END struct; diff --git a/VHD_test/hdl/tb_24_1_5_entity.vhg b/VHD_test/hdl/tb_24_1_5_entity.vhg new file mode 100644 index 0000000..5108ba9 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_5_entity.vhg @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_19_1_5.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:03:49 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- + + +ENTITY tb_19_1_5 IS +-- Declarations + +END tb_19_1_5 ; + diff --git a/VHD_test/hdl/tb_24_1_5_struct.vhg b/VHD_test/hdl/tb_24_1_5_struct.vhg new file mode 100644 index 0000000..bb34fd7 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_5_struct.vhg @@ -0,0 +1,94 @@ +-- +-- VHDL Architecture VHD_test.tb_19_1_5.struct +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:50:24 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_19_1_5 IS + + -- Architecture declarations + constant speedBitNb : positive := 8; + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL done : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0); + SIGNAL start : std_ulogic; + + + -- Component Declarations + COMPONENT ex_19_1_5 + GENERIC ( + speedBitNb : positive + ); + PORT ( + start : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + done : OUT std_ulogic ; + speed : OUT unsigned (speedBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_19_1_5 USE ENTITY VHD.ex_19_1_5; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + process + constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod; + begin + start <= '0'; + + wait for testDelay; + start <= '1', '0' after clockPeriod; + + wait for testDelay; + start <= '1', '0' after clockPeriod; + + wait; + end process; + + + + + + + -- Instance port mappings. + I_dut : ex_19_1_5 + GENERIC MAP ( + speedBitNb => speedBitNb + ) + PORT MAP ( + start => start, + clock => clock, + reset => reset, + done => done, + speed => speed + ); + +END struct; diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_1_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_1_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_1_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_1_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_1_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_2_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_2_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_2_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_2_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_4_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_4_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_4_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_4_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_4_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_4_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_5_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_5_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_5_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_1_5_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_1_5_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_1_5_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_1_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_1_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_1_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_1_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_1_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_2_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_2_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_2_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_2_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_3_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_3_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_3_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_3_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_3_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_4_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_4_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_4_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_4_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_4_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_4_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_5_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_5_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_5_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_18_2_5_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_18_2_5_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_18_2_5_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_1_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_1_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_1_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_1_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_1_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_2_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_2_entity.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_2_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_2_struct.vhd._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_2_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_3_entity.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_3_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_3_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_3_struct.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_3_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_3_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_4_entity.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_4_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_4_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_4_struct.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_4_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_4_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_5_entity.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_5_entity.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_5_entity.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_19_1_5_struct.vhg._fpf b/VHD_test/hds/.hdlsidedata/_tb_19_1_5_struct.vhg._fpf new file mode 100644 index 0000000..3eea781 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_19_1_5_struct.vhg._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_ANY diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_1_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_1_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_1_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_1_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_1_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_1_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_2_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_2_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_2_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_2_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_2_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_2_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_3_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_3_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_3_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_3_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_3_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_3_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_4_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_4_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_4_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_4_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_4_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_4_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_5_entity.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_5_entity.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_5_entity.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.hdlsidedata/_tb_24_1_5_struct.vhd._fpf b/VHD_test/hds/.hdlsidedata/_tb_24_1_5_struct.vhd._fpf new file mode 100644 index 0000000..376bb70 --- /dev/null +++ b/VHD_test/hds/.hdlsidedata/_tb_24_1_5_struct.vhd._fpf @@ -0,0 +1 @@ +DIALECT atom VHDL_2008 diff --git a/VHD_test/hds/.xrf/tb_24_1_1_entity.xrf b/VHD_test/hds/.xrf/tb_24_1_1_entity.xrf new file mode 100644 index 0000000..a4c166e --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_1_entity.xrf @@ -0,0 +1,12 @@ +DESIGN tb_24_1_1 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN tb_24_1_1 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN tb_24_1_1 +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN tb_24_1_1 +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/VHD_test/hds/.xrf/tb_24_1_1_struct.xrf b/VHD_test/hds/.xrf/tb_24_1_1_struct.xrf new file mode 100644 index 0000000..b16f319 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_1_struct.xrf @@ -0,0 +1,104 @@ +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1,0 18 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 18 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1122,0 27 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1272,0 28 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1098,0 29 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1130,0 30 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1280,0 31 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 32 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 33 +LIBRARY VHD +DESIGN ex_24_1_1 +VIEW student@version +GRAPHIC 1659,0 35 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 14,0 36 1 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 57,0 40 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 89,0 41 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 262,0 42 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 267,0 43 0 +DESIGN ex_24_1_1 +VIEW symbol.sb +GRAPHIC 272,0 44 0 +LIBRARY VHD_test +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 47 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1659,0 50 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 53 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 445,0 56 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 80 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 81 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1659,0 83 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1666,0 84 1 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1274,0 88 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1100,0 89 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1282,0 90 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1124,0 91 0 +DESIGN tb_24_1_1 +VIEW struct.bd +GRAPHIC 1132,0 92 0 +DESIGN tb_24_1_1 +VIEW struct.bd +NO_GRAPHIC 95 diff --git a/VHD_test/hds/.xrf/tb_24_1_2_entity.xrf b/VHD_test/hds/.xrf/tb_24_1_2_entity.xrf new file mode 100644 index 0000000..a1d39d3 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_2_entity.xrf @@ -0,0 +1,12 @@ +DESIGN tb_24_1_2 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN tb_24_1_2 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN tb_24_1_2 +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN tb_24_1_2 +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/VHD_test/hds/.xrf/tb_24_1_2_struct.xrf b/VHD_test/hds/.xrf/tb_24_1_2_struct.xrf new file mode 100644 index 0000000..4c52bc6 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_2_struct.xrf @@ -0,0 +1,98 @@ +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1,0 18 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 18 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1370,0 23 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1386,0 24 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1378,0 25 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1362,0 26 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1354,0 27 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 28 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 29 +LIBRARY VHD +DESIGN ex_24_1_2 +VIEW student@version +GRAPHIC 1519,0 31 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 57,0 33 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 89,0 34 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 262,0 35 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 267,0 36 0 +DESIGN ex_24_1_2 +VIEW symbol.sb +GRAPHIC 352,0 37 0 +LIBRARY VHD_test +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 40 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1519,0 43 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 46 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 445,0 49 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 72 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 73 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1519,0 75 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1372,0 77 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1364,0 78 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1380,0 79 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1388,0 80 0 +DESIGN tb_24_1_2 +VIEW struct.bd +GRAPHIC 1356,0 81 0 +DESIGN tb_24_1_2 +VIEW struct.bd +NO_GRAPHIC 84 diff --git a/VHD_test/hds/.xrf/tb_24_1_3_entity.xrf b/VHD_test/hds/.xrf/tb_24_1_3_entity.xrf new file mode 100644 index 0000000..633fb89 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_3_entity.xrf @@ -0,0 +1,12 @@ +DESIGN tb_24_1_3 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN tb_24_1_3 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN tb_24_1_3 +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN tb_24_1_3 +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/VHD_test/hds/.xrf/tb_24_1_3_struct.xrf b/VHD_test/hds/.xrf/tb_24_1_3_struct.xrf new file mode 100644 index 0000000..8e768c7 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_3_struct.xrf @@ -0,0 +1,95 @@ +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1,0 18 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 18 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1122,0 27 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1503,0 28 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1130,0 29 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1511,0 30 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 31 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 32 +LIBRARY VHD +DESIGN ex_24_1_3 +VIEW student@version +GRAPHIC 1601,0 34 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 14,0 35 1 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 262,0 40 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 267,0 41 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 272,0 42 0 +DESIGN ex_24_1_3 +VIEW symbol.sb +GRAPHIC 400,0 43 0 +LIBRARY VHD_test +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 46 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1601,0 49 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 52 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 445,0 55 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 61 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 62 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1601,0 64 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1608,0 65 1 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1513,0 70 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1124,0 71 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1132,0 72 0 +DESIGN tb_24_1_3 +VIEW struct.bd +GRAPHIC 1505,0 73 0 +DESIGN tb_24_1_3 +VIEW struct.bd +NO_GRAPHIC 76 diff --git a/VHD_test/hds/.xrf/tb_24_1_4_entity.xrf b/VHD_test/hds/.xrf/tb_24_1_4_entity.xrf new file mode 100644 index 0000000..1236155 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_4_entity.xrf @@ -0,0 +1,12 @@ +DESIGN tb_24_1_4 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN tb_24_1_4 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN tb_24_1_4 +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN tb_24_1_4 +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/VHD_test/hds/.xrf/tb_24_1_4_struct.xrf b/VHD_test/hds/.xrf/tb_24_1_4_struct.xrf new file mode 100644 index 0000000..6128f6f --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_4_struct.xrf @@ -0,0 +1,107 @@ +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1,0 18 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 18 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1106,0 25 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1114,0 26 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1122,0 27 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1280,0 28 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1288,0 29 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1130,0 30 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 31 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 32 +LIBRARY VHD +DESIGN ex_24_1_4 +VIEW student@version +GRAPHIC 1495,0 34 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 57,0 36 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 262,0 37 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 267,0 38 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 272,0 39 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 329,0 40 0 +DESIGN ex_24_1_4 +VIEW symbol.sb +GRAPHIC 334,0 41 0 +LIBRARY VHD_test +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 44 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1495,0 47 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 50 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 445,0 53 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 85 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 86 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1495,0 88 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1108,0 90 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1116,0 91 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1124,0 92 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1132,0 93 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1290,0 94 0 +DESIGN tb_24_1_4 +VIEW struct.bd +GRAPHIC 1282,0 95 0 +DESIGN tb_24_1_4 +VIEW struct.bd +NO_GRAPHIC 98 diff --git a/VHD_test/hds/.xrf/tb_24_1_5_entity.xrf b/VHD_test/hds/.xrf/tb_24_1_5_entity.xrf new file mode 100644 index 0000000..d6ccaa5 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_5_entity.xrf @@ -0,0 +1,12 @@ +DESIGN tb_24_1_5 +VIEW symbol.sb +NO_GRAPHIC 0 +DESIGN tb_24_1_5 +VIEW symbol.sb +GRAPHIC 50,0 8 0 +DESIGN tb_24_1_5 +VIEW symbol.sb +GRAPHIC 1,0 11 0 +DESIGN tb_24_1_5 +VIEW symbol.sb +GRAPHIC 1,0 12 0 diff --git a/VHD_test/hds/.xrf/tb_24_1_5_struct.xrf b/VHD_test/hds/.xrf/tb_24_1_5_struct.xrf new file mode 100644 index 0000000..ca8d440 --- /dev/null +++ b/VHD_test/hds/.xrf/tb_24_1_5_struct.xrf @@ -0,0 +1,104 @@ +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 142,0 9 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 12 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 0,0 15 2 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1,0 18 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 18 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1122,0 27 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1498,0 28 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1130,0 29 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1506,0 30 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1514,0 31 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 32 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 33 +LIBRARY VHD +DESIGN ex_24_1_5 +VIEW student@version +GRAPHIC 1581,0 35 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 14,0 36 1 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 262,0 40 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 267,0 41 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 272,0 42 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 334,0 43 0 +DESIGN ex_24_1_5 +VIEW symbol.sb +GRAPHIC 390,0 44 0 +LIBRARY VHD_test +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 47 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1581,0 50 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 53 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 445,0 56 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 78 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 79 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1581,0 81 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1588,0 82 1 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1516,0 86 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1124,0 87 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1132,0 88 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1500,0 89 0 +DESIGN tb_24_1_5 +VIEW struct.bd +GRAPHIC 1508,0 90 0 +DESIGN tb_24_1_5 +VIEW struct.bd +NO_GRAPHIC 93 diff --git a/VHD_test/hds/_tb_24_1_1._epf b/VHD_test/hds/_tb_24_1_1._epf new file mode 100644 index 0000000..a104438 --- /dev/null +++ b/VHD_test/hds/_tb_24_1_1._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom tb_24_1_1/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/VHD_test/hds/_tb_24_1_2._epf b/VHD_test/hds/_tb_24_1_2._epf new file mode 100644 index 0000000..91b401a --- /dev/null +++ b/VHD_test/hds/_tb_24_1_2._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom tb_24_1_2/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/VHD_test/hds/_tb_24_1_3._epf b/VHD_test/hds/_tb_24_1_3._epf new file mode 100644 index 0000000..6810fc2 --- /dev/null +++ b/VHD_test/hds/_tb_24_1_3._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom tb_24_1_3/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/VHD_test/hds/_tb_24_1_4._epf b/VHD_test/hds/_tb_24_1_4._epf new file mode 100644 index 0000000..40cdcee --- /dev/null +++ b/VHD_test/hds/_tb_24_1_4._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom tb_24_1_4/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/VHD_test/hds/_tb_24_1_5._epf b/VHD_test/hds/_tb_24_1_5._epf new file mode 100644 index 0000000..26941e5 --- /dev/null +++ b/VHD_test/hds/_tb_24_1_5._epf @@ -0,0 +1,2 @@ +DEFAULT_FILE atom tb_24_1_5/struct.bd +DEFAULT_ARCHITECTURE atom struct diff --git a/VHD_test/hds/tb_24_1_1/_struct.bd._fpf b/VHD_test/hds/tb_24_1_1/_struct.bd._fpf new file mode 100644 index 0000000..6f7cd54 --- /dev/null +++ b/VHD_test/hds/tb_24_1_1/_struct.bd._fpf @@ -0,0 +1,16 @@ +ARCHITECTURES list { + {tb_18_2_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_24_1_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/VHD_test/hds/tb_24_1_1/default_view b/VHD_test/hds/tb_24_1_1/default_view new file mode 100644 index 0000000..2ba0264 --- /dev/null +++ b/VHD_test/hds/tb_24_1_1/default_view @@ -0,0 +1,2 @@ +DefaultView = struct.bd +Top = false diff --git a/VHD_test/hds/tb_24_1_1/struct.bd b/VHD_test/hds/tb_24_1_1/struct.bd new file mode 100644 index 0000000..eff2877 --- /dev/null +++ b/VHD_test/hds/tb_24_1_1/struct.bd @@ -0,0 +1,2764 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_dut" +duLibraryName "VHD" +duName "ex_24_1_1" +elements [ +(GiElement +name "counterBitNb" +type "positive" +value "positionBitNb" +) +] +mwi 0 +uid 1659,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_1" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:02:54" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_1" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:02:54" +) +(vvPair +variable "unit" +value "tb_24_1_1" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,54000,61000,55000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,54000,56700,55000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 115,0 +shape (Rectangle +uid 116,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,50000,65000,51000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 117,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,50000,64200,51000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*4 (CommentText +uid 118,0 +shape (Rectangle +uid 119,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,52000,61000,53000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 120,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,52000,54200,53000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*5 (CommentText +uid 121,0 +shape (Rectangle +uid 122,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,52000,44000,53000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 123,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "40200,52000,42300,53000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*6 (CommentText +uid 124,0 +shape (Rectangle +uid 125,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,51000,81000,55000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 126,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,51200,70600,52200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*7 (CommentText +uid 127,0 +shape (Rectangle +uid 128,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "65000,50000,81000,51000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 129,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "65200,50000,75400,51000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*8 (CommentText +uid 130,0 +shape (Rectangle +uid 131,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,50000,61000,52000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 132,0 +va (VaSet +fg "32768,0,0" +) +xt "47000,50500,54000,51500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*9 (CommentText +uid 133,0 +shape (Rectangle +uid 134,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,53000,44000,54000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 135,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "40200,53000,42300,54000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 136,0 +shape (Rectangle +uid 137,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,54000,44000,55000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 138,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "40200,54000,42900,55000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 139,0 +shape (Rectangle +uid 140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,53000,61000,54000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,53000,54400,54000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 111,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "40000,50000,81000,55000" +) +oxt "14000,66000,55000,71000" +) +*12 (HdlText +uid 445,0 +optionalChildren [ +*13 (EmbeddedText +uid 450,0 +commentText (CommentText +uid 451,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 452,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "7000,22000,37000,34000" +) +oxt "0,0,18000,5000" +text (MLText +uid 453,0 +va (VaSet +) +xt "7200,22200,25400,34200" +st " +reset <= '1', '0' after 2*clockPeriod; +sClock <= not sClock after clockPeriod/2; +clock <= transport sClock after clockPeriod*9/10; + +process + constant stepDelay: time := 1 us; +begin + en <= '0'; + up_down <= '1'; + wait for stepDelay; + for index in 0 to 10 loop + en <= '1', '0' after clockPeriod; + position_int <= position_int + 1; + wait for stepDelay; + end loop; + up_down <= '0'; + for index in 10 downto 0 loop + en <= '1', '0' after clockPeriod; + position_int <= position_int - 1; + wait for stepDelay; + end loop; + wait; +end process; + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 12000 +visibleWidth 30000 +) +) +) +] +shape (Rectangle +uid 446,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "6000,21000,38000,35000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 447,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*14 (Text +uid 448,0 +va (VaSet +) +xt "6400,35000,8000,36000" +st "eb1" +blo "6400,35800" +tm "HdlTextNameMgr" +) +*15 (Text +uid 449,0 +va (VaSet +) +xt "6400,36000,7200,37000" +st "1" +blo "6400,36800" +tm "HdlTextNumberMgr" +) +] +) +) +*16 (Net +uid 1098,0 +decl (Decl +n "position" +t "unsigned" +b "(positionBitNb-1 downto 0)" +o 3 +suid 8,0 +) +declText (MLText +uid 1099,0 +va (VaSet +) +xt "2000,17800,21800,18800" +st "SIGNAL position : unsigned(positionBitNb-1 downto 0)" +) +) +*17 (Net +uid 1122,0 +decl (Decl +n "clock" +t "std_ulogic" +o 1 +suid 11,0 +) +declText (MLText +uid 1123,0 +va (VaSet +) +xt "2000,15800,12600,16800" +st "SIGNAL clock : std_ulogic" +) +) +*18 (Net +uid 1130,0 +decl (Decl +n "reset" +t "std_ulogic" +o 4 +suid 12,0 +) +declText (MLText +uid 1131,0 +va (VaSet +) +xt "2000,18800,12500,19800" +st "SIGNAL reset : std_ulogic" +) +) +*19 (Net +uid 1272,0 +decl (Decl +n "en" +t "std_ulogic" +o 2 +suid 13,0 +) +declText (MLText +uid 1273,0 +va (VaSet +) +xt "2000,16800,12200,17800" +st "SIGNAL en : std_ulogic" +) +) +*20 (Net +uid 1280,0 +decl (Decl +n "up_down" +t "std_ulogic" +o 5 +suid 14,0 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+dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *68 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,2000,44400,3000" +st "User:" +blo "42000,2800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3000,44000,3000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 109,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/VHD_test/hds/tb_24_1_2/_struct.bd._fpf b/VHD_test/hds/tb_24_1_2/_struct.bd._fpf new file mode 100644 index 0000000..9261639 --- /dev/null +++ b/VHD_test/hds/tb_24_1_2/_struct.bd._fpf @@ -0,0 +1,23 @@ +ARCHITECTURES list { + {tb_18_2_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_19_1_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_24_1_2 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_2.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/VHD_test/hds/tb_24_1_2/default_view b/VHD_test/hds/tb_24_1_2/default_view new file mode 100644 index 0000000..2ba0264 --- /dev/null +++ b/VHD_test/hds/tb_24_1_2/default_view @@ -0,0 +1,2 @@ +DefaultView = struct.bd +Top = false diff --git a/VHD_test/hds/tb_24_1_2/struct.bd b/VHD_test/hds/tb_24_1_2/struct.bd new file mode 100644 index 0000000..15efe98 --- /dev/null +++ b/VHD_test/hds/tb_24_1_2/struct.bd @@ -0,0 +1,2744 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_dut" +duLibraryName "VHD" +duName "ex_24_1_2" +elements [ +] +mwi 0 +uid 1519,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_2" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:01:25" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_2" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:01:25" +) +(vvPair +variable "unit" +value "tb_24_1_2" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,54000,61000,55000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,54000,56700,55000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) 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"C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_2" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:01:24" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Projects\\Biquad\\Development\\Tools\\VHDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_2" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_2\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:01:24" +) +(vvPair +variable "unit" +value "tb_24_1_2" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 51,0 +optionalChildren [ +*51 (SymbolBody +uid 8,0 +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg 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+xt "22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *67 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *68 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,2000,44400,3000" +st "User:" +blo "42000,2800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3000,44000,3000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 109,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/VHD_test/hds/tb_24_1_3/_struct.bd._fpf b/VHD_test/hds/tb_24_1_3/_struct.bd._fpf new file mode 100644 index 0000000..e579317 --- /dev/null +++ b/VHD_test/hds/tb_24_1_3/_struct.bd._fpf @@ -0,0 +1,23 @@ +ARCHITECTURES list { + {tb_18_2_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_19_1_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_24_1_3 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_3.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/VHD_test/hds/tb_24_1_3/default_view b/VHD_test/hds/tb_24_1_3/default_view new file mode 100644 index 0000000..2ba0264 --- /dev/null +++ b/VHD_test/hds/tb_24_1_3/default_view @@ -0,0 +1,2 @@ +DefaultView = struct.bd +Top = false diff --git a/VHD_test/hds/tb_24_1_3/struct.bd b/VHD_test/hds/tb_24_1_3/struct.bd new file mode 100644 index 0000000..689e4c0 --- /dev/null +++ b/VHD_test/hds/tb_24_1_3/struct.bd @@ -0,0 +1,2644 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_dut" +duLibraryName "VHD" +duName "ex_24_1_3" +elements [ +(GiElement +name "timerBitNb" +type "positive" +value "8" +) +(GiElement +name "testModeBitNb" +type "positive" +value "1" +) +] +mwi 0 +uid 1601,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_3" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:01:25" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_3" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:01:25" +) +(vvPair +variable "unit" +value "tb_24_1_3" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,54000,61000,55000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,54000,56700,55000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 115,0 +shape (Rectangle +uid 116,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,50000,65000,51000" +) +oxt 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"0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *68 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,2000,44400,3000" +st "User:" +blo "42000,2800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3000,44000,3000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 109,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/VHD_test/hds/tb_24_1_4/_struct.bd._fpf b/VHD_test/hds/tb_24_1_4/_struct.bd._fpf new file mode 100644 index 0000000..8662b1f --- /dev/null +++ b/VHD_test/hds/tb_24_1_4/_struct.bd._fpf @@ -0,0 +1,16 @@ +ARCHITECTURES list { + {tb_18_2_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_24_1_4 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_4.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/VHD_test/hds/tb_24_1_4/default_view b/VHD_test/hds/tb_24_1_4/default_view new file mode 100644 index 0000000..2ba0264 --- /dev/null +++ b/VHD_test/hds/tb_24_1_4/default_view @@ -0,0 +1,2 @@ +DefaultView = struct.bd +Top = false diff --git a/VHD_test/hds/tb_24_1_4/struct.bd b/VHD_test/hds/tb_24_1_4/struct.bd new file mode 100644 index 0000000..be6ed34 --- /dev/null +++ b/VHD_test/hds/tb_24_1_4/struct.bd @@ -0,0 +1,2862 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_dut" +duLibraryName "VHD" +duName "ex_24_1_4" +elements [ +] +mwi 0 +uid 1495,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_4" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:01:25" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_4" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable "this_ext" +value "bd" +) +(vvPair +variable "this_file" +value "struct" +) +(vvPair +variable "this_file_logical" +value "struct" +) +(vvPair +variable "time" +value "15:01:25" +) +(vvPair +variable "unit" +value "tb_24_1_4" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "struct" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 153,0 +optionalChildren [ +*1 (Grouping +uid 110,0 +optionalChildren [ +*2 (CommentText +uid 112,0 +shape (Rectangle +uid 113,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,54000,61000,55000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 114,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,54000,56700,55000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*3 (CommentText +uid 115,0 +shape (Rectangle +uid 116,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "61000,50000,65000,51000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 117,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "61200,50000,64200,51000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 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+ignorePrefs 1 +) +*9 (CommentText +uid 133,0 +shape (Rectangle +uid 134,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,53000,44000,54000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 135,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "40200,53000,42300,54000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*10 (CommentText +uid 136,0 +shape (Rectangle +uid 137,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "40000,54000,44000,55000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 138,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "40200,54000,42900,55000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*11 (CommentText +uid 139,0 +shape (Rectangle +uid 140,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "44000,53000,61000,54000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 141,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "44200,53000,54400,54000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 111,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "40000,50000,81000,55000" +) +oxt "14000,66000,55000,71000" +) +*12 (HdlText +uid 445,0 +optionalChildren [ +*13 (EmbeddedText +uid 450,0 +commentText (CommentText +uid 451,0 +ps "CenterOffsetStrategy" +shape (Rectangle +uid 452,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +) +xt "7000,22000,37000,34000" +) +oxt "0,0,18000,5000" +text (MLText +uid 453,0 +va (VaSet +) +xt "7200,22200,25400,34200" +st " +reset <= '1', '0' after 2*clockPeriod; +sClock <= not sClock after clockPeriod/2; +clock <= transport sClock after clockPeriod*9/10; + +process + constant stepDelay: time := 1 us; +begin + wait for stepDelay; + for index in 0 to 10 loop + position_int <= position_int + 1; + wait for stepDelay; + end loop; + for index in 10 downto 0 loop + position_int <= position_int - 1; + wait for stepDelay; + end loop; + wait; +end process; + +process(position_int) +begin + case to_integer(to_unsigned(position_int, 2)) is + when 0 => A <= '0'; B <= '0'; + when 1 => A <= '1'; B <= '0'; + when 2 => A <= '1'; B <= '1'; + when 3 => A <= '0'; B <= '1'; + when others => null; + end case; +end process; + + + +" +tm "HdlTextMgr" +wrapOption 3 +visibleHeight 12000 +visibleWidth 30000 +) +) +) +] +shape (Rectangle +uid 446,0 +va (VaSet +vasetType 1 +fg "65535,65535,32768" +) +xt "6000,21000,38000,35000" +) +oxt "0,0,8000,10000" +ttg (MlTextGroup +uid 447,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +textVec [ +*14 (Text +uid 448,0 +va (VaSet +) +xt "6400,35000,8000,36000" +st "eb1" +blo "6400,35800" +tm "HdlTextNameMgr" +) +*15 (Text +uid 449,0 +va (VaSet +) +xt "6400,36000,7200,37000" +st "1" +blo "6400,36800" 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"C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:01:24" +) +(vvPair +variable "unit" +value "tb_24_1_4" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2024" +) 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New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *68 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,2000,44400,3000" +st "User:" +blo "42000,2800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3000,44000,3000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 109,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/VHD_test/hds/tb_24_1_5/_struct.bd._fpf b/VHD_test/hds/tb_24_1_5/_struct.bd._fpf new file mode 100644 index 0000000..633e370 --- /dev/null +++ b/VHD_test/hds/tb_24_1_5/_struct.bd._fpf @@ -0,0 +1,23 @@ +ARCHITECTURES list { + {tb_18_2_1 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_18_2_1.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_19_1_4 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_4.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } + {tb_24_1_5 struct} list { + TASK_SETTINGS list { + PLUGIN_SETTINGS list { + ModelSimSimulator atom {TaskSetting Arguments {} TaskSetting Communication 1 TaskSetting DelaySelection typ TaskSetting GlitchGeneration 1 TaskSetting InitCmd {$SIMULATION_DIR/wave_19_1_5.do} TaskSetting LogFile {} TaskSetting RemoteHost {} TaskSetting Resolution ps TaskSetting SdfDelay typ TaskSetting SdfMultiSrcDelay latest TaskSetting SdfReduce 0 TaskSetting SdfWarnings 1 TaskSetting TimingChecks 1 TaskSetting UseBatch 0 TaskSetting UseGUI 1 TaskSetting VitalVersion 95 TaskSetting autoNames 1 TaskSetting coverage 0 TaskSetting excludePSL 0 TaskSetting exepath %task_ModelSimPath TaskSetting minimumSimSetting 0 TaskSetting saveReplayScript 0 TaskSetting useCustomSimDir 0} + } + } + } +} diff --git a/VHD_test/hds/tb_24_1_5/default_view b/VHD_test/hds/tb_24_1_5/default_view new file mode 100644 index 0000000..2ba0264 --- /dev/null +++ b/VHD_test/hds/tb_24_1_5/default_view @@ -0,0 +1,2 @@ +DefaultView = struct.bd +Top = false diff --git a/VHD_test/hds/tb_24_1_5/struct.bd b/VHD_test/hds/tb_24_1_5/struct.bd new file mode 100644 index 0000000..0a54f1e --- /dev/null +++ b/VHD_test/hds/tb_24_1_5/struct.bd @@ -0,0 +1,2763 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +(DmPackageRef +library "ieee" +unitName "std_logic_1164" +) +(DmPackageRef +library "ieee" +unitName "numeric_std" +itemName "ALL" +) +] +instances [ +(Instance +name "I_dut" +duLibraryName "VHD" +duName "ex_24_1_5" +elements [ +(GiElement +name "speedBitNb" +type "positive" +value "speedBitNb" +) +] +mwi 0 +uid 1581,0 +) +] +embeddedInstances [ +(EmbeddedInstance +name "eb1" +number "1" +) +] +libraryRefs [ +"ieee" +] +) +version "32.1" +appVersion "2019.2 (Build 5)" +noEmbeddedEditors 1 +model (BlockDiag +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "struct" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_5" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "struct.bd" +) +(vvPair +variable "f_logical" +value "struct.bd" +) +(vvPair +variable "f_noext" +value "struct" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair 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"C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\struct.bd" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_LeonardoPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "task_NC-SimPath" +value "" +) +(vvPair +variable "task_PrecisionRTLPath" +value "" +) +(vvPair +variable "task_QuestaSimPath" +value "" +) +(vvPair +variable "task_VCSPath" +value "" +) +(vvPair +variable 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23 +uid 610,0 +) +*118 (MRCItem +litem &105 +pos 2 +hidden 1 +dimension 20 +uid 611,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 612,0 +optionalChildren [ +*119 (MRCItem +litem &106 +pos 0 +dimension 20 +uid 613,0 +) +*120 (MRCItem +litem &108 +pos 1 +dimension 50 +uid 614,0 +) +*121 (MRCItem +litem &109 +pos 2 +dimension 100 +uid 615,0 +) +*122 (MRCItem +litem &110 +pos 3 +dimension 100 +uid 616,0 +) +*123 (MRCItem +litem &111 +pos 4 +dimension 50 +uid 617,0 +) +*124 (MRCItem +litem &112 +pos 5 +dimension 50 +uid 618,0 +) +*125 (MRCItem +litem &113 +pos 6 +dimension 80 +uid 619,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 607,0 +vaOverrides [ +] +) +] +) +uid 593,0 +type 1 +) +activeModelName "BlockDiag" +) diff --git a/VHD_test/hds/tb_24_1_5/symbol.sb b/VHD_test/hds/tb_24_1_5/symbol.sb new file mode 100644 index 0000000..4192c40 --- /dev/null +++ b/VHD_test/hds/tb_24_1_5/symbol.sb @@ -0,0 +1,1242 @@ +DocumentHdrVersion "1.1" +Header (DocumentHdr +version 2 +dialect 11 +dmPackageRefs [ +] +) +version "27.1" +appVersion "2019.2 (Build 5)" +model (Symbol +commonDM (CommonDM +ldm (LogicalDM +suid 2001,0 +usingSuid 1 +emptyRow *1 (LEmptyRow +) +uid 105,0 +optionalChildren [ +*2 (RefLabelRowHdr +) +*3 (TitleRowHdr +) +*4 (FilterRowHdr +) +*5 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*6 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*7 (GroupColHdr +tm "GroupColHdrMgr" +) +*8 (NameColHdr +tm "NameColHdrMgr" +) +*9 (ModeColHdr +tm "ModeColHdrMgr" +) +*10 (TypeColHdr +tm "TypeColHdrMgr" +) +*11 (BoundsColHdr +tm "BoundsColHdrMgr" +) +*12 (InitColHdr +tm "InitColHdrMgr" +) +*13 (EolColHdr +tm "EolColHdrMgr" +) +] +) +pdm (PhysicalDM +displayShortBounds 1 +editShortBounds 1 +uid 106,0 +optionalChildren [ +*14 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *15 (MRCItem +litem &1 +pos 3 +dimension 20 +) +uid 53,0 +optionalChildren [ +*16 (MRCItem +litem &2 +pos 0 +dimension 20 +uid 56,0 +) +*17 (MRCItem +litem &3 +pos 1 +dimension 23 +uid 58,0 +) +*18 (MRCItem +litem &4 +pos 2 +hidden 1 +dimension 20 +uid 60,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 54,0 +optionalChildren [ +*19 (MRCItem +litem &5 +pos 0 +dimension 20 +uid 62,0 +) +*20 (MRCItem +litem &7 +pos 1 +dimension 50 +uid 66,0 +) +*21 (MRCItem +litem &8 +pos 2 +dimension 100 +uid 68,0 +) +*22 (MRCItem +litem &9 +pos 3 +dimension 50 +uid 70,0 +) +*23 (MRCItem +litem &10 +pos 4 +dimension 100 +uid 72,0 +) +*24 (MRCItem +litem &11 +pos 5 +dimension 100 +uid 74,0 +) +*25 (MRCItem +litem &12 +pos 6 +dimension 50 +uid 76,0 +) +*26 (MRCItem +litem &13 +pos 7 +dimension 80 +uid 78,0 +) +] +) +fixedCol 4 +fixedRow 2 +name "Ports" +uid 52,0 +vaOverrides [ +] +) +] +) +uid 104,0 +) +genericsCommonDM (CommonDM +ldm (LogicalDM +emptyRow *27 (LEmptyRow +) +uid 108,0 +optionalChildren [ +*28 (RefLabelRowHdr +) +*29 (TitleRowHdr +) +*30 (FilterRowHdr +) +*31 (RefLabelColHdr +tm "RefLabelColHdrMgr" +) +*32 (RowExpandColHdr +tm "RowExpandColHdrMgr" +) +*33 (GroupColHdr +tm "GroupColHdrMgr" +) +*34 (NameColHdr +tm "GenericNameColHdrMgr" +) +*35 (TypeColHdr +tm "GenericTypeColHdrMgr" +) +*36 (InitColHdr +tm "GenericValueColHdrMgr" +) +*37 (PragmaColHdr +tm "GenericPragmaColHdrMgr" +) +*38 (EolColHdr +tm "GenericEolColHdrMgr" +) +] +) +pdm (PhysicalDM +uid 109,0 +optionalChildren [ +*39 (Sheet +sheetRow (SheetRow +headerVa (MVa +cellColor "49152,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +) +cellVa (MVa +cellColor "65535,65535,65535" +fontColor "0,0,0" +font "Tahoma,10,0" +) +groupVa (MVa +cellColor "39936,56832,65280" +fontColor "0,0,0" +font "Tahoma,10,0" +) +emptyMRCItem *40 (MRCItem +litem &27 +pos 3 +dimension 20 +) +uid 80,0 +optionalChildren [ +*41 (MRCItem +litem &28 +pos 0 +dimension 20 +uid 83,0 +) +*42 (MRCItem +litem &29 +pos 1 +dimension 23 +uid 85,0 +) +*43 (MRCItem +litem &30 +pos 2 +hidden 1 +dimension 20 +uid 87,0 +) +] +) +sheetCol (SheetCol +propVa (MVa +cellColor "0,49152,49152" +fontColor "0,0,0" +font "Tahoma,10,0" +textAngle 90 +) +uid 81,0 +optionalChildren [ +*44 (MRCItem +litem &31 +pos 0 +dimension 20 +uid 89,0 +) +*45 (MRCItem +litem &33 +pos 1 +dimension 50 +uid 93,0 +) +*46 (MRCItem +litem &34 +pos 2 +dimension 100 +uid 95,0 +) +*47 (MRCItem +litem &35 +pos 3 +dimension 100 +uid 97,0 +) +*48 (MRCItem +litem &36 +pos 4 +dimension 50 +uid 99,0 +) +*49 (MRCItem +litem &37 +pos 5 +dimension 50 +uid 101,0 +) +*50 (MRCItem +litem &38 +pos 6 +dimension 80 +uid 103,0 +) +] +) +fixedCol 3 +fixedRow 2 +name "Ports" +uid 79,0 +vaOverrides [ +] +) +] +) +uid 107,0 +type 1 +) +VExpander (VariableExpander +vvMap [ +(vvPair +variable " " +value " " +) +(vvPair +variable "HDLDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl" +) +(vvPair +variable "HDSDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "SideDataDesignDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\symbol.sb.info" +) +(vvPair +variable "SideDataUserDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\symbol.sb.user" +) +(vvPair +variable "SourceDir" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds" +) +(vvPair +variable "appl" +value "HDL Designer" +) +(vvPair +variable "arch_name" +value "symbol" +) +(vvPair +variable "concat_file" +value "" +) +(vvPair +variable "config" +value "%(unit)_config" +) +(vvPair +variable "d" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5" +) +(vvPair +variable "d_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5" +) +(vvPair +variable "date" +value "20.03.2024" +) +(vvPair +variable "day" +value "mer." +) +(vvPair +variable "day_long" +value "mercredi" +) +(vvPair +variable "dd" +value "20" +) +(vvPair +variable "designName" +value "" +) +(vvPair +variable "entity_name" +value "tb_24_1_5" +) +(vvPair +variable "ext" +value "" +) +(vvPair +variable "f" +value "symbol.sb" +) +(vvPair +variable "f_logical" +value "symbol.sb" +) +(vvPair +variable "f_noext" +value "symbol" +) +(vvPair +variable "graphical_source_author" +value "remy.borgeat" +) +(vvPair +variable "graphical_source_date" +value "20.03.2024" +) +(vvPair +variable "graphical_source_group" +value "UNKNOWN" +) +(vvPair +variable "graphical_source_host" +value "WE10993" +) +(vvPair +variable "graphical_source_time" +value "15:01:24" +) +(vvPair +variable "group" +value "UNKNOWN" +) +(vvPair +variable "host" +value "WE10993" +) +(vvPair +variable "language" +value "VHDL" +) +(vvPair +variable "library" +value "VHD_test" +) +(vvPair +variable "library_downstream_HdsLintPlugin" +value "$HDS_PROJECT_DIR/../VHD_test/designcheck" +) +(vvPair +variable "library_downstream_ModelSim" +value "D:\\Projects\\Biquad\\Development\\Tools\\VHDL\\VHDL_comp" +) +(vvPair +variable "library_downstream_ModelSimCompiler" +value "$SCRATCH_DIR/Exam/VHD_test/work" +) +(vvPair +variable "mm" +value "03" +) +(vvPair +variable "module_name" +value "tb_24_1_5" +) +(vvPair +variable "month" +value "mars" +) +(vvPair +variable "month_long" +value "mars" +) +(vvPair +variable "p" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\symbol.sb" +) +(vvPair +variable "p_logical" +value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_5\\symbol.sb" +) +(vvPair +variable "package_name" +value "" +) +(vvPair +variable "project_name" +value "hds" +) +(vvPair +variable "series" +value "HDL Designer Series" +) +(vvPair +variable "task_DesignCompilerPath" +value "" +) +(vvPair +variable "task_HDSPath" +value "$HDS_HOME" +) +(vvPair +variable "task_ISEBinPath" +value "" +) +(vvPair +variable "task_ISEPath" +value "" +) +(vvPair +variable "task_ModelSimPath" +value "$MODELSIM_HOME" +) +(vvPair +variable "this_ext" +value "sb" +) +(vvPair +variable "this_file" +value "symbol" +) +(vvPair +variable "this_file_logical" +value "symbol" +) +(vvPair +variable "time" +value "15:01:24" +) +(vvPair +variable "unit" +value "tb_24_1_5" +) +(vvPair +variable "user" +value "remy.borgeat" +) +(vvPair +variable "version" +value "2019.2 (Build 5)" +) +(vvPair +variable "view" +value "symbol" +) +(vvPair +variable "year" +value "2024" +) +(vvPair +variable "yy" +value "24" +) +] +) +LanguageMgr "Vhdl2008LangMgr" +uid 51,0 +optionalChildren [ +*51 (SymbolBody +uid 8,0 +shape (Rectangle +uid 9,0 +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +uid 10,0 +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +uid 11,0 +va (VaSet +font "Verdana,9,1" +) +xt "22600,14800,28000,16000" +st "VHD_test" +blo "22600,15800" +) +second (Text +uid 12,0 +va (VaSet +font "Verdana,9,1" +) +xt "22600,16000,28500,17200" +st "tb_24_1_5" +blo "22600,17000" +) +) +gi *52 (GenericInterface +uid 13,0 +ps "CenterOffsetStrategy" +matrix (Matrix +uid 14,0 +text (MLText +uid 15,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,11500,12800" +st "Generic Declarations" +) +header "Generic Declarations" +showHdrWhenContentsEmpty 1 +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +*53 (Grouping +uid 16,0 +optionalChildren [ +*54 (CommentText +uid 18,0 +shape (Rectangle +uid 19,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,48000,53000,49000" +) +oxt "18000,70000,35000,71000" +text (MLText +uid 20,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,48000,45600,49000" +st " +by %user on %dd %month %year +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*55 (CommentText +uid 21,0 +shape (Rectangle +uid 22,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,44000,57000,45000" +) +oxt "35000,66000,39000,67000" +text (MLText +uid 23,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,44000,56200,45000" +st " +Project: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*56 (CommentText +uid 24,0 +shape (Rectangle +uid 25,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,46000,53000,47000" +) +oxt "18000,68000,35000,69000" +text (MLText +uid 26,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,46000,46200,47000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +*57 (CommentText +uid 27,0 +shape (Rectangle +uid 28,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,46000,36000,47000" +) +oxt "14000,68000,18000,69000" +text (MLText +uid 29,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,46000,34300,47000" +st " +Title: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*58 (CommentText +uid 30,0 +shape (Rectangle +uid 31,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "53000,45000,73000,49000" +) +oxt "35000,67000,55000,71000" +text (MLText +uid 32,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "53200,45200,62600,46200" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 4000 +visibleWidth 20000 +) +ignorePrefs 1 +) +*59 (CommentText +uid 33,0 +shape (Rectangle +uid 34,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "57000,44000,73000,45000" +) +oxt "39000,66000,55000,67000" +text (MLText +uid 35,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "57200,44000,67400,45000" +st " + +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 16000 +) +position 1 +ignorePrefs 1 +) +*60 (CommentText +uid 36,0 +shape (Rectangle +uid 37,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,44000,53000,46000" +) +oxt "14000,66000,35000,68000" +text (MLText +uid 38,0 +va (VaSet +fg "32768,0,0" +) +xt "39000,44500,46000,45500" +st " + +" +ju 0 +tm "CommentText" +wrapOption 3 +visibleHeight 2000 +visibleWidth 21000 +) +position 1 +ignorePrefs 1 +) +*61 (CommentText +uid 39,0 +shape (Rectangle +uid 40,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,47000,36000,48000" +) +oxt "14000,69000,18000,70000" +text (MLText +uid 41,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,47000,34300,48000" +st " +Path: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*62 (CommentText +uid 42,0 +shape (Rectangle +uid 43,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "32000,48000,36000,49000" +) +oxt "14000,70000,18000,71000" +text (MLText +uid 44,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "32200,48000,34900,49000" +st " +Edited: +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 4000 +) +position 1 +ignorePrefs 1 +) +*63 (CommentText +uid 45,0 +shape (Rectangle +uid 46,0 +sl 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +) +xt "36000,47000,53000,48000" +) +oxt "18000,69000,35000,70000" +text (MLText +uid 47,0 +va (VaSet +fg "0,0,32768" +bg "0,0,32768" +) +xt "36200,47000,47000,48000" +st " +%library/%unit/%view +" +tm "CommentText" +wrapOption 3 +visibleHeight 1000 +visibleWidth 17000 +) +position 1 +ignorePrefs 1 +) +] +shape (GroupingShape +uid 17,0 +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineStyle 2 +lineWidth 2 +) +xt "32000,44000,73000,49000" +) +oxt "14000,66000,55000,71000" +) +] +bg "65535,65535,65535" +grid (Grid +origin "0,0" +isVisible 1 +isActive 1 +xSpacing 1000 +xySpacing 1000 +xShown 1 +yShown 1 +color "26368,26368,26368" +) +packageList *64 (PackageList +uid 48,0 +stg "VerticalLayoutStrategy" +textVec [ +*65 (Text +uid 49,0 +va (VaSet +font "arial,8,1" +) +xt "0,0,5400,1000" +st "Package List" +blo "0,800" +) +*66 (MLText +uid 50,0 +va (VaSet +) +xt "0,1000,10900,3000" +tm "PackageList" +) +] +) +windowSize "0,0,895,750" +viewArea "0,0,0,0" +cachedDiagramExtent "0,0,0,0" +pageBreakOrigin "0,0" +defaultCommentText (CommentText +shape (Rectangle +layer 0 +va (VaSet +vasetType 1 +fg "65280,65280,46080" +lineColor "0,0,32768" +) +xt "0,0,15000,5000" +) +text (MLText +va (VaSet +fg "0,0,32768" +font "Courier New,9,0" +) +xt "200,200,2700,1400" +st " +Text +" +tm "CommentText" +wrapOption 3 +visibleHeight 4600 +visibleWidth 14600 +) +) +defaultRequirementText (RequirementText +shape (ZoomableIcon +layer 0 +va (VaSet +vasetType 1 +fg "59904,39936,65280" +lineColor "0,0,32768" +) +xt "0,0,1500,1750" +iconName "reqTracerRequirement.bmp" +iconMaskName "reqTracerRequirement.msk" +) +autoResize 1 +text (MLText +va (VaSet +fg "0,0,32768" +font "arial,8,0" +) +xt "500,2150,1400,3150" +st " +Text +" +tm "RequirementText" +wrapOption 3 +visibleHeight 1350 +visibleWidth 1100 +) +) +defaultPanel (Panel +shape (RectFrame +va (VaSet +vasetType 1 +fg "65535,65535,65535" +lineColor "32768,0,0" +lineWidth 2 +) +xt "0,0,20000,20000" +) +title (TextAssociate +ps "TopLeftStrategy" +text (Text +va (VaSet +font "Verdana,9,1" +) +xt "1000,1000,4400,2200" +st "Panel0" +blo "1000,2000" +tm "PanelText" +) +) +) +parentGraphicsRef (HdmGraphicsRef +libraryName "" +entityName "" +viewName "" +) +defaultSymbolBody (SymbolBody +shape (Rectangle +va (VaSet +vasetType 1 +fg "0,65535,0" +lineColor "0,32896,0" +lineWidth 2 +) +xt "15000,6000,35000,26000" +) +biTextGroup (BiTextGroup +ps "CenterOffsetStrategy" +stg "VerticalLayoutStrategy" +first (Text +va (VaSet +font "Verdana,9,1" +) +xt "22600,14800,27400,16000" +st "" +blo "22600,15800" +) +second (Text +va (VaSet +font "Verdana,9,1" +) +xt "22600,16000,25900,17200" +st "" +blo "22600,17000" +) +) +gi *67 (GenericInterface +ps "CenterOffsetStrategy" +matrix (Matrix +text (MLText +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "0,12000,0,12000" +) +header "Generic Declarations" +) +elements [ +] +) +portInstanceVisAsIs 1 +portInstanceVis (PortSigDisplay +) +) +defaultCptPort (CptPort +ps "OnEdgeStrategy" +shape (Triangle +ro 90 +va (VaSet +vasetType 1 +fg "0,65535,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,1400,1750" +st "In0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +decl (Decl +n "In0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +defaultCptPortBuffer (CptPort +ps "OnEdgeStrategy" +shape (Diamond +va (VaSet +vasetType 1 +fg "65535,65535,65535" +bg "0,0,0" +) +xt "0,0,750,750" +) +tg (CPTG +ps "CptPortTextPlaceStrategy" +stg "VerticalLayoutStrategy" +f (Text +va (VaSet +) +xt "0,750,2800,1750" +st "Buffer0" +blo "0,1550" +tm "CptPortNameMgr" +) +) +dt (MLText +va (VaSet +font "Courier New,8,0" +) +) +thePort (LogicalPort +lang 11 +m 3 +decl (Decl +n "Buffer0" +t "std_logic_vector" +b "(15 DOWNTO 0)" +o 0 +) +) +) +DeclarativeBlock *68 (SymDeclBlock +uid 1,0 +stg "SymDeclLayoutStrategy" +declLabel (Text +uid 2,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,0,47400,1000" +st "Declarations" +blo "42000,800" +) +portLabel (Text +uid 3,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,1000,44700,2000" +st "Ports:" +blo "42000,1800" +) +externalLabel (Text +uid 4,0 +va (VaSet +font "Arial,8,1" +) +xt "42000,2000,44400,3000" +st "User:" +blo "42000,2800" +) +internalLabel (Text +uid 6,0 +va (VaSet +isHidden 1 +font "Arial,8,1" +) +xt "42000,0,47800,1000" +st "Internal User:" +blo "42000,800" +) +externalText (MLText +uid 5,0 +va (VaSet +font "Courier New,8,0" +) +xt "44000,3000,44000,3000" +tm "SyDeclarativeTextMgr" +) +internalText (MLText +uid 7,0 +va (VaSet +isHidden 1 +font "Courier New,8,0" +) +xt "42000,0,42000,0" +tm "SyDeclarativeTextMgr" +) +) +lastUid 109,0 +okToSyncOnLoad 1 +OkToSyncGenericsOnLoad 1 +) diff --git a/hdlDesigner.bat b/hdlDesigner.bat new file mode 100644 index 0000000..c6167d3 --- /dev/null +++ b/hdlDesigner.bat @@ -0,0 +1,40 @@ +@echo off +REM ---------------------------------------------------------------------------- +REM Define environment variables +REM +set HDS_PROJECT_DIR=%CD% +set HDS_LIBS=%HDS_PROJECT_DIR%\Prefs\hds.hdp +set HDS_USER_HOME=%HDS_PROJECT_DIR%\Prefs\hds_user +set HDS_TEAM_HOME=%HDS_PROJECT_DIR%\Prefs\hds_team + +set SIMULATION_DIR=%HDS_PROJECT_DIR:\=/%/Simulation +set SCRATCH_DIR=%USERPROFILE%\Work\Tmp + +set HDS_HOME=C:\eda\MentorGraphics\HDS +if "%MODELSIM_HOME%" == "" ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win32 + if not exist !MODELSIM_HOME!\ ( + set MODELSIM_HOME=C:\eda\MentorGraphics\modelsim\win64 + ) +) +::set HDS_HOME=C:\tools\eda\HDS +::set MODELSIM_HOME=C:\tools\eda\Modelsim\win64 + +REM ---------------------------------------------------------------------------- +REM Prepare scratch directory +REM +rmdir /S /Q "%SCRATCH_DIR%\%DESIGN_NAME%" +mkdir "%SCRATCH_DIR%\%DESIGN_NAME%" + +REM ---------------------------------------------------------------------------- +REM Delete intermediate files +REM +del /s %HDS_PROJECT_DIR%\*.bak %HDS_PROJECT_DIR%\*.lck %HDS_PROJECT_DIR%\.cache.dat +del /s %HDS_PROJECT_DIR%\*_entity.vhd %HDS_PROJECT_DIR%\*_struct.vhd %HDS_PROJECT_DIR%\*_fsm.vhd +REM del /s %HDS_PROJECT_DIR%\*.vhg + +REM ---------------------------------------------------------------------------- +REM Launch Application +REM +REM %windir%\system32\cmd.exe /c start %HDS_HOME%\bin\hdldesigner.exe +start %HDS_HOME%\bin\hdldesigner.exe diff --git a/hdl_designer.bash b/hdl_designer.bash new file mode 100644 index 0000000..ed8185a --- /dev/null +++ b/hdl_designer.bash @@ -0,0 +1,66 @@ +#!/bin/bash + +#================================================================================ +# hdl_designer.bash - Starts HDL designer from the "Prefs" folder +# + +SEPARATOR='--------------------------------------------------------------------------------' +INDENT=' ' + + +#-------------------------------------------------------------------------------- +# Parse command line options +# +usage='Usage: hdl_designer.bash [-v] [-h]' +usage="$usage\n\t[-d designDirectory] [-u userPrefsDirectory]" + +design_directory=`pwd` +design_directory="$design_directory/Prefs" +user_prefs_directory="$design_directory/hds_user-linux" + +while getopts "d:u:vh" options; do + case $options in + d ) design_directory=$OPTARG;; + u ) user_prefs_directory=$OPTARG;; + v ) verbose=1;; + h ) echo -e $usage + exit 1;; + * ) echo -e $usage + exit 1;; + esac +done + + +#================================================================================ +# Main script +# +if [ -n "$verbose" ] ; then + echo "$SEPARATOR" + echo "Launching HDL Designer" + echo "${INDENT}Start directory is $design_directory" + echo "${INDENT}User prefs directory is $user_prefs_directory" +fi + + +#------------------------------------------------------------------------------- +# System environment variables +# +export HDS_HOME=/usr/opt/HDS +export LC_ALL=C +export LD_LIBRARY_PATH=/usr/openwin/lib:/usr/lib:/usr/dt/lib:/usr/opt/HDS/ezwave/lib:/usr/opt/HDS/bin +export MGLS_HOME=/usr/opt/HDS/license/mgls + +#------------------------------------------------------------------------------- +# Project environment variables +# +export HDS_LIBS="$design_directory/hds.hdp" +export HDS_USER_HOME="$user_prefs_directory" +export HDS_TEAM_HOME="$user_prefs_directory/../hds_team" +export SIMULATION_DIR="$design_directory/../Simulation" +export SCRATCH_DIR='/tmp' + + +#------------------------------------------------------------------------------- +# Launch application +# +hdldesigner &