From 8b9202c0ab282f4f5539e7c0afdbcfb1527a90c1 Mon Sep 17 00:00:00 2001 From: Klagarge Date: Fri, 22 Mar 2024 14:55:12 +0100 Subject: [PATCH] exercice 5 --- VHD/hdl/ex_24_1_5_entity.vhd | 28 +++++++++ VHD/hdl/ex_24_1_5_studentVersion.vhd | 51 ++++++++++++++- VHD_test/hdl/tb_24_1_5_entity.vhd | 15 +++++ VHD_test/hdl/tb_24_1_5_struct.vhd | 94 ++++++++++++++++++++++++++++ 4 files changed, 186 insertions(+), 2 deletions(-) create mode 100644 VHD/hdl/ex_24_1_5_entity.vhd create mode 100644 VHD_test/hdl/tb_24_1_5_entity.vhd create mode 100644 VHD_test/hdl/tb_24_1_5_struct.vhd diff --git a/VHD/hdl/ex_24_1_5_entity.vhd b/VHD/hdl/ex_24_1_5_entity.vhd new file mode 100644 index 0000000..75a660f --- /dev/null +++ b/VHD/hdl/ex_24_1_5_entity.vhd @@ -0,0 +1,28 @@ +-- VHDL Entity VHD.ex_24_1_5.symbol +-- +-- Created: +-- by - francois.francois (Aphelia) +-- at - 13:07:26 03/27/19 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.all; + +ENTITY ex_24_1_5 IS + GENERIC( + speedBitNb : positive + ); + PORT( + start : IN std_ulogic; + clock : IN std_ulogic; + reset : IN std_ulogic; + done : OUT std_ulogic; + speed : OUT unsigned (speedBitNb-1 DOWNTO 0) + ); + +-- Declarations + +END ex_24_1_5 ; + diff --git a/VHD/hdl/ex_24_1_5_studentVersion.vhd b/VHD/hdl/ex_24_1_5_studentVersion.vhd index 1626ede..c802cf8 100644 --- a/VHD/hdl/ex_24_1_5_studentVersion.vhd +++ b/VHD/hdl/ex_24_1_5_studentVersion.vhd @@ -1,5 +1,52 @@ architecture studentVersion of ex_24_1_5 is + + signal running : std_ulogic; + signal deccel : std_ulogic; + signal counter : unsigned(speedBitNb/2-1 downto 0); + signal accumulator : unsigned(speedBitNb-1 downto 0); + begin - speed <= (others => '0'); - done <= '0'; + process(clock, reset) begin + if reset = '1' then + + running <= '0'; + deccel <= '0'; + counter <= (others => '0'); + accumulator <= (others => '0'); + speed <= (others => '0'); + done <= '0'; + + elsif rising_edge(clock) then + + if start = '1' then + running <= '1'; + deccel <= '0'; + counter <= (others => '0'); + accumulator <= (others => '0'); -- Comment this line if you want 2 accel without overflow (l.38-39) + end if; + + if running = '1' then + if deccel = '0' then + counter <= counter + 1; + else + counter <= counter - 1; + end if; + accumulator <= accumulator + counter; + speed <= accumulator; + end if; + + --if ((counter = 2**(speedBitNb/2-1)) and (deccel = '0')) then -- For 2 accel without overflow + if ((counter = 2**((speedBitNb/2))-2) and (deccel = '0')) then -- For best fit for only one acceleration + deccel <= '1'; + done <= '1'; + else + done <= '0'; + end if; + + if ((deccel = '1') and (counter = 0)) then + running <= '0'; + end if; + + end if; + end process; end studentVersion; diff --git a/VHD_test/hdl/tb_24_1_5_entity.vhd b/VHD_test/hdl/tb_24_1_5_entity.vhd new file mode 100644 index 0000000..1efe075 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_5_entity.vhd @@ -0,0 +1,15 @@ +-- VHDL Entity VHD_test.tb_24_1_5.symbol +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:24 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- + + +ENTITY tb_24_1_5 IS +-- Declarations + +END tb_24_1_5 ; + diff --git a/VHD_test/hdl/tb_24_1_5_struct.vhd b/VHD_test/hdl/tb_24_1_5_struct.vhd new file mode 100644 index 0000000..9561da5 --- /dev/null +++ b/VHD_test/hdl/tb_24_1_5_struct.vhd @@ -0,0 +1,94 @@ +-- +-- VHDL Architecture VHD_test.tb_24_1_5.struct +-- +-- Created: +-- by - remy.borgeat.UNKNOWN (WE10993) +-- at - 15:01:25 20.03.2024 +-- +-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5) +-- +LIBRARY ieee; + USE ieee.std_logic_1164.all; + USE ieee.numeric_std.ALL; + +LIBRARY VHD; + +ARCHITECTURE struct OF tb_24_1_5 IS + + -- Architecture declarations + constant speedBitNb : positive := 8; + + constant clockFrequency : real := 100.0E6; + constant clockPeriod : time := (1.0/clockFrequency) * 1 sec; + signal sClock : std_uLogic := '1'; + + signal position_int : integer := 0; + + -- Internal signal declarations + SIGNAL clock : std_ulogic; + SIGNAL done : std_ulogic; + SIGNAL reset : std_ulogic; + SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0); + SIGNAL start : std_ulogic; + + + -- Component Declarations + COMPONENT ex_24_1_5 + GENERIC ( + speedBitNb : positive + ); + PORT ( + start : IN std_ulogic ; + clock : IN std_ulogic ; + reset : IN std_ulogic ; + done : OUT std_ulogic ; + speed : OUT unsigned (speedBitNb-1 DOWNTO 0) + ); + END COMPONENT; + + -- Optional embedded configurations + -- pragma synthesis_off + FOR ALL : ex_24_1_5 USE ENTITY VHD.ex_24_1_5; + -- pragma synthesis_on + + +BEGIN + -- Architecture concurrent statements + -- HDL Embedded Text Block 1 eb1 + reset <= '1', '0' after 2*clockPeriod; + sClock <= not sClock after clockPeriod/2; + clock <= transport sClock after clockPeriod*9/10; + + process + constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod; + begin + start <= '0'; + + wait for testDelay; + start <= '1', '0' after clockPeriod; + + wait for testDelay; + start <= '1', '0' after clockPeriod; + + wait; + end process; + + + + + + + -- Instance port mappings. + I_dut : ex_24_1_5 + GENERIC MAP ( + speedBitNb => speedBitNb + ) + PORT MAP ( + start => start, + clock => clock, + reset => reset, + done => done, + speed => speed + ); + +END struct;