-- VHDL Entity VHD.ex_19_1_3.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 09:40:30 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY ex_19_1_3 IS
   GENERIC( 
      timerBitNb    : positive := 8;
      testModeBitNb : positive := 1
   );
   PORT( 
      testMode : IN     std_ulogic;
      clock    : IN     std_ulogic;
      reset    : IN     std_ulogic;
      pwmEn    : OUT    std_ulogic
   );

-- Declarations

END ex_19_1_3 ;