FILE_NAMING_RULE: %(module_name).v
DESCRIPTION_START
Template for the creation of Verilog Module files.
This template was migrated from header preferences created in a
previous version of HDL Designer.
DESCRIPTION_END
// 
//
// Module %(library).%(unit).%(view)
//
// Created:
//          by - %(user).%(group) (%(host))
//          at - %(time) %(date)
//
// Generated by Mentor Graphics' HDL Designer(TM) %(version)
//
// 
%(moduleBody)
// 
// ### Please start your Verilog code here ### 

endmodule