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elements [ ] ) archFileType "UNKNOWN" ) defaultVhdlComponent (VhdlComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,8000,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *57 (Text va (VaSet ) xt "950,3500,3250,4500" st "Library" blo "950,4300" ) *58 (Text va (VaSet ) xt "950,4500,7050,5500" st "VhdlComponent" blo "950,5300" ) *59 (Text va (VaSet ) xt "950,5500,1550,6500" st "I0" blo "950,6300" tm "InstanceNameMgr" ) ] ) ga (GenericAssociation ps "EdgeToEdgeStrategy" matrix (Matrix text (MLText va (VaSet isHidden 1 ) xt "-6050,1500,-6050,1500" ) header "" ) elements [ ] ) entityPath "" archName "" archPath "" ) defaultVerilogComponent (VerilogComponent shape (Rectangle va (VaSet vasetType 1 fg "0,65535,0" ) xt "-50,0,8050,10000" ) ttg (MlTextGroup ps "CenterOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *60 (Text va (VaSet ) xt "450,3500,2750,4500" st "Library" blo "450,4300" ) *61 (Text va (VaSet ) xt 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(VaSet isHidden 1 font "Arial,12,0" ) xt "0,-375,0,-375" blo "0,-375" tm "WireNameMgr" ) ) ) defaultSignal (Wire shape (OrthoPolyLine va (VaSet vasetType 3 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 stc 0 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet font "Arial,12,0" ) xt "0,0,2600,1400" st "sig0" blo "0,1200" tm "WireNameMgr" ) ) ) defaultBus (Wire shape (OrthoPolyLine va (VaSet vasetType 3 lineWidth 2 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 sty 1 stc 0 st 0 sf 1 si 0 tg (WTG ps "ConnStartEndStrategy" stg "STSignalDisplayStrategy" f (Text va (VaSet font "Arial,12,0" ) xt "0,0,3900,1400" st "dbus0" blo "0,1200" tm "WireNameMgr" ) ) ) defaultBundle (Bundle shape (OrthoPolyLine va (VaSet vasetType 3 lineStyle 3 lineWidth 1 ) pts [ "0,0" "0,0" ] ) ss 0 es 0 sat 32 eat 32 textGroup (BiTextGroup ps "ConnStartEndStrategy" stg "VerticalLayoutStrategy" first (Text va (VaSet ) xt "0,0,2600,1000" st "bundle0" blo "0,800" tm "BundleNameMgr" ) second (MLText va (VaSet ) xt "0,1000,1000,2000" st "()" tm "BundleContentsMgr" ) ) bundleNet &0 ) defaultPortMapFrame (PortMapFrame ps "PortMapFrameStrategy" shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "0,0,50000" lineWidth 2 ) xt "0,0,10000,12000" ) portMapText (BiTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" first (MLText va (VaSet ) xt "0,0,3100,1000" st "Auto list" ) second (MLText va (VaSet ) xt "0,1000,6300,2000" st "User defined list" tm "PortMapTextMgr" ) ) ) defaultGenFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "28160,28160,28160" lineStyle 2 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1100,12500,-100" st "g0: FOR i IN 0 TO n GENERATE" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1050,1450" ) num (Text va (VaSet ) xt "350,250,750,1250" st "1" blo "350,1050" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *65 (Text va (VaSet font "Arial,8,1" ) xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) *66 (MLText va (VaSet ) xt "14100,21000,14100,21000" tm "BdFrameDeclTextMgr" ) ] ) ) defaultBlockFrame (Frame shape (RectFrame va (VaSet vasetType 1 fg "65535,65535,65535" lineColor "28160,28160,28160" lineStyle 1 lineWidth 3 ) xt "0,0,20000,20000" ) title (TextAssociate ps "TopLeftStrategy" text (MLText va (VaSet ) xt "0,-1100,7300,-100" st "b0: BLOCK (guard)" tm "FrameTitleTextMgr" ) ) seqNum (FrameSequenceNumber ps "TopLeftStrategy" shape (Rectangle va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "50,50,1050,1450" ) num (Text va (VaSet ) xt "350,250,750,1250" st "1" blo "350,1050" tm "FrameSeqNumMgr" ) ) decls (MlTextGroup ps "BottomRightOffsetStrategy" stg "VerticalLayoutStrategy" textVec [ *67 (Text va (VaSet font "Arial,8,1" ) xt "14100,20000,22000,21000" st "Frame Declarations" blo "14100,20800" ) *68 (MLText va (VaSet ) xt "14100,21000,14100,21000" tm "BdFrameDeclTextMgr" ) ] ) style 3 ) defaultSaCptPort (CptPort ps "OnEdgeStrategy" shape (Triangle ro 90 va (VaSet vasetType 1 fg "0,65535,0" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,1400,1750" st "Port" blo "0,1550" ) ) thePort (LogicalPort decl (Decl n "Port" t "" o 0 ) ) ) defaultSaCptPortBuffer (CptPort ps "OnEdgeStrategy" shape (Diamond va (VaSet vasetType 1 fg "65535,65535,65535" ) xt "0,0,750,750" ) tg (CPTG ps "CptPortTextPlaceStrategy" stg "VerticalLayoutStrategy" f (Text va (VaSet ) xt "0,750,1400,1750" st "Port" blo "0,1550" ) ) thePort (LogicalPort m 3 decl (Decl n "Port" t "" o 0 ) ) ) defaultDeclText (MLText va (VaSet ) ) archDeclarativeBlock (BdArchDeclBlock uid 1,0 stg "BdArchDeclBlockLS" declLabel (Text uid 2,0 va (VaSet font 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optionalChildren [ *70 (RefLabelRowHdr ) *71 (TitleRowHdr ) *72 (FilterRowHdr ) *73 (RefLabelColHdr tm "RefLabelColHdrMgr" ) *74 (RowExpandColHdr tm "RowExpandColHdrMgr" ) *75 (GroupColHdr tm "GroupColHdrMgr" ) *76 (NameColHdr tm "BlockDiagramNameColHdrMgr" ) *77 (ModeColHdr tm "BlockDiagramModeColHdrMgr" ) *78 (TypeColHdr tm "BlockDiagramTypeColHdrMgr" ) *79 (BoundsColHdr tm "BlockDiagramBoundsColHdrMgr" ) *80 (InitColHdr tm "BlockDiagramInitColHdrMgr" ) *81 (EolColHdr tm "BlockDiagramEolColHdrMgr" ) *82 (LeafLogPort port (LogicalPort m 4 decl (Decl n "A" t "std_ulogic" o 1 suid 9,0 ) ) uid 1140,0 ) *83 (LeafLogPort port (LogicalPort m 4 decl (Decl n "B" t "std_ulogic" o 2 suid 10,0 ) ) uid 1142,0 ) *84 (LeafLogPort port (LogicalPort m 4 decl (Decl n "clock" t "std_ulogic" o 3 suid 11,0 ) ) uid 1144,0 ) *85 (LeafLogPort port (LogicalPort m 4 decl (Decl n "reset" t "std_ulogic" o 6 suid 12,0 ) ) uid 1146,0 ) *86 (LeafLogPort port (LogicalPort m 4 decl (Decl n "dir" t "std_ulogic" o 4 suid 13,0 ) ) uid 1296,0 ) *87 (LeafLogPort port (LogicalPort m 4 decl (Decl n "en" t "std_ulogic" o 5 suid 14,0 ) ) uid 1298,0 ) ] ) pdm (PhysicalDM displayShortBounds 1 editShortBounds 1 uid 578,0 optionalChildren [ *88 (Sheet sheetRow (SheetRow headerVa (MVa cellColor "49152,49152,49152" fontColor "0,0,0" font "Tahoma,10,0" ) cellVa (MVa cellColor "65535,65535,65535" fontColor "0,0,0" font "Tahoma,10,0" ) groupVa (MVa cellColor "39936,56832,65280" fontColor "0,0,0" font "Tahoma,10,0" ) emptyMRCItem *89 (MRCItem litem &69 pos 6 dimension 20 ) uid 580,0 optionalChildren [ *90 (MRCItem litem &70 pos 0 dimension 20 uid 581,0 ) *91 (MRCItem litem &71 pos 1 dimension 23 uid 582,0 ) *92 (MRCItem litem &72 pos 2 hidden 1 dimension 20 uid 583,0 ) *93 (MRCItem litem &82 pos 0 dimension 20 uid 1141,0 ) *94 (MRCItem litem &83 pos 1 dimension 20 uid 1143,0 ) *95 (MRCItem litem &84 pos 2 dimension 20 uid 1145,0 ) *96 (MRCItem litem &85 pos 3 dimension 20 uid 1147,0 ) *97 (MRCItem litem &86 pos 4 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612,0 optionalChildren [ *124 (MRCItem litem &111 pos 0 dimension 20 uid 613,0 ) *125 (MRCItem litem &113 pos 1 dimension 50 uid 614,0 ) *126 (MRCItem litem &114 pos 2 dimension 100 uid 615,0 ) *127 (MRCItem litem &115 pos 3 dimension 100 uid 616,0 ) *128 (MRCItem litem &116 pos 4 dimension 50 uid 617,0 ) *129 (MRCItem litem &117 pos 5 dimension 50 uid 618,0 ) *130 (MRCItem litem &118 pos 6 dimension 80 uid 619,0 ) ] ) fixedCol 3 fixedRow 2 name "Ports" uid 607,0 vaOverrides [ ] ) ] ) uid 593,0 type 1 ) activeModelName "BlockDiag" )