--
-- VHDL Architecture VHD_test.tb_19_1_4.struct
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 12:59:54 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY VHD;

ARCHITECTURE struct OF tb_19_1_4 IS

   -- Architecture declarations
   constant positionBitNb : positive := 8;
   
   constant clockFrequency : real := 100.0E6;
   constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
   signal sClock :  std_uLogic := '1';
   
   signal position_int : integer := 0;

   -- Internal signal declarations
   SIGNAL A     : std_ulogic;
   SIGNAL B     : std_ulogic;
   SIGNAL clock : std_ulogic;
   SIGNAL dir   : std_ulogic;
   SIGNAL en    : std_ulogic;
   SIGNAL reset : std_ulogic;


   -- Component Declarations
   COMPONENT ex_19_1_4
   PORT (
      A     : IN     std_ulogic ;
      B     : IN     std_ulogic ;
      clock : IN     std_ulogic ;
      reset : IN     std_ulogic ;
      en    : OUT    std_ulogic ;
      dir   : OUT    std_ulogic 
   );
   END COMPONENT;

   -- Optional embedded configurations
   -- pragma synthesis_off
   FOR ALL : ex_19_1_4 USE ENTITY VHD.ex_19_1_4;
   -- pragma synthesis_on


BEGIN
   -- Architecture concurrent statements
   -- HDL Embedded Text Block 1 eb1
   reset <= '1', '0' after 2*clockPeriod;
   sClock <= not sClock after clockPeriod/2;
   clock <= transport sClock after clockPeriod*9/10;
   
   process
     constant stepDelay: time := 1 us;
   begin
     wait for stepDelay;
     for index in 0 to 10 loop
       position_int <= position_int + 1;
       wait for stepDelay;
     end loop;
     for index in 10 downto 0 loop
       position_int <= position_int - 1;
       wait for stepDelay;
     end loop;
     wait;
   end process;
   
   process(position_int)
   begin
     case to_integer(to_unsigned(position_int, 2)) is
       when 0 => A <= '0'; B <= '0';
       when 1 => A <= '1'; B <= '0';
       when 2 => A <= '1'; B <= '1';
       when 3 => A <= '0'; B <= '1';
       when others => null;
     end case;
   end process;
   
   


   -- Instance port mappings.
   I_dut : ex_19_1_4
      PORT MAP (
         A     => A,
         B     => B,
         clock => clock,
         reset => reset,
         en    => en,
         dir   => dir
      );

END struct;