-- VHDL Entity VHD.ex_19_1_4.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 12:57:27 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY ex_19_1_4 IS
   PORT( 
      A     : IN     std_ulogic;
      B     : IN     std_ulogic;
      clock : IN     std_ulogic;
      reset : IN     std_ulogic;
      en    : OUT    std_ulogic;
      dir   : OUT    std_ulogic
   );

-- Declarations

END ex_19_1_4 ;