-- VHDL Entity VHD.ex_19_1_5.symbol
--
-- Created:
--          by - francois.francois (Aphelia)
--          at - 13:07:26 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.all;

ENTITY ex_19_1_5 IS
   GENERIC( 
      speedBitNb : positive
   );
   PORT( 
      start : IN     std_ulogic;
      clock : IN     std_ulogic;
      reset : IN     std_ulogic;
      done  : OUT    std_ulogic;
      speed : OUT    unsigned (speedBitNb-1 DOWNTO 0)
   );

-- Declarations

END ex_19_1_5 ;