DocumentHdrVersion "1.1"
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version 2
dialect 11
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unitName "std_logic_1164"
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library "ieee"
unitName "numeric_std"
itemName "ALL"
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duName "ex_24_1_3"
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name "timerBitNb"
type "positive"
value "13"
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value "1"
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mwi 0
uid 1601,0
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embeddedInstances [
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number "1"
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libraryRefs [
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
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variable " "
value " "
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)
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variable "HDSDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
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value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.info"
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value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.user"
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value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
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variable "appl"
value "HDL Designer"
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variable "arch_name"
value "struct"
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variable "concat_file"
value "<TBD>"
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variable "config"
value "%(unit)_config"
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variable "d"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
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variable "d_logical"
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variable "date"
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variable "day"
value "ven."
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variable "entity_name"
value "tb_24_1_3"
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variable "f_logical"
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variable "f_noext"
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variable "graphical_source_time"
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variable "host"
value "WE2330808"
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variable "language"
value "VHDL"
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variable "library"
value "VHD_test"
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value "$HDS_PROJECT_DIR/../VHD_test/designcheck"
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variable "library_downstream_ModelSim"
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp"
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variable "month_long"
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variable "p"
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variable "p_logical"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "hds"
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variable "series"
value "HDL Designer Series"
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variable "task_DesignCompilerPath"
value "<TBD>"
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variable "task_HDSPath"
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variable "task_ISEBinPath"
value "<TBD>"
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variable "task_ISEPath"
value "<TBD>"
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(vvPair
variable "task_LeonardoPath"
value "<TBD>"
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variable "task_ModelSimPath"
value "$MODELSIM_HOME"
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variable "task_NC-SimPath"
value "<TBD>"
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variable "task_PrecisionRTLPath"
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variable "task_QuestaSimPath"
value "<TBD>"
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variable "task_VCSPath"
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variable "this_ext"
value "bd"
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variable "this_file"
value "struct"
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variable "this_file_logical"
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variable "time"
value "13:45:06"
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variable "unit"
value "tb_24_1_3"
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variable "user"
value "remi.heredero"
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variable "version"
value "2019.2 (Build 5)"
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value "struct"
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variable "year"
value "2024"
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variable "yy"
value "24"
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xt "40200,54000,42900,55000"
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xt "44000,53000,61000,54000"
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xt "44200,53000,54400,54000"
st "
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commentText (CommentText
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shape (Rectangle
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fg "65535,65535,65535"
lineStyle 2
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xt "7000,24000,37000,34000"
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oxt "0,0,18000,5000"
text (MLText
uid 453,0
va (VaSet
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xt "7200,24200,25400,29200"
st "
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testMode <= '1', '0' after 100*clockPeriod;
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tm "HdlTextMgr"
wrapOption 3
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visibleWidth 30000
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)
)
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shape (Rectangle
uid 446,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
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xt "6000,23000,38000,35000"
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oxt "0,0,8000,10000"
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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uid 448,0
va (VaSet
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xt "6400,35000,8000,36000"
st "eb1"
blo "6400,35800"
tm "HdlTextNameMgr"
)
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va (VaSet
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xt "6400,36000,7200,37000"
st "1"
blo "6400,36800"
tm "HdlTextNumberMgr"
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uid 1122,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 11,0
)
declText (MLText
uid 1123,0
va (VaSet
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xt "2000,15800,12600,16800"
st "SIGNAL clock    : std_ulogic"
)
)
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uid 1130,0
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 12,0
)
declText (MLText
uid 1131,0
va (VaSet
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xt "2000,17800,12500,18800"
st "SIGNAL reset    : std_ulogic"
)
)
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decl (Decl
n "pwmEn"
t "std_ulogic"
o 2
suid 15,0
)
declText (MLText
uid 1504,0
va (VaSet
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xt "2000,16800,13400,17800"
st "SIGNAL pwmEn    : std_ulogic"
)
)
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decl (Decl
n "testMode"
t "std_ulogic"
o 4
suid 16,0
)
declText (MLText
uid 1512,0
va (VaSet
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xt "2000,18800,13300,19800"
st "SIGNAL testMode : std_ulogic"
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ro 90
va (VaSet
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)
tg (CPTG
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stg "VerticalLayoutStrategy"
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va (VaSet
font "Arial,9,0"
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xt "47000,26550,51300,27750"
st "testMode"
blo "47000,27450"
)
)
thePort (LogicalPort
decl (Decl
n "testMode"
t "std_ulogic"
o 1
suid 2004,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
uid 1590,0
ro 90
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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va (VaSet
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xt "47000,30550,49700,31750"
st "clock"
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)
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thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2005,0
)
)
)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
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fg "0,65535,0"
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tg (CPTG
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st "reset"
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)
)
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decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 2006,0
)
)
)
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uid 1597,0
ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,26625,62750,27375"
)
tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "57500,26550,61000,27750"
st "pwmEn"
ju 2
blo "61000,27450"
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)
thePort (LogicalPort
m 1
decl (Decl
n "pwmEn"
t "std_ulogic"
o 4
suid 2007,0
)
)
)
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shape (Rectangle
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bg "0,65535,0"
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va (VaSet
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tm "CptNameMgr"
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text (MLText
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xt "46000,38400,58500,40400"
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header ""
)
elements [
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type "positive"
value "1"
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]
)
ordering 1
portVis (PortSigDisplay
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va (VaSet
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xt "38000,31000,45250,31000"
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]
)
start &22
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
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va (VaSet
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on &16
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va (VaSet
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)
xt "38000,33000,45250,33000"
pts [
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]
)
start &23
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1137,0
va (VaSet
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tm "WireNameMgr"
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)
on &17
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va (VaSet
vasetType 3
)
xt "62750,27000,70000,27000"
pts [
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]
)
start &24
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1509,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1510,0
va (VaSet
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xt "64750,25700,69650,27200"
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tm "WireNameMgr"
)
)
on &18
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va (VaSet
vasetType 3
)
xt "38000,27000,45250,27000"
pts [
"45250,27000"
"38000,27000"
]
)
start &21
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1517,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1518,0
va (VaSet
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)
xt "38250,25700,43950,27200"
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blo "38250,26900"
tm "WireNameMgr"
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)
on &19
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grid (Grid
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yShown 1
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