1
0
This repository has been archived on 2024-10-30. You can view files and clone it, but cannot push or open issues or pull requests.
SEm-ExamMidterm2024/Prefs/hds_user-linux/v2015.2/templates/verilog_Interface/interface.sv
2024-03-22 13:16:48 +01:00

19 lines
455 B
Systemverilog

FILE_NAMING_RULE: %(interface_name).sv
DESCRIPTION_START
This is the default template used for the creation of Interface files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Verilog interface %(library).%(unit)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//
%(interfaceBody)
// ### Please start your Verilog code here ###
endinterface