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SEm-ExamMidterm2024/Prefs/hds_user-linux/v2016.1/templates/verilog_include/verilog_include.v
2024-03-22 13:16:48 +01:00

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FILE_NAMING_RULE: include_filename.v
DESCRIPTION_START
This is the default template used for the creation of Verilog Include files.
Template supplied by Mentor Graphics.
DESCRIPTION_END
//
// Include file %(library)
//
// Created:
// by - %(user).%(group) (%(host))
// at - %(time) %(date)
//
// using Mentor Graphics HDL Designer(TM) %(version)
//