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SEm-ExamMidterm2024/VHD/hdl/ex_24_1_2_entity.vhd
2024-03-22 13:16:48 +01:00

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VHDL

-- VHDL Entity VHD.ex_24_1_2.symbol
--
-- Created:
-- by - francois.francois (Aphelia)
-- at - 09:18:55 03/27/19
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
ENTITY ex_24_1_2 IS
PORT(
motorOn : IN std_ulogic;
side1 : OUT std_ulogic;
right_left : IN std_ulogic;
pwm : IN std_ulogic;
side2 : OUT std_ulogic
);
-- Declarations
END ex_24_1_2 ;