29 lines
553 B
VHDL
29 lines
553 B
VHDL
architecture studentVersion of ex_24_1_3 is
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signal counter : unsigned(timerBitNb-1 downto 0);
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begin
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process(reset, clock) begin
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if reset = '1' then
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counter <= (others => '0');
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elsif rising_edge(clock) then
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if testMode = '0' then
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counter <= counter - 1;
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else
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counter <= counter - 2**(timerBitNb - testModeBitNb);
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end if;
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end if;
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end process;
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process(counter)
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begin
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if counter = 0 then
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pwmEn <= '1';
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else
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pwmEn <= '0';
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end if;
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end process;
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end studentVersion;
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