53 lines
1014 B
VHDL
53 lines
1014 B
VHDL
architecture studentVersion of ex_24_1_4 is
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signal oldA: std_ulogic;
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signal oldB: std_ulogic;
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begin
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process(reset, clock) begin
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if reset = '1' then
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en <= '0';
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dir <= '0';
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oldA <= '0';
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oldA <= '0';
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elsif rising_edge(clock) then
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oldA <= a;
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oldB <= b;
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if (a='1' and oldA='0') then
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en <= '1';
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if b = '0' then
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dir <= '1';
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else
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dir <= '0';
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end if;
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elsif (b='1' and oldB='0') then
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en <= '1';
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if a = '0' then
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dir <= '0';
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else
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dir <= '1';
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end if;
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elsif (a='0' and oldA='1') then
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en <= '1';
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if b = '1' then
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dir <= '1';
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else
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dir <= '0';
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end if;
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elsif (b='0' and oldB='1') then
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en <= '1';
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if a = '1' then
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dir <= '0';
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else
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dir <= '1';
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end if;
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else
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en <= '0';
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end if;
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end if;
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end process;
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end studentVersion;
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