97 lines
2.3 KiB
VHDL
97 lines
2.3 KiB
VHDL
--
|
|
-- VHDL Architecture VHD_test.tb_24_1_1.struct
|
|
--
|
|
-- Created:
|
|
-- by - remy.borgeat.UNKNOWN (WE10993)
|
|
-- at - 15:02:54 20.03.2024
|
|
--
|
|
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
|
|
--
|
|
LIBRARY ieee;
|
|
USE ieee.std_logic_1164.all;
|
|
USE ieee.numeric_std.ALL;
|
|
|
|
LIBRARY VHD;
|
|
|
|
ARCHITECTURE struct OF tb_24_1_1 IS
|
|
|
|
-- Architecture declarations
|
|
constant positionBitNb : positive := 8;
|
|
|
|
constant clockFrequency : real := 100.0E6;
|
|
constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
|
|
signal sClock : std_uLogic := '1';
|
|
|
|
signal position_int : integer := 0;
|
|
|
|
-- Internal signal declarations
|
|
SIGNAL clock : std_ulogic;
|
|
SIGNAL en : std_ulogic;
|
|
SIGNAL position : unsigned(positionBitNb-1 DOWNTO 0);
|
|
SIGNAL reset : std_ulogic;
|
|
SIGNAL up_down : std_ulogic;
|
|
|
|
|
|
-- Component Declarations
|
|
COMPONENT ex_24_1_1
|
|
GENERIC (
|
|
counterBitNb : positive := 8
|
|
);
|
|
PORT (
|
|
en : IN std_ulogic ;
|
|
position : OUT unsigned (counterBitNb-1 DOWNTO 0);
|
|
up_down : IN std_ulogic ;
|
|
clock : IN std_ulogic ;
|
|
reset : IN std_ulogic
|
|
);
|
|
END COMPONENT;
|
|
|
|
-- Optional embedded configurations
|
|
-- pragma synthesis_off
|
|
FOR ALL : ex_24_1_1 USE ENTITY VHD.ex_24_1_1;
|
|
-- pragma synthesis_on
|
|
|
|
|
|
BEGIN
|
|
-- Architecture concurrent statements
|
|
-- HDL Embedded Text Block 1 eb1
|
|
reset <= '1', '0' after 2*clockPeriod;
|
|
sClock <= not sClock after clockPeriod/2;
|
|
clock <= transport sClock after clockPeriod*9/10;
|
|
|
|
process
|
|
constant stepDelay: time := 1 us;
|
|
begin
|
|
en <= '0';
|
|
up_down <= '1';
|
|
wait for stepDelay;
|
|
for index in 0 to 10 loop
|
|
en <= '1', '0' after clockPeriod;
|
|
position_int <= position_int + 1;
|
|
wait for stepDelay;
|
|
end loop;
|
|
up_down <= '0';
|
|
for index in 10 downto 0 loop
|
|
en <= '1', '0' after clockPeriod;
|
|
position_int <= position_int - 1;
|
|
wait for stepDelay;
|
|
end loop;
|
|
wait;
|
|
end process;
|
|
|
|
|
|
-- Instance port mappings.
|
|
I_dut : ex_24_1_1
|
|
GENERIC MAP (
|
|
counterBitNb => positionBitNb
|
|
)
|
|
PORT MAP (
|
|
en => en,
|
|
position => position,
|
|
up_down => up_down,
|
|
clock => clock,
|
|
reset => reset
|
|
);
|
|
|
|
END struct;
|