95 lines
2.0 KiB
Plaintext
95 lines
2.0 KiB
Plaintext
--
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-- VHDL Architecture VHD_test.tb_19_1_5.struct
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--
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-- Created:
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-- by - francois.francois (Aphelia)
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-- at - 13:50:24 03/27/19
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2018.1 (Build 12)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.ALL;
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LIBRARY VHD;
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ARCHITECTURE struct OF tb_19_1_5 IS
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-- Architecture declarations
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constant speedBitNb : positive := 8;
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constant clockFrequency : real := 100.0E6;
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constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
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signal sClock : std_uLogic := '1';
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signal position_int : integer := 0;
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-- Internal signal declarations
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SIGNAL clock : std_ulogic;
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SIGNAL done : std_ulogic;
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SIGNAL reset : std_ulogic;
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SIGNAL speed : unsigned(speedBitNb-1 DOWNTO 0);
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SIGNAL start : std_ulogic;
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-- Component Declarations
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COMPONENT ex_19_1_5
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GENERIC (
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speedBitNb : positive
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);
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PORT (
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start : IN std_ulogic ;
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clock : IN std_ulogic ;
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reset : IN std_ulogic ;
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done : OUT std_ulogic ;
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speed : OUT unsigned (speedBitNb-1 DOWNTO 0)
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);
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END COMPONENT;
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-- Optional embedded configurations
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-- pragma synthesis_off
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FOR ALL : ex_19_1_5 USE ENTITY VHD.ex_19_1_5;
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-- pragma synthesis_on
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BEGIN
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-- Architecture concurrent statements
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-- HDL Embedded Text Block 1 eb1
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reset <= '1', '0' after 2*clockPeriod;
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sClock <= not sClock after clockPeriod/2;
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clock <= transport sClock after clockPeriod*9/10;
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process
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constant testDelay: time := 2**(speedBitNb/2+3) * clockPeriod;
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begin
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start <= '0';
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wait for testDelay;
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start <= '1', '0' after clockPeriod;
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wait for testDelay;
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start <= '1', '0' after clockPeriod;
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wait;
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end process;
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-- Instance port mappings.
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I_dut : ex_19_1_5
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GENERIC MAP (
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speedBitNb => speedBitNb
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)
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PORT MAP (
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start => start,
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clock => clock,
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reset => reset,
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done => done,
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speed => speed
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);
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END struct;
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