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SEm-ExamMidterm2024/VHD_test/hds/tb_24_1_1/struct.bd
2024-03-22 13:16:48 +01:00

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DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
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library "ieee"
unitName "std_logic_1164"
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(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
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instances [
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name "I_dut"
duLibraryName "VHD"
duName "ex_24_1_1"
elements [
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name "counterBitNb"
type "positive"
value "positionBitNb"
)
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mwi 0
uid 1659,0
)
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embeddedInstances [
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name "eb1"
number "1"
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libraryRefs [
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
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value " "
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd.info"
)
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variable "SideDataUserDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1\\struct.bd.user"
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variable "SourceDir"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
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(vvPair
variable "appl"
value "HDL Designer"
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(vvPair
variable "arch_name"
value "struct"
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variable "concat_file"
value "<TBD>"
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(vvPair
variable "config"
value "%(unit)_config"
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variable "d"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_1"
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value "20.03.2024"
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variable "day"
value "mer."
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(vvPair
variable "day_long"
value "mercredi"
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(vvPair
variable "dd"
value "20"
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(vvPair
variable "designName"
value "<TBD>"
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variable "entity_name"
value "tb_24_1_1"
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(vvPair
variable "ext"
value "<TBD>"
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variable "f"
value "struct.bd"
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variable "f_logical"
value "struct.bd"
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variable "f_noext"
value "struct"
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variable "graphical_source_author"
value "remy.borgeat"
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(vvPair
variable "graphical_source_date"
value "20.03.2024"
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variable "graphical_source_group"
value "UNKNOWN"
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variable "graphical_source_host"
value "WE10993"
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variable "graphical_source_time"
value "15:02:54"
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(vvPair
variable "group"
value "UNKNOWN"
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variable "host"
value "WE10993"
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variable "language"
value "VHDL"
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variable "library"
value "VHD_test"
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variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/../VHD_test/designcheck"
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variable "library_downstream_ModelSim"
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp"
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(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Exam/VHD_test/work"
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variable "mm"
value "03"
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variable "module_name"
value "tb_24_1_1"
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variable "month"
value "mars"
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variable "month_long"
value "mars"
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variable "p"
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)
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variable "package_name"
value "<Undefined Variable>"
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variable "project_name"
value "hds"
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(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
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(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
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variable "task_ISEBinPath"
value "<TBD>"
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variable "task_ISEPath"
value "<TBD>"
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variable "task_LeonardoPath"
value "<TBD>"
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value "$MODELSIM_HOME"
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variable "task_NC-SimPath"
value "<TBD>"
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variable "task_PrecisionRTLPath"
value "<TBD>"
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variable "task_QuestaSimPath"
value "<TBD>"
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variable "task_VCSPath"
value "<TBD>"
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variable "this_ext"
value "bd"
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variable "this_file"
value "struct"
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variable "this_file_logical"
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variable "time"
value "15:02:54"
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(vvPair
variable "unit"
value "tb_24_1_1"
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(vvPair
variable "user"
value "remy.borgeat"
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(vvPair
variable "version"
value "2019.2 (Build 5)"
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(vvPair
variable "view"
value "struct"
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(vvPair
variable "year"
value "2024"
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(vvPair
variable "yy"
value "24"
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reset <= '1', '0' after 2*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
process
constant stepDelay: time := 1 us;
begin
en <= '0';
up_down <= '1';
wait for stepDelay;
for index in 0 to 10 loop
en <= '1', '0' after clockPeriod;
position_int <= position_int + 1;
wait for stepDelay;
end loop;
up_down <= '0';
for index in 10 downto 0 loop
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position_int <= position_int - 1;
wait for stepDelay;
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end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1137,0
va (VaSet
font "Arial,12,0"
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xt "40250,31700,43750,33200"
st "reset"
blo "40250,32900"
tm "WireNameMgr"
)
)
on &18
)
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uid 1274,0
shape (OrthoPolyLine
uid 1275,0
va (VaSet
vasetType 3
)
xt "38000,25000,45250,25000"
pts [
"45250,25000"
"38000,25000"
]
)
start &22
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1278,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1279,0
va (VaSet
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xt "40000,23700,42100,25200"
st "en"
blo "40000,24900"
tm "WireNameMgr"
)
)
on &19
)
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uid 1282,0
shape (OrthoPolyLine
uid 1283,0
va (VaSet
vasetType 3
)
xt "38000,27000,45250,27000"
pts [
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start &24
end &12
sat 32
eat 2
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st 0
sf 1
si 0
tg (WTG
uid 1286,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1287,0
va (VaSet
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)
xt "40000,25700,45800,27200"
st "up_down"
blo "40000,26900"
tm "WireNameMgr"
)
)
on &20
)
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isActive 1
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xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
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stg "VerticalLayoutStrategy"
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va (VaSet
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tm "PackageList"
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stg "VerticalLayoutStrategy"
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uid 146,0
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blo "20000,1800"
)
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uid 148,0
va (VaSet
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st "`resetall
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uid 149,0
va (VaSet
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uid 150,0
va (VaSet
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tm "BdCompilerDirectivesTextMgr"
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va (VaSet
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uid 152,0
va (VaSet
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tm "BdCompilerDirectivesTextMgr"
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xt "0,0,15000,5000"
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text (MLText
va (VaSet
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xt "200,200,2100,1200"
st "
Text
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tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
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xt "0,0,1500,1750"
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iconMaskName "reqTracerRequirement.msk"
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text (MLText
va (VaSet
fg "0,0,32768"
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xt "500,2150,1400,3150"
st "
Text
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tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
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shape (RectFrame
va (VaSet
vasetType 1
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lineColor "32768,0,0"
lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
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xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
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shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
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xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*46 (Text
va (VaSet
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xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
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va (VaSet
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st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
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]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
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xt "1700,13200,1700,13200"
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header ""
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elements [
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)
defaultMWComponent (MWC
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ttg (MlTextGroup
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blo "1000,5300"
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blo "1000,6300"
tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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xt "-6000,1500,-6000,1500"
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header ""
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elements [
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prms (Property
pclass "params"
pname "params"
ptn "String"
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visOptions (mwParamsVisibilityOptions
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xt "0,0,8000,10000"
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "1250,3500,3550,4500"
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tm "BdLibraryNameMgr"
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va (VaSet
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xt "1250,4500,6750,5500"
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tm "CptNameMgr"
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va (VaSet
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tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
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header ""
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elements [
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ttg (MlTextGroup
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va (VaSet
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blo "950,5300"
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st "I0"
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tm "InstanceNameMgr"
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ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
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header ""
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elements [
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archPath ""
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ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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tm "InstanceNameMgr"
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ga (GenericAssociation
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matrix (Matrix
text (MLText
va (VaSet
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xt "-6550,1500,-6550,1500"
)
header ""
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elements [
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)
entityPath ""
)
defaultHdlText (HdlText
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va (VaSet
vasetType 1
fg "65535,65535,32768"
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xt "0,0,8000,10000"
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ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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xt "3400,4000,4600,5000"
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blo "3400,4800"
tm "HdlTextNameMgr"
)
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va (VaSet
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xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
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)
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commentText (CommentText
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shape (Rectangle
va (VaSet
vasetType 1
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lineStyle 2
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xt "0,0,18000,5000"
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text (MLText
va (VaSet
)
xt "200,200,2100,1200"
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Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
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va (VaSet
vasetType 1
fg "65535,65535,0"
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xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
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blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
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"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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ro 270
xt "-2000,-375,-500,375"
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(Line
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ro 270
xt "-500,0,0,0"
pts [
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tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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font "Arial,12,0"
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xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
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sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
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)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
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font "Arial,12,0"
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xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
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"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
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sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
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]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Arial,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
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]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Arial,12,0"
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xt "0,0,3900,1400"
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blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
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]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
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va (VaSet
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tm "BundleContentsMgr"
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)
bundleNet &0
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ps "PortMapFrameStrategy"
shape (RectFrame
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lineColor "0,0,50000"
lineWidth 2
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xt "0,0,10000,12000"
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portMapText (BiTextGroup
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stg "VerticalLayoutStrategy"
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)
xt "0,0,3100,1000"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,6300,2000"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
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vasetType 1
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lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12500,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
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)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
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va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
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num (Text
va (VaSet
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
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decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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*63 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
)
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va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
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xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7300,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
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ps "TopLeftStrategy"
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fg "65535,65535,65535"
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xt "50,50,1050,1450"
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num (Text
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xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
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)
decls (MlTextGroup
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stg "VerticalLayoutStrategy"
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*65 (MLText
va (VaSet
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xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
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va (VaSet
vasetType 1
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xt "0,0,750,750"
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tg (CPTG
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stg "VerticalLayoutStrategy"
f (Text
va (VaSet
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xt "0,750,1400,1750"
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blo "0,1550"
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)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
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tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
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xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
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archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
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uid 2,0
va (VaSet
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xt "0,4800,5400,5800"
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blo "0,5600"
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portLabel (Text
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va (VaSet
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va (VaSet
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uid 5,0
va (VaSet
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tm "BdDeclarativeTextMgr"
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uid 8,0
va (VaSet
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xt "0,4800,0,4800"
tm "BdDeclarativeTextMgr"
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commonDM (CommonDM
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emptyRow *66 (LEmptyRow
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uid 565,0
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*68 (TitleRowHdr
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*69 (FilterRowHdr
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*70 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*71 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*72 (GroupColHdr
tm "GroupColHdrMgr"
)
*73 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*74 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*75 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*76 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*77 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*78 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*79 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "position"
t "unsigned"
b "(positionBitNb-1 downto 0)"
o 3
suid 8,0
)
)
uid 1138,0
)
*80 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 11,0
)
)
uid 1144,0
)
*81 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 4
suid 12,0
)
)
uid 1146,0
)
*82 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "en"
t "std_ulogic"
o 2
suid 13,0
)
)
uid 1288,0
)
*83 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "up_down"
t "std_ulogic"
o 5
suid 14,0
)
)
uid 1290,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 578,0
optionalChildren [
*84 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
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)
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optionalChildren [
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uid 1291,0
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sheetCol (SheetCol
propVa (MVa
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optionalChildren [
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uid 590,0
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litem &77
pos 6
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pos 7
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uid 592,0
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)
fixedCol 4
fixedRow 2
name "Ports"
uid 579,0
vaOverrides [
]
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]
)
uid 564,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *102 (LEmptyRow
)
uid 594,0
optionalChildren [
*103 (RefLabelRowHdr
)
*104 (TitleRowHdr
)
*105 (FilterRowHdr
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*106 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*107 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*108 (GroupColHdr
tm "GroupColHdrMgr"
)
*109 (NameColHdr
tm "GenericNameColHdrMgr"
)
*110 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*111 (InitColHdr
tm "GenericValueColHdrMgr"
)
*112 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*113 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
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optionalChildren [
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
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groupVa (MVa
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fontColor "0,0,0"
font "Tahoma,10,0"
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sheetCol (SheetCol
propVa (MVa
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uid 612,0
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uid 619,0
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fixedCol 3
fixedRow 2
name "Ports"
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vaOverrides [
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uid 593,0
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activeModelName "BlockDiag"
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