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SEm-ExamMidterm2024/VHD_test/hds/tb_24_1_3/struct.bd
2024-03-22 13:48:57 +01:00

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DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
(DmPackageRef
library "ieee"
unitName "std_logic_1164"
)
(DmPackageRef
library "ieee"
unitName "numeric_std"
itemName "ALL"
)
]
instances [
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name "I_dut"
duLibraryName "VHD"
duName "ex_24_1_3"
elements [
(GiElement
name "timerBitNb"
type "positive"
value "14"
)
(GiElement
name "testModeBitNb"
type "positive"
value "1"
)
]
mwi 0
uid 1601,0
)
]
embeddedInstances [
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name "eb1"
number "1"
)
]
libraryRefs [
"ieee"
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version "32.1"
appVersion "2019.2 (Build 5)"
noEmbeddedEditors 1
model (BlockDiag
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vvMap [
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variable " "
value " "
)
(vvPair
variable "HDLDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hdl"
)
(vvPair
variable "HDSDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
)
(vvPair
variable "SideDataDesignDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.info"
)
(vvPair
variable "SideDataUserDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd.user"
)
(vvPair
variable "SourceDir"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds"
)
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variable "appl"
value "HDL Designer"
)
(vvPair
variable "arch_name"
value "struct"
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(vvPair
variable "concat_file"
value "<TBD>"
)
(vvPair
variable "config"
value "%(unit)_config"
)
(vvPair
variable "d"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
)
(vvPair
variable "d_logical"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3"
)
(vvPair
variable "date"
value "22.03.2024"
)
(vvPair
variable "day"
value "ven."
)
(vvPair
variable "day_long"
value "vendredi"
)
(vvPair
variable "dd"
value "22"
)
(vvPair
variable "designName"
value "<TBD>"
)
(vvPair
variable "entity_name"
value "tb_24_1_3"
)
(vvPair
variable "ext"
value "<TBD>"
)
(vvPair
variable "f"
value "struct.bd"
)
(vvPair
variable "f_logical"
value "struct.bd"
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(vvPair
variable "f_noext"
value "struct"
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(vvPair
variable "graphical_source_author"
value "remi.heredero"
)
(vvPair
variable "graphical_source_date"
value "22.03.2024"
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variable "graphical_source_group"
value "UNKNOWN"
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variable "graphical_source_host"
value "WE2330808"
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(vvPair
variable "graphical_source_time"
value "13:45:47"
)
(vvPair
variable "group"
value "UNKNOWN"
)
(vvPair
variable "host"
value "WE2330808"
)
(vvPair
variable "language"
value "VHDL"
)
(vvPair
variable "library"
value "VHD_test"
)
(vvPair
variable "library_downstream_HdsLintPlugin"
value "$HDS_PROJECT_DIR/../VHD_test/designcheck"
)
(vvPair
variable "library_downstream_ModelSim"
value "D:\\Users\\FCo_HEVs\\Cours\\SEm\\Examens HDL\\VHDL_comp"
)
(vvPair
variable "library_downstream_ModelSimCompiler"
value "$SCRATCH_DIR/Exam/VHD_test/work"
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variable "mm"
value "03"
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variable "module_name"
value "tb_24_1_3"
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(vvPair
variable "month"
value "mars"
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variable "month_long"
value "mars"
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variable "p"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
)
(vvPair
variable "p_logical"
value "C:\\Users\\remi.heredero\\GIT\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_3\\struct.bd"
)
(vvPair
variable "package_name"
value "<Undefined Variable>"
)
(vvPair
variable "project_name"
value "hds"
)
(vvPair
variable "series"
value "HDL Designer Series"
)
(vvPair
variable "task_DesignCompilerPath"
value "<TBD>"
)
(vvPair
variable "task_HDSPath"
value "$HDS_HOME"
)
(vvPair
variable "task_ISEBinPath"
value "<TBD>"
)
(vvPair
variable "task_ISEPath"
value "<TBD>"
)
(vvPair
variable "task_LeonardoPath"
value "<TBD>"
)
(vvPair
variable "task_ModelSimPath"
value "$MODELSIM_HOME"
)
(vvPair
variable "task_NC-SimPath"
value "<TBD>"
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(vvPair
variable "task_PrecisionRTLPath"
value "<TBD>"
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(vvPair
variable "task_QuestaSimPath"
value "<TBD>"
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(vvPair
variable "task_VCSPath"
value "<TBD>"
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variable "this_ext"
value "bd"
)
(vvPair
variable "this_file"
value "struct"
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(vvPair
variable "this_file_logical"
value "struct"
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(vvPair
variable "time"
value "13:45:47"
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(vvPair
variable "unit"
value "tb_24_1_3"
)
(vvPair
variable "user"
value "remi.heredero"
)
(vvPair
variable "version"
value "2019.2 (Build 5)"
)
(vvPair
variable "view"
value "struct"
)
(vvPair
variable "year"
value "2024"
)
(vvPair
variable "yy"
value "24"
)
]
)
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xt "44200,54000,57000,55000"
st "
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tm "CommentText"
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st "
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shape (Rectangle
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va (VaSet
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text (MLText
uid 135,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "40200,53000,42300,54000"
st "
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tm "CommentText"
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position 1
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uid 136,0
shape (Rectangle
uid 137,0
sl 0
va (VaSet
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fg "65280,65280,46080"
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xt "40000,54000,44000,55000"
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oxt "14000,70000,18000,71000"
text (MLText
uid 138,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
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xt "40200,54000,42900,55000"
st "
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tm "CommentText"
wrapOption 3
visibleHeight 1000
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position 1
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uid 139,0
shape (Rectangle
uid 140,0
sl 0
va (VaSet
vasetType 1
fg "65280,65280,46080"
)
xt "44000,53000,61000,54000"
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oxt "18000,69000,35000,70000"
text (MLText
uid 141,0
va (VaSet
fg "0,0,32768"
bg "0,0,32768"
)
xt "44200,53000,54400,54000"
st "
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tm "CommentText"
wrapOption 3
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position 1
ignorePrefs 1
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]
shape (GroupingShape
uid 111,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
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xt "40000,50000,81000,55000"
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)
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uid 445,0
optionalChildren [
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uid 450,0
commentText (CommentText
uid 451,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 452,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "7000,24000,37000,34000"
)
oxt "0,0,18000,5000"
text (MLText
uid 453,0
va (VaSet
)
xt "7200,24200,25400,29200"
st "
reset <= '1', '0' after 2*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
testMode <= '1', '0' after 100*clockPeriod;
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 10000
visibleWidth 30000
)
)
)
]
shape (Rectangle
uid 446,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "6000,23000,38000,35000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 447,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*14 (Text
uid 448,0
va (VaSet
)
xt "6400,35000,8000,36000"
st "eb1"
blo "6400,35800"
tm "HdlTextNameMgr"
)
*15 (Text
uid 449,0
va (VaSet
)
xt "6400,36000,7200,37000"
st "1"
blo "6400,36800"
tm "HdlTextNumberMgr"
)
]
)
)
*16 (Net
uid 1122,0
decl (Decl
n "clock"
t "std_ulogic"
o 1
suid 11,0
)
declText (MLText
uid 1123,0
va (VaSet
)
xt "2000,15800,12600,16800"
st "SIGNAL clock : std_ulogic"
)
)
*17 (Net
uid 1130,0
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 12,0
)
declText (MLText
uid 1131,0
va (VaSet
)
xt "2000,17800,12500,18800"
st "SIGNAL reset : std_ulogic"
)
)
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uid 1503,0
decl (Decl
n "pwmEn"
t "std_ulogic"
o 2
suid 15,0
)
declText (MLText
uid 1504,0
va (VaSet
)
xt "2000,16800,13400,17800"
st "SIGNAL pwmEn : std_ulogic"
)
)
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uid 1511,0
decl (Decl
n "testMode"
t "std_ulogic"
o 4
suid 16,0
)
declText (MLText
uid 1512,0
va (VaSet
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xt "2000,18800,13300,19800"
st "SIGNAL testMode : std_ulogic"
)
)
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uid 1601,0
optionalChildren [
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uid 1585,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1586,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,26625,46000,27375"
)
tg (CPTG
uid 1587,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1588,0
va (VaSet
font "Arial,9,0"
)
xt "47000,26550,51300,27750"
st "testMode"
blo "47000,27450"
)
)
thePort (LogicalPort
decl (Decl
n "testMode"
t "std_ulogic"
o 1
suid 2004,0
)
)
)
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uid 1589,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1590,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,30625,46000,31375"
)
tg (CPTG
uid 1591,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1592,0
va (VaSet
font "Arial,9,0"
)
xt "47000,30550,49700,31750"
st "clock"
blo "47000,31450"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 2
suid 2005,0
)
)
)
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uid 1593,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1594,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "45250,32625,46000,33375"
)
tg (CPTG
uid 1595,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1596,0
va (VaSet
font "Arial,9,0"
)
xt "47000,32550,49600,33750"
st "reset"
blo "47000,33450"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 3
suid 2006,0
)
)
)
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uid 1597,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1598,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,26625,62750,27375"
)
tg (CPTG
uid 1599,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1600,0
va (VaSet
font "Arial,9,0"
)
xt "57500,26550,61000,27750"
st "pwmEn"
ju 2
blo "61000,27450"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "pwmEn"
t "std_ulogic"
o 4
suid 2007,0
)
)
)
]
shape (Rectangle
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va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
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oxt "32000,12000,48000,24000"
ttg (MlTextGroup
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stg "VerticalLayoutStrategy"
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va (VaSet
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xt "46600,34800,49100,35900"
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tm "CptNameMgr"
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matrix (Matrix
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text (MLText
uid 1609,0
va (VaSet
)
xt "46000,38400,58500,40400"
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)
header ""
)
elements [
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value "14"
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type "positive"
value "1"
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]
)
ordering 1
portVis (PortSigDisplay
sTC 0
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archFileType "UNKNOWN"
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va (VaSet
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)
xt "38000,31000,45250,31000"
pts [
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]
)
start &22
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
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ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1129,0
va (VaSet
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)
xt "40250,29700,43750,31200"
st "clock"
blo "40250,30900"
tm "WireNameMgr"
)
)
on &16
)
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uid 1132,0
shape (OrthoPolyLine
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va (VaSet
vasetType 3
)
xt "38000,33000,45250,33000"
pts [
"45250,33000"
"38000,33000"
]
)
start &23
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1137,0
va (VaSet
font "Arial,12,0"
)
xt "40250,31700,43750,33200"
st "reset"
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tm "WireNameMgr"
)
)
on &17
)
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uid 1505,0
shape (OrthoPolyLine
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va (VaSet
vasetType 3
)
xt "62750,27000,70000,27000"
pts [
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"70000,27000"
]
)
start &24
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1509,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1510,0
va (VaSet
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)
xt "64750,25700,69650,27200"
st "pwmEn"
blo "64750,26900"
tm "WireNameMgr"
)
)
on &18
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uid 1514,0
va (VaSet
vasetType 3
)
xt "38000,27000,45250,27000"
pts [
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"38000,27000"
]
)
start &21
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1517,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1518,0
va (VaSet
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)
xt "38250,25700,43950,27200"
st "testMode"
blo "38250,26900"
tm "WireNameMgr"
)
)
on &19
)
]
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grid (Grid
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isActive 1
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xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
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stg "VerticalLayoutStrategy"
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