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8b2f630f7b
SEm-ExamMidterm2024/VHD_test/hds/tb_24_1_4/struct.bd
Klagarge 8b2f630f7b Initial commit
2024-03-22 13:16:48 +01:00

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DocumentHdrVersion "1.1"
Header (DocumentHdr
version 2
dialect 11
dmPackageRefs [
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library "ieee"
unitName "std_logic_1164"
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library "ieee"
unitName "numeric_std"
itemName "ALL"
)
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instances [
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duLibraryName "VHD"
duName "ex_24_1_4"
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embeddedInstances [
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libraryRefs [
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version "32.1"
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noEmbeddedEditors 1
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variable "HDSDir"
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)
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variable "SideDataDesignDir"
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)
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variable "appl"
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value "struct"
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variable "config"
value "%(unit)_config"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4"
)
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variable "dd"
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variable "designName"
value "<TBD>"
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variable "ext"
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variable "f"
value "struct.bd"
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value "remy.borgeat"
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value "20.03.2024"
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variable "language"
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variable "month_long"
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value "C:\\Users\\remy.borgeat\\Documents\\Exam_24_1\\Exam_24_1\\Exam_24_1\\Prefs\\..\\VHD_test\\hds\\tb_24_1_4\\struct.bd"
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variable "view"
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(vvPair
variable "year"
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reset <= '1', '0' after 2*clockPeriod;
sClock <= not sClock after clockPeriod/2;
clock <= transport sClock after clockPeriod*9/10;
process
constant stepDelay: time := 1 us;
begin
wait for stepDelay;
for index in 0 to 10 loop
position_int <= position_int + 1;
wait for stepDelay;
end loop;
for index in 10 downto 0 loop
position_int <= position_int - 1;
wait for stepDelay;
end loop;
wait;
end process;
process(position_int)
begin
case to_integer(to_unsigned(position_int, 2)) is
when 0 => A <= '0'; B <= '0';
when 1 => A <= '1'; B <= '0';
when 2 => A <= '1'; B <= '1';
when 3 => A <= '0'; B <= '1';
when others => null;
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tm "WireNameMgr"
)
)
on &16
)
*33 (Wire
uid 1116,0
shape (OrthoPolyLine
uid 1117,0
va (VaSet
vasetType 3
)
xt "38000,27000,45250,27000"
pts [
"38000,27000"
"45250,27000"
]
)
start &12
end &24
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1120,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1121,0
va (VaSet
font "Arial,12,0"
)
xt "43000,25700,44500,27200"
st "B"
blo "43000,26900"
tm "WireNameMgr"
)
)
on &17
)
*34 (Wire
uid 1124,0
shape (OrthoPolyLine
uid 1125,0
va (VaSet
vasetType 3
)
xt "38000,31000,45250,31000"
pts [
"45250,31000"
"38000,31000"
]
)
start &25
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1128,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1129,0
va (VaSet
font "Arial,12,0"
)
xt "40250,29700,43750,31200"
st "clock"
blo "40250,30900"
tm "WireNameMgr"
)
)
on &18
)
*35 (Wire
uid 1132,0
shape (OrthoPolyLine
uid 1133,0
va (VaSet
vasetType 3
)
xt "38000,33000,45250,33000"
pts [
"45250,33000"
"38000,33000"
]
)
start &26
end &12
sat 32
eat 2
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1136,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1137,0
va (VaSet
font "Arial,12,0"
)
xt "40250,31700,43750,33200"
st "reset"
blo "40250,32900"
tm "WireNameMgr"
)
)
on &19
)
*36 (Wire
uid 1282,0
shape (OrthoPolyLine
uid 1283,0
va (VaSet
vasetType 3
)
xt "62750,27000,70000,27000"
pts [
"62750,27000"
"70000,27000"
]
)
start &28
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1286,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1287,0
va (VaSet
font "Arial,12,0"
)
xt "64750,25700,66850,27200"
st "dir"
blo "64750,26900"
tm "WireNameMgr"
)
)
on &20
)
*37 (Wire
uid 1290,0
shape (OrthoPolyLine
uid 1291,0
va (VaSet
vasetType 3
)
xt "62750,25000,70000,25000"
pts [
"62750,25000"
"70000,25000"
]
)
start &27
sat 32
eat 16
stc 0
st 0
sf 1
si 0
tg (WTG
uid 1294,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 1295,0
va (VaSet
font "Arial,12,0"
)
xt "64750,23700,66850,25200"
st "en"
blo "64750,24900"
tm "WireNameMgr"
)
)
on &21
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 1
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *38 (PackageList
uid 142,0
stg "VerticalLayoutStrategy"
textVec [
*39 (Text
uid 143,0
va (VaSet
font "Arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*40 (MLText
uid 144,0
va (VaSet
)
xt "0,1000,11200,4000"
st "LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.ALL;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 145,0
stg "VerticalLayoutStrategy"
textVec [
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uid 146,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,0,28100,1000"
st "Compiler Directives"
blo "20000,800"
)
*42 (Text
uid 147,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,1000,29600,2000"
st "Pre-module directives:"
blo "20000,1800"
)
*43 (MLText
uid 148,0
va (VaSet
isHidden 1
)
xt "20000,2000,27600,4000"
st "`resetall
`timescale 1ns/10ps"
tm "BdCompilerDirectivesTextMgr"
)
*44 (Text
uid 149,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,4000,30100,5000"
st "Post-module directives:"
blo "20000,4800"
)
*45 (MLText
uid 150,0
va (VaSet
isHidden 1
)
xt "20000,0,20000,0"
tm "BdCompilerDirectivesTextMgr"
)
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uid 151,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "20000,5000,29900,6000"
st "End-module directives:"
blo "20000,5800"
)
*47 (MLText
uid 152,0
va (VaSet
isHidden 1
)
xt "20000,6000,20000,6000"
tm "BdCompilerDirectivesTextMgr"
)
]
associable 1
)
windowSize "260,93,1448,938"
viewArea "-1200,-1200,83280,54856"
cachedDiagramExtent "0,0,81000,55000"
pageSetupInfo (PageSetupInfo
ptrCmd "Generic PostScript Printer,winspool,"
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toPrinter 1
xMargin 48
yMargin 48
paperWidth 1077
paperHeight 761
unixPaperWidth 595
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windowsPaperWidth 1077
windowsPaperHeight 761
paperType "A4"
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windowsPaperName "A4"
scale 90
exportedDirectories [
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]
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)
hasePageBreakOrigin 1
pageBreakOrigin "0,0"
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shape (Rectangle
layer 0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,15000,5000"
)
text (MLText
va (VaSet
fg "65535,0,0"
)
xt "200,200,2100,1200"
st "
Text
"
tm "CommentText"
wrapOption 3
visibleHeight 4600
visibleWidth 14600
)
)
defaultRequirementText (RequirementText
shape (ZoomableIcon
layer 0
va (VaSet
vasetType 1
fg "59904,39936,65280"
lineColor "0,0,32768"
)
xt "0,0,1500,1750"
iconName "reqTracerRequirement.bmp"
iconMaskName "reqTracerRequirement.msk"
)
autoResize 1
text (MLText
va (VaSet
fg "0,0,32768"
)
xt "500,2150,1400,3150"
st "
Text
"
tm "RequirementText"
wrapOption 3
visibleHeight 1350
visibleWidth 1100
)
)
defaultPanel (Panel
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "32768,0,0"
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (Text
va (VaSet
font "Arial,10,1"
)
xt "1000,1000,4400,2200"
st "Panel0"
blo "1000,2000"
tm "PanelText"
)
)
)
defaultBlk (Blk
shape (Rectangle
va (VaSet
vasetType 1
fg "40000,56832,65535"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*48 (Text
va (VaSet
font "Arial,9,0"
)
xt "1700,3200,6300,4400"
st "<library>"
blo "1700,4200"
tm "BdLibraryNameMgr"
)
*49 (Text
va (VaSet
font "Arial,9,0"
)
xt "1700,4400,5800,5600"
st "<block>"
blo "1700,5400"
tm "BlkNameMgr"
)
*50 (Text
va (VaSet
font "Arial,9,0"
)
xt "1700,5600,2900,6800"
st "I0"
blo "1700,6600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "1700,13200,1700,13200"
)
header ""
)
elements [
]
)
)
defaultMWComponent (MWC
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*51 (Text
va (VaSet
)
xt "1000,3500,3300,4500"
st "Library"
blo "1000,4300"
)
*52 (Text
va (VaSet
)
xt "1000,4500,7000,5500"
st "MWComponent"
blo "1000,5300"
)
*53 (Text
va (VaSet
)
xt "1000,5500,1600,6500"
st "I0"
blo "1000,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6000,1500,-6000,1500"
)
header ""
)
elements [
]
)
prms (Property
pclass "params"
pname "params"
ptn "String"
)
visOptions (mwParamsVisibilityOptions
)
)
defaultSaComponent (SaComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*54 (Text
va (VaSet
)
xt "1250,3500,3550,4500"
st "Library"
blo "1250,4300"
tm "BdLibraryNameMgr"
)
*55 (Text
va (VaSet
)
xt "1250,4500,6750,5500"
st "SaComponent"
blo "1250,5300"
tm "CptNameMgr"
)
*56 (Text
va (VaSet
)
xt "1250,5500,1850,6500"
st "I0"
blo "1250,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-5750,1500,-5750,1500"
)
header ""
)
elements [
]
)
archFileType "UNKNOWN"
)
defaultVhdlComponent (VhdlComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*57 (Text
va (VaSet
)
xt "950,3500,3250,4500"
st "Library"
blo "950,4300"
)
*58 (Text
va (VaSet
)
xt "950,4500,7050,5500"
st "VhdlComponent"
blo "950,5300"
)
*59 (Text
va (VaSet
)
xt "950,5500,1550,6500"
st "I0"
blo "950,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6050,1500,-6050,1500"
)
header ""
)
elements [
]
)
entityPath ""
archName ""
archPath ""
)
defaultVerilogComponent (VerilogComponent
shape (Rectangle
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "-50,0,8050,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*60 (Text
va (VaSet
)
xt "450,3500,2750,4500"
st "Library"
blo "450,4300"
)
*61 (Text
va (VaSet
)
xt "450,4500,7550,5500"
st "VerilogComponent"
blo "450,5300"
)
*62 (Text
va (VaSet
)
xt "450,5500,1050,6500"
st "I0"
blo "450,6300"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
ps "EdgeToEdgeStrategy"
matrix (Matrix
text (MLText
va (VaSet
isHidden 1
)
xt "-6550,1500,-6550,1500"
)
header ""
)
elements [
]
)
entityPath ""
)
defaultHdlText (HdlText
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "0,0,8000,10000"
)
ttg (MlTextGroup
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*63 (Text
va (VaSet
)
xt "3400,4000,4600,5000"
st "eb1"
blo "3400,4800"
tm "HdlTextNameMgr"
)
*64 (Text
va (VaSet
)
xt "3400,5000,3800,6000"
st "1"
blo "3400,5800"
tm "HdlTextNumberMgr"
)
]
)
)
defaultEmbeddedText (EmbeddedText
commentText (CommentText
ps "CenterOffsetStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "0,0,18000,5000"
)
text (MLText
va (VaSet
)
xt "200,200,2100,1200"
st "
Text
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 4600
visibleWidth 17600
)
)
)
defaultGlobalConnector (GlobalConnector
shape (Circle
va (VaSet
vasetType 1
fg "65535,65535,0"
)
xt "-1000,-1000,1000,1000"
radius 1000
)
name (Text
va (VaSet
)
xt "-300,-500,300,500"
st "G"
blo "-300,300"
)
)
defaultRipper (Ripper
ps "OnConnectorStrategy"
shape (Line2D
pts [
"0,0"
"1000,1000"
]
va (VaSet
vasetType 1
)
xt "0,0,1000,1000"
)
)
defaultBdJunction (BdJunction
ps "OnConnectorStrategy"
shape (Circle
va (VaSet
vasetType 1
)
xt "-400,-400,400,400"
radius 400
)
)
defaultPortIoIn (PortIoIn
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "-2000,-375,-500,375"
)
(Line
sl 0
ro 270
xt "-500,0,0,0"
pts [
"-500,0"
"0,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "-1375,-1000,-1375,-1000"
ju 2
blo "-1375,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoOut (PortIoOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Pentagon
sl 0
ro 270
xt "500,-375,2000,375"
)
(Line
sl 0
ro 270
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "625,-1000,625,-1000"
blo "625,-1000"
tm "WireNameMgr"
)
)
)
defaultPortIoInOut (PortIoInOut
shape (CompositeShape
va (VaSet
vasetType 1
fg "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultPortIoBuffer (PortIoBuffer
shape (CompositeShape
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,32768"
)
optionalChildren [
(Hexagon
sl 0
xt "500,-375,2000,375"
)
(Line
sl 0
xt "0,0,500,0"
pts [
"0,0"
"500,0"
]
)
]
)
tg (WTG
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
isHidden 1
font "Arial,12,0"
)
xt "0,-375,0,-375"
blo "0,-375"
tm "WireNameMgr"
)
)
)
defaultSignal (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Arial,12,0"
)
xt "0,0,2600,1400"
st "sig0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBus (Wire
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineWidth 2
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
va (VaSet
font "Arial,12,0"
)
xt "0,0,3900,1400"
st "dbus0"
blo "0,1200"
tm "WireNameMgr"
)
)
)
defaultBundle (Bundle
shape (OrthoPolyLine
va (VaSet
vasetType 3
lineStyle 3
lineWidth 1
)
pts [
"0,0"
"0,0"
]
)
ss 0
es 0
sat 32
eat 32
textGroup (BiTextGroup
ps "ConnStartEndStrategy"
stg "VerticalLayoutStrategy"
first (Text
va (VaSet
)
xt "0,0,2600,1000"
st "bundle0"
blo "0,800"
tm "BundleNameMgr"
)
second (MLText
va (VaSet
)
xt "0,1000,1000,2000"
st "()"
tm "BundleContentsMgr"
)
)
bundleNet &0
)
defaultPortMapFrame (PortMapFrame
ps "PortMapFrameStrategy"
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "0,0,50000"
lineWidth 2
)
xt "0,0,10000,12000"
)
portMapText (BiTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
first (MLText
va (VaSet
)
xt "0,0,3100,1000"
st "Auto list"
)
second (MLText
va (VaSet
)
xt "0,1000,6300,2000"
st "User defined list"
tm "PortMapTextMgr"
)
)
)
defaultGenFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 2
lineWidth 3
)
xt "0,0,20000,20000"
)
title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,12500,-100"
st "g0: FOR i IN 0 TO n GENERATE"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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va (VaSet
font "Arial,8,1"
)
xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*66 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
)
]
)
)
defaultBlockFrame (Frame
shape (RectFrame
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineColor "28160,28160,28160"
lineStyle 1
lineWidth 3
)
xt "0,0,20000,20000"
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title (TextAssociate
ps "TopLeftStrategy"
text (MLText
va (VaSet
)
xt "0,-1100,7300,-100"
st "b0: BLOCK (guard)"
tm "FrameTitleTextMgr"
)
)
seqNum (FrameSequenceNumber
ps "TopLeftStrategy"
shape (Rectangle
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "50,50,1050,1450"
)
num (Text
va (VaSet
)
xt "350,250,750,1250"
st "1"
blo "350,1050"
tm "FrameSeqNumMgr"
)
)
decls (MlTextGroup
ps "BottomRightOffsetStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "14100,20000,22000,21000"
st "Frame Declarations"
blo "14100,20800"
)
*68 (MLText
va (VaSet
)
xt "14100,21000,14100,21000"
tm "BdFrameDeclTextMgr"
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]
)
style 3
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defaultSaCptPort (CptPort
ps "OnEdgeStrategy"
shape (Triangle
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "0,0,750,750"
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tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultSaCptPortBuffer (CptPort
ps "OnEdgeStrategy"
shape (Diamond
va (VaSet
vasetType 1
fg "65535,65535,65535"
)
xt "0,0,750,750"
)
tg (CPTG
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
va (VaSet
)
xt "0,750,1400,1750"
st "Port"
blo "0,1550"
)
)
thePort (LogicalPort
m 3
decl (Decl
n "Port"
t ""
o 0
)
)
)
defaultDeclText (MLText
va (VaSet
)
)
archDeclarativeBlock (BdArchDeclBlock
uid 1,0
stg "BdArchDeclBlockLS"
declLabel (Text
uid 2,0
va (VaSet
font "Arial,8,1"
)
xt "0,4800,5400,5800"
st "Declarations"
blo "0,5600"
)
portLabel (Text
uid 3,0
va (VaSet
font "Arial,8,1"
)
xt "0,5800,2700,6800"
st "Ports:"
blo "0,6600"
)
preUserLabel (Text
uid 4,0
va (VaSet
font "Arial,8,1"
)
xt "0,6800,3800,7800"
st "Pre User:"
blo "0,7600"
)
preUserText (MLText
uid 5,0
va (VaSet
)
xt "2000,7800,23700,12800"
st "constant clockFrequency : real := 100.0E6;
constant clockPeriod : time := (1.0/clockFrequency) * 1 sec;
signal sClock : std_uLogic := '1';
signal position_int : integer := 0;"
tm "BdDeclarativeTextMgr"
)
diagSignalLabel (Text
uid 6,0
va (VaSet
font "Arial,8,1"
)
xt "0,12800,7100,13800"
st "Diagram Signals:"
blo "0,13600"
)
postUserLabel (Text
uid 7,0
va (VaSet
isHidden 1
font "Arial,8,1"
)
xt "0,4800,4700,5800"
st "Post User:"
blo "0,5600"
)
postUserText (MLText
uid 8,0
va (VaSet
isHidden 1
)
xt "0,4800,0,4800"
tm "BdDeclarativeTextMgr"
)
)
commonDM (CommonDM
ldm (LogicalDM
suid 14,0
usingSuid 1
emptyRow *69 (LEmptyRow
)
uid 565,0
optionalChildren [
*70 (RefLabelRowHdr
)
*71 (TitleRowHdr
)
*72 (FilterRowHdr
)
*73 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*74 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*75 (GroupColHdr
tm "GroupColHdrMgr"
)
*76 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*77 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*78 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*79 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*80 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*81 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*82 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "A"
t "std_ulogic"
o 1
suid 9,0
)
)
uid 1140,0
)
*83 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "B"
t "std_ulogic"
o 2
suid 10,0
)
)
uid 1142,0
)
*84 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "clock"
t "std_ulogic"
o 3
suid 11,0
)
)
uid 1144,0
)
*85 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "reset"
t "std_ulogic"
o 6
suid 12,0
)
)
uid 1146,0
)
*86 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "dir"
t "std_ulogic"
o 4
suid 13,0
)
)
uid 1296,0
)
*87 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "en"
t "std_ulogic"
o 5
suid 14,0
)
)
uid 1298,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 578,0
optionalChildren [
*88 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *89 (MRCItem
litem &69
pos 6
dimension 20
)
uid 580,0
optionalChildren [
*90 (MRCItem
litem &70
pos 0
dimension 20
uid 581,0
)
*91 (MRCItem
litem &71
pos 1
dimension 23
uid 582,0
)
*92 (MRCItem
litem &72
pos 2
hidden 1
dimension 20
uid 583,0
)
*93 (MRCItem
litem &82
pos 0
dimension 20
uid 1141,0
)
*94 (MRCItem
litem &83
pos 1
dimension 20
uid 1143,0
)
*95 (MRCItem
litem &84
pos 2
dimension 20
uid 1145,0
)
*96 (MRCItem
litem &85
pos 3
dimension 20
uid 1147,0
)
*97 (MRCItem
litem &86
pos 4
dimension 20
uid 1297,0
)
*98 (MRCItem
litem &87
pos 5
dimension 20
uid 1299,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 584,0
optionalChildren [
*99 (MRCItem
litem &73
pos 0
dimension 20
uid 585,0
)
*100 (MRCItem
litem &75
pos 1
dimension 50
uid 586,0
)
*101 (MRCItem
litem &76
pos 2
dimension 100
uid 587,0
)
*102 (MRCItem
litem &77
pos 3
dimension 50
uid 588,0
)
*103 (MRCItem
litem &78
pos 4
dimension 100
uid 589,0
)
*104 (MRCItem
litem &79
pos 5
dimension 100
uid 590,0
)
*105 (MRCItem
litem &80
pos 6
dimension 50
uid 591,0
)
*106 (MRCItem
litem &81
pos 7
dimension 80
uid 592,0
)
]
)
fixedCol 4
fixedRow 2
name "Ports"
uid 579,0
vaOverrides [
]
)
]
)
uid 564,0
)
genericsCommonDM (CommonDM
ldm (LogicalDM
emptyRow *107 (LEmptyRow
)
uid 594,0
optionalChildren [
*108 (RefLabelRowHdr
)
*109 (TitleRowHdr
)
*110 (FilterRowHdr
)
*111 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*112 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*113 (GroupColHdr
tm "GroupColHdrMgr"
)
*114 (NameColHdr
tm "GenericNameColHdrMgr"
)
*115 (TypeColHdr
tm "GenericTypeColHdrMgr"
)
*116 (InitColHdr
tm "GenericValueColHdrMgr"
)
*117 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*118 (EolColHdr
tm "GenericEolColHdrMgr"
)
]
)
pdm (PhysicalDM
uid 606,0
optionalChildren [
*119 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
)
emptyMRCItem *120 (MRCItem
litem &107
pos 0
dimension 20
)
uid 608,0
optionalChildren [
*121 (MRCItem
litem &108
pos 0
dimension 20
uid 609,0
)
*122 (MRCItem
litem &109
pos 1
dimension 23
uid 610,0
)
*123 (MRCItem
litem &110
pos 2
hidden 1
dimension 20
uid 611,0
)
]
)
sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
textAngle 90
)
uid 612,0
optionalChildren [
*124 (MRCItem
litem &111
pos 0
dimension 20
uid 613,0
)
*125 (MRCItem
litem &113
pos 1
dimension 50
uid 614,0
)
*126 (MRCItem
litem &114
pos 2
dimension 100
uid 615,0
)
*127 (MRCItem
litem &115
pos 3
dimension 100
uid 616,0
)
*128 (MRCItem
litem &116
pos 4
dimension 50
uid 617,0
)
*129 (MRCItem
litem &117
pos 5
dimension 50
uid 618,0
)
*130 (MRCItem
litem &118
pos 6
dimension 80
uid 619,0
)
]
)
fixedCol 3
fixedRow 2
name "Ports"
uid 607,0
vaOverrides [
]
)
]
)
uid 593,0
type 1
)
activeModelName "BlockDiag"
)
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