53 lines
1.4 KiB
VHDL
53 lines
1.4 KiB
VHDL
architecture studentVersion of ex_24_1_5 is
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signal running : std_ulogic;
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signal deccel : std_ulogic;
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signal counter : unsigned(speedBitNb/2-1 downto 0);
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signal accumulator : unsigned(speedBitNb-1 downto 0);
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begin
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process(clock, reset) begin
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if reset = '1' then
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running <= '0';
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deccel <= '0';
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counter <= (others => '0');
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accumulator <= (others => '0');
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speed <= (others => '0');
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done <= '0';
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elsif rising_edge(clock) then
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if start = '1' then
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running <= '1';
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deccel <= '0';
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counter <= (others => '0');
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accumulator <= (others => '0'); -- Comment this line if you want 2 accel without overflow (l.38-39)
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end if;
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if running = '1' then
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if deccel = '0' then
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counter <= counter + 1;
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else
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counter <= counter - 1;
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end if;
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accumulator <= accumulator + counter;
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speed <= accumulator;
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end if;
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--if ((counter = 2**(speedBitNb/2-1)) and (deccel = '0')) then -- For 2 accel without overflow
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if ((counter = 2**((speedBitNb/2))-2) and (deccel = '0')) then -- For best fit for only one acceleration
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deccel <= '1';
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done <= '1';
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else
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done <= '0';
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end if;
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if ((deccel = '1') and (counter = 0)) then
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running <= '0';
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end if;
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end if;
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end process;
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end studentVersion;
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