--
-- VHDL Architecture WaveformGenerator_test.waveformGen_tb.struct
--
-- Created:
--          by - remi.heredero.UNKNOWN (WE2330808)
--          at - 15:12:57 01.03.2024
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY WaveformGenerator;
LIBRARY WaveformGenerator_test;

ARCHITECTURE struct OF waveformGen_tb IS

    -- Architecture declarations
    constant bitNb: positive := 16;
    constant signalBitNb: positive := 16;
    constant phaseBitNb: positive := 16;
    --constant clockFrequency: real := 60.0E6;
    constant clockFrequency: real := 66.0E6;

    -- Internal signal declarations
    SIGNAL clock    : std_ulogic;
    SIGNAL en       : std_ulogic;
    SIGNAL polygon  : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL reset    : std_ulogic;
    SIGNAL sawtooth : unsigned(phaseBitNb-1 DOWNTO 0);
    SIGNAL sine     : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL square   : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL step     : unsigned(bitNb-1 DOWNTO 0);
    SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);


    -- Component Declarations
    COMPONENT waveformGen
    GENERIC (
        phaseBitNb  : positive := 16;
        signalBitNb : positive := 16
    );
    PORT (
        clock    : IN     std_ulogic ;
        en       : IN     std_ulogic ;
        reset    : IN     std_ulogic ;
        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        polygon  : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        sawtooth : OUT    unsigned (phaseBitNb-1 DOWNTO 0);
        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
    );
    END COMPONENT;
    COMPONENT waveformGen_tester
    GENERIC (
        bitNb          : positive := 16;
        clockFrequency : real     := 60.0E6;
        phaseBitNb     : positive := 16;
        signalBitNb    : positive := 16
    );
    PORT (
        polygon  : IN     unsigned (signalBitNb-1 DOWNTO 0);
        sawtooth : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
        clock    : OUT    std_ulogic ;
        en       : OUT    std_ulogic ;
        reset    : OUT    std_ulogic ;
        step     : OUT    unsigned (bitNb-1 DOWNTO 0)
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : waveformGen USE ENTITY WaveformGenerator.waveformGen;
    FOR ALL : waveformGen_tester USE ENTITY WaveformGenerator_test.waveformGen_tester;
    -- pragma synthesis_on


BEGIN

    -- Instance port mappings.
    I_DUT : waveformGen
        GENERIC MAP (
            phaseBitNb  => bitNb,
            signalBitNb => bitNb
        )
        PORT MAP (
            clock    => clock,
            en       => en,
            reset    => reset,
            step     => step,
            polygon  => polygon,
            sawtooth => sawtooth,
            sine     => sine,
            square   => square,
            triangle => triangle
        );
    I_tb : waveformGen_tester
        GENERIC MAP (
            bitNb          => bitNb,
            clockFrequency => clockFrequency
        )
        PORT MAP (
            polygon  => polygon,
            sawtooth => sawtooth,
            sine     => sine,
            square   => square,
            triangle => triangle,
            clock    => clock,
            en       => en,
            reset    => reset,
            step     => step
        );

END struct;
