--
-- VHDL Architecture SplineInterpolator_test.sineGen_tb.struct
--
-- Created:
--          by - axel.amand.UNKNOWN (WE7860)
--          at - 14:41:39 28.04.2023
--
-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
--
LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.numeric_std.ALL;

LIBRARY SplineInterpolator;
LIBRARY SplineInterpolator_test;

ARCHITECTURE struct OF sineGen_tb IS

    -- Architecture declarations
    constant signalBitNb: positive := 16;
    constant phaseBitNb: positive := 10;
    constant clockFrequency: real := 60.0E6;
    --constant clockFrequency: real := 66.0E6;

    -- Internal signal declarations
    SIGNAL clock    : std_ulogic;
    SIGNAL reset    : std_ulogic;
    SIGNAL sawtooth : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL sine     : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL square   : unsigned(signalBitNb-1 DOWNTO 0);
    SIGNAL step     : unsigned(phaseBitNb-1 DOWNTO 0);
    SIGNAL triangle : unsigned(signalBitNb-1 DOWNTO 0);


    -- Component Declarations
    COMPONENT sineGen
    GENERIC (
        signalBitNb : positive := 16;
        phaseBitNb  : positive := 10
    );
    PORT (
        clock    : IN     std_ulogic ;
        reset    : IN     std_ulogic ;
        step     : IN     unsigned (phaseBitNb-1 DOWNTO 0);
        sawtooth : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        sine     : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        square   : OUT    unsigned (signalBitNb-1 DOWNTO 0);
        triangle : OUT    unsigned (signalBitNb-1 DOWNTO 0)
    );
    END COMPONENT;
    COMPONENT sineGen_tester
    GENERIC (
        signalBitNb    : positive := 16;
        phaseBitNb     : positive := 10;
        clockFrequency : real     := 60.0E6
    );
    PORT (
        sawtooth : IN     unsigned (signalBitNb-1 DOWNTO 0);
        sine     : IN     unsigned (signalBitNb-1 DOWNTO 0);
        square   : IN     unsigned (signalBitNb-1 DOWNTO 0);
        triangle : IN     unsigned (signalBitNb-1 DOWNTO 0);
        clock    : OUT    std_ulogic ;
        reset    : OUT    std_ulogic ;
        step     : OUT    unsigned (phaseBitNb-1 DOWNTO 0)
    );
    END COMPONENT;

    -- Optional embedded configurations
    -- pragma synthesis_off
    FOR ALL : sineGen USE ENTITY SplineInterpolator.sineGen;
    FOR ALL : sineGen_tester USE ENTITY SplineInterpolator_test.sineGen_tester;
    -- pragma synthesis_on


BEGIN

    -- Instance port mappings.
    I_DUT : sineGen
        GENERIC MAP (
            signalBitNb => signalBitNb,
            phaseBitNb  => phaseBitNb
        )
        PORT MAP (
            clock    => clock,
            reset    => reset,
            step     => step,
            sawtooth => sawtooth,
            sine     => sine,
            square   => square,
            triangle => triangle
        );
    I_tb : sineGen_tester
        GENERIC MAP (
            signalBitNb    => signalBitNb,
            phaseBitNb     => phaseBitNb,
            clockFrequency => clockFrequency
        )
        PORT MAP (
            sawtooth => sawtooth,
            sine     => sine,
            square   => square,
            triangle => triangle,
            clock    => clock,
            reset    => reset,
            step     => step
        );

END struct;
