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t "std_uLogic"
o 2
)
)
)
*32 (CptPort
uid 184,0
ps "OnEdgeStrategy"
shape (Triangle
uid 185,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "62000,30625,62750,31375"
)
tg (CPTG
uid 186,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 187,0
va (VaSet
font "Verdana,12,0"
)
xt "59200,30300,61000,31700"
st "Q"
ju 2
blo "61000,31500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 163,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "56000,29000,62000,37000"
)
showPorts 0
oxt "23000,3000,29000,11000"
ttg (MlTextGroup
uid 164,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*33 (Text
uid 165,0
va (VaSet
)
xt "60600,36700,64200,37900"
st "Board"
blo "60600,37700"
tm "BdLibraryNameMgr"
)
*34 (Text
uid 166,0
va (VaSet
)
xt "60600,37700,63300,38900"
st "DFF"
blo "60600,38700"
tm "CptNameMgr"
)
*35 (Text
uid 167,0
va (VaSet
)
xt "60600,38700,62500,39900"
st "I8"
blo "60600,39700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 168,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 169,0
text (MLText
uid 170,0
va (VaSet
)
xt "63000,36400,63000,36400"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*36 (SaComponent
uid 188,0
optionalChildren [
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uid 197,0
ps "OnEdgeStrategy"
shape (Triangle
uid 198,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "55250,64625,56000,65375"
)
tg (CPTG
uid 199,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 200,0
va (VaSet
font "Verdana,12,0"
)
xt "57000,64300,58700,65700"
st "D"
blo "57000,65500"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*38 (CptPort
uid 201,0
optionalChildren [
*39 (FFT
pts [
"56750,69000"
"56000,69375"
"56000,68625"
]
uid 205,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "56000,68625,56750,69375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 202,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "55250,68625,56000,69375"
)
tg (CPTG
uid 203,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 204,0
va (VaSet
font "Verdana,12,0"
)
xt "57000,68400,60200,69800"
st "CLK"
blo "57000,69600"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*40 (CptPort
uid 206,0
ps "OnEdgeStrategy"
shape (Triangle
uid 207,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "58625,71000,59375,71750"
)
tg (CPTG
uid 208,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 209,0
va (VaSet
font "Verdana,12,0"
)
xt "58000,69600,61200,71000"
st "CLR"
blo "58000,70800"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*41 (CptPort
uid 210,0
ps "OnEdgeStrategy"
shape (Triangle
uid 211,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "62000,64625,62750,65375"
)
tg (CPTG
uid 212,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 213,0
va (VaSet
font "Verdana,12,0"
)
xt "59200,64300,61000,65700"
st "Q"
ju 2
blo "61000,65500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 189,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "56000,63000,62000,71000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 190,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*42 (Text
uid 191,0
va (VaSet
)
xt "62600,68700,66200,69900"
st "Board"
blo "62600,69700"
tm "BdLibraryNameMgr"
)
*43 (Text
uid 192,0
va (VaSet
)
xt "62600,69700,65300,70900"
st "DFF"
blo "62600,70700"
tm "CptNameMgr"
)
*44 (Text
uid 193,0
va (VaSet
)
xt "62600,70700,65200,71900"
st "I12"
blo "62600,71700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 194,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 195,0
text (MLText
uid 196,0
va (VaSet
)
xt "33000,60000,33000,60000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*45 (SaComponent
uid 214,0
optionalChildren [
*46 (CptPort
uid 223,0
optionalChildren [
*47 (Circle
uid 228,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "67092,64546,68000,65454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 224,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "66342,64625,67092,65375"
)
tg (CPTG
uid 225,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 226,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "68000,64500,70700,65900"
st "in1"
blo "68000,65700"
)
s (Text
uid 227,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "68000,65900,68000,65900"
blo "68000,65900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*48 (CptPort
uid 229,0
ps "OnEdgeStrategy"
shape (Triangle
uid 230,0
ro 90
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "73000,64625,73750,65375"
)
tg (CPTG
uid 231,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 232,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "69050,64500,72750,65900"
st "out1"
ju 2
blo "72750,65700"
)
s (Text
uid 233,0
va (VaSet
isHidden 1
font "Verdana,12,0"
)
xt "72750,65900,72750,65900"
ju 2
blo "72750,65900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 215,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "68000,62000,73000,68000"
)
showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 216,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*49 (Text
uid 217,0
va (VaSet
isHidden 1
)
xt "68910,60700,72510,61900"
st "Board"
blo "68910,61700"
tm "BdLibraryNameMgr"
)
*50 (Text
uid 218,0
va (VaSet
isHidden 1
)
xt "68910,61700,75310,62900"
st "inverterIn"
blo "68910,62700"
tm "CptNameMgr"
)
*51 (Text
uid 219,0
va (VaSet
)
xt "68910,61700,70810,62900"
st "I3"
blo "68910,62700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 220,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 221,0
text (MLText
uid 222,0
va (VaSet
)
xt "45000,58000,45000,58000"
)
header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*52 (SaComponent
uid 234,0
optionalChildren [
*53 (CptPort
uid 243,0
ps "OnEdgeStrategy"
shape (Triangle
uid 244,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "78250,40625,79000,41375"
)
tg (CPTG
uid 245,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 246,0
va (VaSet
)
xt "80000,40400,83400,41600"
st "clock"
blo "80000,41400"
)
)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_ulogic"
o 7
)
)
)
*54 (CptPort
uid 247,0
ps "OnEdgeStrategy"
shape (Triangle
uid 248,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,36625,95750,37375"
)
tg (CPTG
uid 249,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 250,0
va (VaSet
)
xt "91001,36400,94001,37600"
st "outX"
ju 2
blo "94001,37400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outX"
t "std_ulogic"
o 3
)
)
)
*55 (CptPort
uid 251,0
ps "OnEdgeStrategy"
shape (Triangle
uid 252,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,38625,95750,39375"
)
tg (CPTG
uid 253,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 254,0
va (VaSet
)
xt "91001,38400,94001,39600"
st "outY"
ju 2
blo "94001,39400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "outY"
t "std_ulogic"
o 4
)
)
)
*56 (CptPort
uid 255,0
ps "OnEdgeStrategy"
shape (Triangle
uid 256,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,40625,95750,41375"
)
tg (CPTG
uid 257,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 258,0
va (VaSet
)
xt "88201,40400,94001,41600"
st "selSinCos"
ju 2
blo "94001,41400"
)
)
thePort (LogicalPort
decl (Decl
n "selSinCos"
t "std_ulogic"
o 5
)
)
)
*57 (CptPort
uid 259,0
ps "OnEdgeStrategy"
shape (Triangle
uid 260,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "78250,42625,79000,43375"
)
tg (CPTG
uid 261,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 262,0
va (VaSet
)
xt "80000,42400,83300,43600"
st "reset"
blo "80000,43400"
)
)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_ulogic"
o 6
)
)
)
*58 (CptPort
uid 263,0
ps "OnEdgeStrategy"
shape (Triangle
uid 264,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "78250,28625,79000,29375"
)
tg (CPTG
uid 265,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 266,0
va (VaSet
)
xt "80000,28400,82800,29600"
st "TxD"
blo "80000,29400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "TxD"
t "std_ulogic"
o 1
)
)
)
*59 (CptPort
uid 267,0
ps "OnEdgeStrategy"
shape (Triangle
uid 268,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "78250,30625,79000,31375"
)
tg (CPTG
uid 269,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 270,0
va (VaSet
)
xt "80000,30400,82800,31600"
st "RxD"
blo "80000,31400"
)
)
thePort (LogicalPort
decl (Decl
n "RxD"
t "std_ulogic"
o 2
)
)
)
*60 (CptPort
uid 271,0
ps "OnEdgeStrategy"
shape (Triangle
uid 272,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,28625,95750,29375"
)
tg (CPTG
uid 273,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 274,0
va (VaSet
)
xt "91100,28400,94000,29600"
st "ioEn"
ju 2
blo "94000,29400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioEn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 8
)
)
)
*61 (CptPort
uid 275,0
ps "OnEdgeStrategy"
shape (Triangle
uid 276,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,30625,95750,31375"
)
tg (CPTG
uid 277,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 278,0
va (VaSet
)
xt "90500,30400,94000,31600"
st "ioOut"
ju 2
blo "94000,31400"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "ioOut"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 9
)
)
)
*62 (CptPort
uid 279,0
ps "OnEdgeStrategy"
shape (Triangle
uid 280,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "95000,32625,95750,33375"
)
tg (CPTG
uid 281,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 282,0
va (VaSet
)
xt "91300,32400,94000,33600"
st "ioIn"
ju 2
blo "94000,33400"
)
)
thePort (LogicalPort
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 10
)
)
)
*63 (CptPort
uid 283,0
ps "OnEdgeStrategy"
shape (Triangle
uid 284,0
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "86625,24250,87375,25000"
)
tg (CPTG
uid 285,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 286,0
va (VaSet
)
xt "85000,26000,89600,27200"
st "testOut"
ju 2
blo "89600,27000"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 11
)
)
)
]
shape (Rectangle
uid 235,0
va (VaSet
vasetType 1
fg "0,65535,0"
bg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "79000,25000,95000,45000"
)
oxt "36000,10000,52000,30000"
ttg (MlTextGroup
uid 236,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*64 (Text
uid 237,0
va (VaSet
font "Verdana,9,1"
)
xt "79600,44800,88000,46000"
st "SystemOnChip"
blo "79600,45800"
tm "BdLibraryNameMgr"
)
*65 (Text
uid 238,0
va (VaSet
font "Verdana,9,1"
)
xt "79600,45700,85600,46900"
st "beamerSoc"
blo "79600,46700"
tm "CptNameMgr"
)
*66 (Text
uid 239,0
va (VaSet
font "Verdana,9,1"
)
xt "79600,46600,83000,47800"
st "I_top"
blo "79600,47600"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 240,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 241,0
text (MLText
uid 242,0
va (VaSet
font "Verdana,8,0"
)
xt "79000,48600,104800,51600"
st "ioNb                = ioNb                   ( positive )  
testOutBitNb        = testOutBitNb           ( positive )  
patternAddressBitNb = patternAddressBitNb    ( positive )  "
)
header ""
)
elements [
(GiElement
name "ioNb"
type "positive"
value "ioNb"
)
(GiElement
name "testOutBitNb"
type "positive"
value "testOutBitNb"
)
(GiElement
name "patternAddressBitNb"
type "positive"
value "patternAddressBitNb"
)
]
)
ordering 1
portVis (PortSigDisplay
sTC 0
)
archFileType "UNKNOWN"
)
*67 (HdlText
uid 287,0
optionalChildren [
*68 (EmbeddedText
uid 292,0
commentText (CommentText
uid 293,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 294,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "91000,2000,107000,8000"
)
oxt "0,0,18000,5000"
text (MLText
uid 295,0
va (VaSet
)
xt "91200,2200,105900,8200"
st "
LED1 <= testOut(1);
LED2 <= testOut(2);
spare(testOut'range) <= testOut;
spare(testOut'high+1 to spare'high) <= (others => '0');
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 6000
visibleWidth 16000
)
)
)
]
shape (Rectangle
uid 288,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "91000,1000,107000,9000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 289,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*69 (Text
uid 290,0
va (VaSet
)
xt "91400,9000,94000,10200"
st "eb3"
blo "91400,10000"
tm "HdlTextNameMgr"
)
*70 (Text
uid 291,0
va (VaSet
)
xt "91400,10000,92800,11200"
st "3"
blo "91400,11000"
tm "HdlTextNumberMgr"
)
]
)
)
*71 (SaComponent
uid 296,0
optionalChildren [
*72 (CptPort
uid 305,0
ps "OnEdgeStrategy"
shape (Triangle
uid 306,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "110000,42625,110750,43375"
)
tg (CPTG
uid 307,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 308,0
va (VaSet
font "Verdana,12,0"
)
xt "107300,42300,109000,43700"
st "D"
ju 2
blo "109000,43500"
)
)
thePort (LogicalPort
decl (Decl
n "D"
t "std_uLogic"
o 3
)
)
)
*73 (CptPort
uid 309,0
optionalChildren [
*74 (FFT
pts [
"109250,47000"
"110000,46625"
"110000,47375"
]
uid 313,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "109250,46625,110000,47375"
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 310,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "110000,46625,110750,47375"
)
tg (CPTG
uid 311,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 312,0
va (VaSet
font "Verdana,12,0"
)
xt "105800,46400,109000,47800"
st "CLK"
ju 2
blo "109000,47600"
)
)
thePort (LogicalPort
decl (Decl
n "CLK"
t "std_uLogic"
o 1
)
)
)
*75 (CptPort
uid 314,0
ps "OnEdgeStrategy"
shape (Triangle
uid 315,0
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "106625,49000,107375,49750"
)
tg (CPTG
uid 316,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 317,0
va (VaSet
font "Verdana,12,0"
)
xt "104800,47600,108000,49000"
st "CLR"
blo "104800,48800"
)
)
thePort (LogicalPort
decl (Decl
n "CLR"
t "std_uLogic"
o 2
)
)
)
*76 (CptPort
uid 318,0
ps "OnEdgeStrategy"
shape (Triangle
uid 319,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "103250,42625,104000,43375"
)
tg (CPTG
uid 320,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 321,0
va (VaSet
font "Verdana,12,0"
)
xt "105000,42300,106800,43700"
st "Q"
blo "105000,43500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "Q"
t "std_uLogic"
o 4
)
)
)
]
shape (Rectangle
uid 297,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
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xt "104000,41000,110000,49000"
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oxt "0,0,8000,10000"
ttg (MlTextGroup
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ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
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uid 299,0
va (VaSet
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xt "110600,46700,114200,47900"
st "Board"
blo "110600,47700"
tm "BdLibraryNameMgr"
)
*78 (Text
uid 300,0
va (VaSet
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xt "110600,47700,113300,48900"
st "DFF"
blo "110600,48700"
tm "CptNameMgr"
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*79 (Text
uid 301,0
va (VaSet
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xt "110600,48700,112500,49900"
st "I9"
blo "110600,49700"
tm "InstanceNameMgr"
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ga (GenericAssociation
uid 302,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 303,0
text (MLText
uid 304,0
va (VaSet
)
xt "81000,38000,81000,38000"
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header ""
)
elements [
]
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portVis (PortSigDisplay
sTC 0
sT 1
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archFileType "UNKNOWN"
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*80 (PortIoOut
uid 322,0
shape (CompositeShape
uid 323,0
va (VaSet
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fg "0,0,32768"
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uid 324,0
sl 0
ro 270
xt "115500,2625,117000,3375"
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(Line
uid 325,0
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ro 270
xt "115000,3000,115500,3000"
pts [
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tg (WTG
uid 326,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "118000,2300,122000,3700"
st "LED1"
blo "118000,3500"
tm "WireNameMgr"
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shape (CompositeShape
uid 329,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 330,0
sl 0
ro 270
xt "115500,4625,117000,5375"
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(Line
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sl 0
ro 270
xt "115000,5000,115500,5000"
pts [
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)
]
)
tg (WTG
uid 332,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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font "Verdana,12,0"
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xt "118000,4300,122000,5700"
st "LED2"
blo "118000,5500"
tm "WireNameMgr"
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)
*82 (PortIoOut
uid 334,0
shape (CompositeShape
uid 335,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 336,0
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ro 270
xt "115500,6625,117000,7375"
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(Line
uid 337,0
sl 0
ro 270
xt "115000,7000,115500,7000"
pts [
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]
)
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)
tg (WTG
uid 338,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "118000,6300,130400,7700"
st "spare : (1 TO 17)"
blo "118000,7500"
tm "WireNameMgr"
)
)
)
*83 (SaComponent
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uid 349,0
optionalChildren [
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uid 354,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "122000,42546,122908,43454"
radius 454
)
]
ps "OnEdgeStrategy"
shape (Triangle
uid 350,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
)
xt "122908,42625,123658,43375"
)
tg (CPTG
uid 351,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 352,0
va (VaSet
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font "Verdana,12,0"
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xt "379566,42500,382266,43900"
st "in1"
ju 2
blo "382266,43700"
)
s (Text
uid 353,0
va (VaSet
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font "Verdana,12,0"
)
xt "382266,43900,382266,43900"
ju 2
blo "382266,43900"
)
)
thePort (LogicalPort
decl (Decl
n "in1"
t "std_uLogic"
o 1
)
)
)
*86 (CptPort
uid 355,0
ps "OnEdgeStrategy"
shape (Triangle
uid 356,0
ro 270
va (VaSet
vasetType 1
isHidden 1
fg "0,65535,0"
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xt "116250,42625,117000,43375"
)
tg (CPTG
uid 357,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "367300,42500,371000,43900"
st "out1"
blo "367300,43700"
)
s (Text
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va (VaSet
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font "Verdana,12,0"
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xt "367300,43900,367300,43900"
blo "367300,43900"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "out1"
t "std_uLogic"
o 2
)
)
)
]
shape (Buf
uid 341,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "117000,40000,122000,46000"
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showPorts 0
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 342,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 343,0
va (VaSet
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xt "117910,38700,121510,39900"
st "Board"
blo "117910,39700"
tm "BdLibraryNameMgr"
)
*88 (Text
uid 344,0
va (VaSet
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)
xt "117910,39700,124310,40900"
st "inverterIn"
blo "117910,40700"
tm "CptNameMgr"
)
*89 (Text
uid 345,0
va (VaSet
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xt "117910,39700,119810,40900"
st "I7"
blo "117910,40700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 346,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 347,0
text (MLText
uid 348,0
va (VaSet
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xt "94000,36000,94000,36000"
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header ""
)
elements [
]
)
portVis (PortSigDisplay
disp 1
sN 0
sTC 0
sT 1
)
archFileType "UNKNOWN"
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*90 (PortIoIn
uid 360,0
shape (CompositeShape
uid 361,0
va (VaSet
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fg "0,0,32768"
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uid 362,0
sl 0
ro 90
xt "127500,42625,129000,43375"
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(Line
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ro 90
xt "127000,43000,127500,43000"
pts [
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"127000,43000"
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]
)
tg (WTG
uid 364,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
)
xt "130000,42300,139300,43700"
st "selSinCos_n"
blo "130000,43500"
tm "WireNameMgr"
)
)
)
*91 (PortIoOut
uid 366,0
shape (CompositeShape
uid 367,0
va (VaSet
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fg "0,0,32768"
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optionalChildren [
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uid 368,0
sl 0
ro 270
xt "127500,36625,129000,37375"
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(Line
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sl 0
ro 270
xt "127000,37000,127500,37000"
pts [
"127000,37000"
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)
]
)
tg (WTG
uid 370,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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font "Verdana,12,0"
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xt "130000,36300,133800,37700"
st "xOut"
blo "130000,37500"
tm "WireNameMgr"
)
)
)
*92 (PortIoOut
uid 372,0
shape (CompositeShape
uid 373,0
va (VaSet
vasetType 1
fg "0,0,32768"
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optionalChildren [
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uid 374,0
sl 0
ro 270
xt "127500,38625,129000,39375"
)
(Line
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sl 0
ro 270
xt "127000,39000,127500,39000"
pts [
"127000,39000"
"127500,39000"
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)
]
)
tg (WTG
uid 376,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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xt "130000,38300,133800,39700"
st "yOut"
blo "130000,39500"
tm "WireNameMgr"
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*93 (Net
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n "selSinCos"
t "std_ulogic"
o 1
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declText (MLText
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va (VaSet
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xt "2000,32200,17000,33200"
st "SIGNAL selSinCos      : std_ulogic
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decl (Decl
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t "std_ulogic"
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declText (MLText
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va (VaSet
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xt "2000,33200,17900,34200"
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*95 (Net
uid 500,0
decl (Decl
n "resetSynch_N"
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o 3
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declText (MLText
uid 501,0
va (VaSet
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xt "2000,30200,17800,31200"
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)
)
*96 (Net
uid 502,0
decl (Decl
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t "std_ulogic"
o 4
suid 4,0
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declText (MLText
uid 503,0
va (VaSet
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xt "2000,13000,14200,14000"
st "selSinCos_n    : std_ulogic
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)
)
*97 (Net
uid 504,0
decl (Decl
n "resetSynch"
t "std_ulogic"
o 5
suid 5,0
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declText (MLText
uid 505,0
va (VaSet
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xt "2000,29200,17300,30200"
st "SIGNAL resetSynch     : std_ulogic
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)
)
*98 (Net
uid 506,0
decl (Decl
n "ioIn"
t "std_ulogic_vector"
b "(ioNb-1 DOWNTO 0)"
o 6
suid 6,0
)
declText (MLText
uid 507,0
va (VaSet
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xt "2000,25400,28000,26400"
st "SIGNAL ioIn           : std_ulogic_vector(ioNb-1 DOWNTO 0)
"
)
)
*99 (Net
uid 508,0
decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 7,0
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declText (MLText
uid 509,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,11000,13200,12000"
st "clock          : std_ulogic
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)
)
*100 (Net
uid 510,0
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 8
suid 8,0
)
declText (MLText
uid 511,0
va (VaSet
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xt "2000,34200,28200,35200"
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*101 (Net
uid 512,0
decl (Decl
n "spare"
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b "(1 TO 17)"
o 9
suid 9,0
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declText (MLText
uid 513,0
va (VaSet
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xt "2000,16800,20900,17800"
st "spare          : std_ulogic_vector(1 TO 17)
"
)
)
*102 (Net
uid 516,0
decl (Decl
n "yOut"
t "std_ulogic"
o 11
suid 11,0
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declText (MLText
uid 517,0
va (VaSet
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)
xt "2000,18800,13400,19800"
st "yOut           : std_ulogic
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)
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*103 (Net
uid 518,0
decl (Decl
n "reset_N"
t "std_ulogic"
o 12
suid 12,0
)
declText (MLText
uid 519,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,12000,13700,13000"
st "reset_N        : std_ulogic
"
)
)
*104 (Net
uid 520,0
decl (Decl
n "rxdSynch"
t "std_ulogic"
o 13
suid 13,0
)
declText (MLText
uid 521,0
va (VaSet
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)
xt "2000,31200,17200,32200"
st "SIGNAL rxdSynch       : std_ulogic
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)
)
*105 (Net
uid 524,0
decl (Decl
n "LED1"
t "std_ulogic"
o 15
suid 15,0
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declText (MLText
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va (VaSet
font "Verdana,8,0"
)
xt "2000,14000,13500,15000"
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)
)
*106 (Net
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decl (Decl
n "LED2"
t "std_ulogic"
o 16
suid 16,0
)
declText (MLText
uid 527,0
va (VaSet
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)
xt "2000,15000,13500,16000"
st "LED2           : std_ulogic
"
)
)
*107 (Net
uid 528,0
decl (Decl
n "xOut"
t "std_ulogic"
o 17
suid 17,0
)
declText (MLText
uid 529,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,17800,13400,18800"
st "xOut           : std_ulogic
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)
)
*108 (Net
uid 530,0
decl (Decl
n "logic1"
t "std_uLogic"
o 18
suid 18,0
)
declText (MLText
uid 531,0
va (VaSet
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)
xt "2000,27200,16600,28200"
st "SIGNAL logic1         : std_uLogic
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)
)
*109 (Net
uid 532,0
decl (Decl
n "reset"
t "std_ulogic"
o 19
suid 19,0
)
declText (MLText
uid 533,0
va (VaSet
font "Verdana,8,0"
)
xt "2000,28200,16400,29200"
st "SIGNAL reset          : std_ulogic
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)
)
*110 (SaComponent
uid 653,0
optionalChildren [
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uid 617,0
ps "OnEdgeStrategy"
shape (Triangle
uid 618,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,51625,62750,52375"
)
tg (CPTG
uid 619,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
font "Verdana,8,0"
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xt "56700,51500,61000,52500"
st "clk10MHz"
ju 2
blo "61000,52300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "clk10MHz"
t "std_ulogic"
o 8
suid 1,0
)
)
)
*112 (CptPort
uid 621,0
ps "OnEdgeStrategy"
shape (Triangle
uid 622,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,50625,62750,51375"
)
tg (CPTG
uid 623,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 624,0
va (VaSet
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)
xt "56700,50500,61000,51500"
st "clk50MHz"
ju 2
blo "61000,51300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "clk50MHz"
t "std_ulogic"
o 7
suid 2,0
)
)
)
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uid 625,0
ps "OnEdgeStrategy"
shape (Triangle
uid 626,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,47625,62750,48375"
)
tg (CPTG
uid 627,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 628,0
va (VaSet
font "Verdana,8,0"
)
xt "56700,47500,61000,48500"
st "clk60MHz"
ju 2
blo "61000,48300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "clk60MHz"
t "std_ulogic"
o 5
suid 3,0
)
)
)
*114 (CptPort
uid 629,0
ps "OnEdgeStrategy"
shape (Triangle
uid 630,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,49625,62750,50375"
)
tg (CPTG
uid 631,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 632,0
va (VaSet
font "Verdana,8,0"
)
xt "56700,49500,61000,50500"
st "clk75MHz"
ju 2
blo "61000,50300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "clk75MHz"
t "std_ulogic"
o 6
suid 4,0
)
)
)
*115 (CptPort
uid 633,0
ps "OnEdgeStrategy"
shape (Triangle
uid 634,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,51625,50000,52375"
)
tg (CPTG
uid 635,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 636,0
va (VaSet
font "Verdana,8,0"
)
xt "51000,51500,54200,52500"
st "en10M"
blo "51000,52300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en10M"
t "std_ulogic"
o 4
suid 6,0
)
)
)
*116 (CptPort
uid 637,0
ps "OnEdgeStrategy"
shape (Triangle
uid 638,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,50625,50000,51375"
)
tg (CPTG
uid 639,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 640,0
va (VaSet
font "Verdana,8,0"
)
xt "51000,50500,54200,51500"
st "en50M"
blo "51000,51300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en50M"
t "std_ulogic"
o 3
suid 7,0
)
)
)
*117 (CptPort
uid 641,0
ps "OnEdgeStrategy"
shape (Triangle
uid 642,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,49625,50000,50375"
)
tg (CPTG
uid 643,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 644,0
va (VaSet
font "Verdana,8,0"
)
xt "51000,49500,54200,50500"
st "en75M"
blo "51000,50300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "en75M"
t "std_ulogic"
o 2
suid 8,0
)
)
)
*118 (CptPort
uid 645,0
ps "OnEdgeStrategy"
shape (Triangle
uid 646,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "62000,53625,62750,54375"
)
tg (CPTG
uid 647,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 648,0
va (VaSet
font "Verdana,8,0"
)
xt "56800,53500,61000,54500"
st "pllLocked"
ju 2
blo "61000,54300"
)
)
thePort (LogicalPort
lang 11
m 1
decl (Decl
n "pllLocked"
t "std_ulogic"
o 9
suid 9,0
)
)
)
*119 (CptPort
uid 649,0
ps "OnEdgeStrategy"
shape (Triangle
uid 650,0
ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "49250,47625,50000,48375"
)
tg (CPTG
uid 651,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 652,0
va (VaSet
font "Verdana,8,0"
)
xt "51000,47500,55600,48500"
st "clkIn100M"
blo "51000,48300"
)
)
thePort (LogicalPort
lang 11
decl (Decl
n "clkIn100M"
t "std_ulogic"
o 1
suid 10,0
)
)
)
]
shape (Rectangle
uid 654,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "50000,47000,62000,55000"
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oxt "20000,20000,32000,28000"
ttg (MlTextGroup
uid 655,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
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uid 656,0
va (VaSet
font "Verdana,8,1"
)
xt "50400,57000,54100,58000"
st "Lattice"
blo "50400,57800"
tm "BdLibraryNameMgr"
)
*121 (Text
uid 657,0
va (VaSet
font "Verdana,8,1"
)
xt "50400,58000,52200,59000"
st "pll"
blo "50400,58800"
tm "CptNameMgr"
)
*122 (Text
uid 658,0
va (VaSet
font "Verdana,8,1"
)
xt "50400,59000,53200,60000"
st "I_pll"
blo "50400,59800"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 659,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 660,0
text (MLText
uid 661,0
va (VaSet
font "Courier New,8,0"
)
xt "26000,-22200,26000,-22200"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 662,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "50250,53250,51750,54750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
ordering 1
viewiconposition 0
portVis (PortSigDisplay
)
archFileType "UNKNOWN"
)
*123 (Net
uid 669,0
lang 11
decl (Decl
n "clk_sys"
t "std_ulogic"
o 20
suid 21,0
)
declText (MLText
uid 670,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,24600,20500,25400"
st "SIGNAL clk_sys        : std_ulogic
"
)
)
*124 (HdlText
uid 671,0
optionalChildren [
*125 (EmbeddedText
uid 676,0
commentText (CommentText
uid 677,0
ps "CenterOffsetStrategy"
shape (Rectangle
uid 678,0
va (VaSet
vasetType 1
fg "65535,65535,65535"
lineStyle 2
)
xt "34000,51000,40000,53000"
)
oxt "0,0,18000,5000"
text (MLText
uid 679,0
va (VaSet
)
xt "34200,51200,39700,52400"
st "
logic0 <= '0';
"
tm "HdlTextMgr"
wrapOption 3
visibleHeight 2000
visibleWidth 6000
)
)
)
]
shape (Rectangle
uid 672,0
va (VaSet
vasetType 1
fg "65535,65535,32768"
)
xt "33000,50000,41000,54000"
)
oxt "0,0,8000,10000"
ttg (MlTextGroup
uid 673,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*126 (Text
uid 674,0
va (VaSet
)
xt "33400,54000,36000,55200"
st "eb5"
blo "33400,55000"
tm "HdlTextNameMgr"
)
*127 (Text
uid 675,0
va (VaSet
)
xt "33400,55000,34800,56200"
st "5"
blo "33400,56000"
tm "HdlTextNumberMgr"
)
]
)
)
*128 (Net
uid 700,0
lang 11
decl (Decl
n "logic0"
t "std_ulogic"
o 21
suid 23,0
)
declText (MLText
uid 701,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,26400,20500,27200"
st "SIGNAL logic0         : std_ulogic
"
)
)
*129 (Net
uid 753,0
decl (Decl
n "RxD"
t "std_ulogic"
o 10
suid 24,0
)
declText (MLText
uid 754,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,10200,17000,11000"
st "RxD            : std_ulogic
"
)
)
*130 (Net
uid 755,0
decl (Decl
n "TxD"
t "std_ulogic"
o 14
suid 25,0
)
declText (MLText
uid 756,0
va (VaSet
font "Courier New,8,0"
)
xt "2000,16000,17000,16800"
st "TxD            : std_ulogic
"
)
)
*131 (Wire
uid 378,0
shape (OrthoPolyLine
uid 379,0
va (VaSet
vasetType 3
)
xt "53000,35000,56000,35000"
pts [
"53000,35000"
"56000,35000"
]
)
end &29
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 382,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 383,0
va (VaSet
font "Verdana,12,0"
)
xt "52000,33600,57300,35000"
st "clk_sys"
blo "52000,34800"
tm "WireNameMgr"
)
)
on &123
)
*132 (Wire
uid 384,0
shape (OrthoPolyLine
uid 385,0
va (VaSet
vasetType 3
)
xt "49000,71000,59000,73000"
pts [
"49000,73000"
"59000,73000"
"59000,71000"
]
)
start &19
end &40
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 386,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 387,0
va (VaSet
font "Verdana,12,0"
)
xt "50000,71600,54100,73000"
st "reset"
blo "50000,72800"
tm "WireNameMgr"
)
)
on &109
)
*133 (Wire
uid 388,0
shape (OrthoPolyLine
uid 389,0
va (VaSet
vasetType 3
)
xt "54000,69000,56000,69000"
pts [
"54000,69000"
"56000,69000"
]
)
end &38
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 392,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 393,0
va (VaSet
font "Verdana,12,0"
)
xt "52000,67600,55800,69000"
st "clock"
blo "52000,68800"
tm "WireNameMgr"
)
)
on &99
)
*134 (Wire
uid 394,0
shape (OrthoPolyLine
uid 395,0
va (VaSet
vasetType 3
)
xt "110000,47000,113000,47000"
pts [
"113000,47000"
"110000,47000"
]
)
end &73
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 398,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 399,0
va (VaSet
font "Verdana,12,0"
)
xt "112000,45600,117300,47000"
st "clk_sys"
blo "112000,46800"
tm "WireNameMgr"
)
)
on &123
)
*135 (Wire
uid 400,0
shape (OrthoPolyLine
uid 401,0
va (VaSet
vasetType 3
)
xt "122908,43000,127000,43000"
pts [
"122908,43000"
"127000,43000"
]
)
start &84
end &90
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 402,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 403,0
va (VaSet
font "Verdana,12,0"
)
xt "124000,41600,133300,43000"
st "selSinCos_n"
blo "124000,42800"
tm "WireNameMgr"
)
)
on &96
)
*136 (Wire
uid 404,0
shape (OrthoPolyLine
uid 405,0
va (VaSet
vasetType 3
)
xt "51000,65000,56000,65000"
pts [
"56000,65000"
"51000,65000"
]
)
start &37
end &23
sat 32
eat 2
stc 0
sf 1
si 0
tg (WTG
uid 408,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 409,0
va (VaSet
font "Verdana,12,0"
)
xt "52000,63600,56400,65000"
st "logic1"
blo "52000,64800"
tm "WireNameMgr"
)
)
on &108
)
*137 (Wire
uid 410,0
shape (OrthoPolyLine
uid 411,0
va (VaSet
vasetType 3
)
xt "110000,43000,117000,43000"
pts [
"110000,43000"
"117000,43000"
]
)
start &72
end &86
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 412,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 413,0
va (VaSet
font "Verdana,12,0"
)
xt "109000,41600,115900,43000"
st "selSinCos"
blo "109000,42800"
tm "WireNameMgr"
)
)
on &93
)
*138 (Wire
uid 414,0
shape (OrthoPolyLine
uid 415,0
va (VaSet
vasetType 3
)
xt "62000,65000,67092,65000"
pts [
"62000,65000"
"67092,65000"
]
)
start &41
end &46
ss 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 416,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 417,0
va (VaSet
font "Verdana,12,0"
)
xt "59000,63600,69300,65000"
st "resetSynch_N"
blo "59000,64800"
tm "WireNameMgr"
)
)
on &95
)
*139 (Wire
uid 418,0
shape (OrthoPolyLine
uid 419,0
va (VaSet
vasetType 3
)
xt "95750,41000,104000,43000"
pts [
"95750,41000"
"99000,41000"
"99000,43000"
"104000,43000"
]
)
start &56
end &76
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 420,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 421,0
va (VaSet
font "Verdana,12,0"
)
xt "97000,41600,108400,43000"
st "selSinCosSynch"
blo "97000,42800"
tm "WireNameMgr"
)
)
on &94
)
*140 (Wire
uid 422,0
shape (OrthoPolyLine
uid 423,0
va (VaSet
vasetType 3
)
xt "39000,31000,56000,31000"
pts [
"56000,31000"
"39000,31000"
]
)
start &28
end &14
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 424,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 425,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,29600,42200,31000"
st "RxD"
blo "39000,30800"
tm "WireNameMgr"
)
)
on &129
)
*141 (Wire
uid 426,0
shape (OrthoPolyLine
uid 427,0
va (VaSet
vasetType 3
)
xt "53000,37000,59000,39000"
pts [
"53000,39000"
"59000,39000"
"59000,37000"
]
)
end &31
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 430,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 431,0
va (VaSet
font "Verdana,12,0"
)
xt "52000,37600,60600,39000"
st "resetSynch"
blo "52000,38800"
tm "WireNameMgr"
)
)
on &97
)
*142 (Wire
uid 432,0
shape (OrthoPolyLine
uid 433,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "107000,7000,115000,7000"
pts [
"107000,7000"
"115000,7000"
]
)
start &67
end &82
sat 2
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 436,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 437,0
va (VaSet
font "Verdana,12,0"
)
xt "111000,5600,115400,7000"
st "spare"
blo "111000,6800"
tm "WireNameMgr"
)
)
on &101
)
*143 (Wire
uid 438,0
shape (OrthoPolyLine
uid 439,0
va (VaSet
vasetType 3
)
xt "73000,43000,78250,65000"
pts [
"78250,43000"
"77000,43000"
"77000,65000"
"73000,65000"
]
)
start &57
end &48
es 0
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 440,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 441,0
va (VaSet
font "Verdana,12,0"
)
xt "74000,63600,82600,65000"
st "resetSynch"
blo "74000,64800"
tm "WireNameMgr"
)
)
on &97
)
*144 (Wire
uid 442,0
shape (OrthoPolyLine
uid 443,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "87000,5000,91000,24250"
pts [
"87000,24250"
"87000,5000"
"91000,5000"
]
)
start &63
end &67
sat 32
eat 1
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 446,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 447,0
va (VaSet
font "Verdana,12,0"
)
xt "83000,3600,88600,5000"
st "testOut"
blo "83000,4800"
tm "WireNameMgr"
)
)
on &100
)
*145 (Wire
uid 448,0
shape (OrthoPolyLine
uid 449,0
va (VaSet
vasetType 3
)
xt "107000,49000,113000,51000"
pts [
"113000,51000"
"107000,51000"
"107000,49000"
]
)
end &75
sat 16
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 452,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 453,0
va (VaSet
font "Verdana,12,0"
)
xt "108000,49600,116600,51000"
st "resetSynch"
blo "108000,50800"
tm "WireNameMgr"
)
)
on &97
)
*146 (Wire
uid 454,0
shape (OrthoPolyLine
uid 455,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "95750,33000,103000,33000"
pts [
"95750,33000"
"103000,33000"
]
)
start &62
sat 32
eat 16
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 458,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 459,0
va (VaSet
font "Verdana,12,0"
)
xt "100000,31600,103200,33000"
st "ioIn"
blo "100000,32800"
tm "WireNameMgr"
)
)
on &98
)
*147 (Wire
uid 460,0
shape (OrthoPolyLine
uid 461,0
va (VaSet
vasetType 3
)
xt "62000,31000,78250,31000"
pts [
"78250,31000"
"62000,31000"
]
)
start &59
end &32
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 462,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 463,0
va (VaSet
font "Verdana,12,0"
)
xt "63000,29600,69500,31000"
st "rxdSynch"
blo "63000,30800"
tm "WireNameMgr"
)
)
on &104
)
*148 (Wire
uid 464,0
shape (OrthoPolyLine
uid 465,0
va (VaSet
vasetType 3
)
xt "95750,39000,127000,39000"
pts [
"127000,39000"
"95750,39000"
]
)
start &92
end &55
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 466,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 467,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,37600,126800,39000"
st "yOut"
blo "123000,38800"
tm "WireNameMgr"
)
)
on &102
)
*149 (Wire
uid 468,0
shape (OrthoPolyLine
uid 469,0
va (VaSet
vasetType 3
)
xt "39000,27000,78250,29000"
pts [
"78250,29000"
"67000,29000"
"67000,27000"
"39000,27000"
]
)
start &58
end &13
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 470,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 471,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,25600,42100,27000"
st "TxD"
blo "39000,26800"
tm "WireNameMgr"
)
)
on &130
)
*150 (Wire
uid 472,0
shape (OrthoPolyLine
uid 473,0
va (VaSet
vasetType 3
)
xt "107000,5000,115000,5000"
pts [
"107000,5000"
"115000,5000"
]
)
start &67
end &81
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 476,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 477,0
va (VaSet
font "Verdana,12,0"
)
xt "112000,3600,116000,5000"
st "LED2"
blo "112000,4800"
tm "WireNameMgr"
)
)
on &106
)
*151 (Wire
uid 478,0
shape (OrthoPolyLine
uid 479,0
va (VaSet
vasetType 3
)
xt "39000,48000,49250,48000"
pts [
"39000,48000"
"49250,48000"
]
)
start &15
end &119
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 480,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 481,0
va (VaSet
font "Verdana,12,0"
)
xt "39000,46600,42800,48000"
st "clock"
blo "39000,47800"
tm "WireNameMgr"
)
)
on &99
)
*152 (Wire
uid 482,0
shape (OrthoPolyLine
uid 483,0
va (VaSet
vasetType 3
)
xt "95750,37000,127000,37000"
pts [
"127000,37000"
"95750,37000"
]
)
start &91
end &54
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 484,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 485,0
va (VaSet
font "Verdana,12,0"
)
xt "123000,35600,126800,37000"
st "xOut"
blo "123000,36800"
tm "WireNameMgr"
)
)
on &107
)
*153 (Wire
uid 486,0
shape (OrthoPolyLine
uid 487,0
va (VaSet
vasetType 3
)
xt "107000,3000,115000,3000"
pts [
"107000,3000"
"115000,3000"
]
)
start &67
end &80
sat 2
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 490,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 491,0
va (VaSet
font "Verdana,12,0"
)
xt "112000,1600,116000,3000"
st "LED1"
blo "112000,2800"
tm "WireNameMgr"
)
)
on &105
)
*154 (Wire
uid 492,0
shape (OrthoPolyLine
uid 493,0
va (VaSet
vasetType 3
)
xt "39000,73000,43092,73000"
pts [
"39000,73000"
"43092,73000"
]
)
start &12
end &17
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 494,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 495,0
va (VaSet
font "Verdana,12,0"
)
xt "38000,71600,43800,73000"
st "reset_N"
blo "38000,72800"
tm "WireNameMgr"
)
)
on &103
)
*155 (Wire
uid 665,0
shape (OrthoPolyLine
uid 666,0
va (VaSet
vasetType 3
)
xt "62750,41000,78250,48000"
pts [
"62750,48000"
"70000,48000"
"70000,41000"
"78250,41000"
]
)
start &113
end &53
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 667,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 668,0
va (VaSet
)
xt "64750,46800,69350,48000"
st "clk_sys"
blo "64750,47800"
tm "WireNameMgr"
)
)
on &123
)
*156 (Wire
uid 682,0
optionalChildren [
*157 (BdJunction
uid 692,0
ps "OnConnectorStrategy"
shape (Circle
uid 693,0
va (VaSet
vasetType 1
)
xt "46600,50600,47400,51400"
radius 400
)
)
*158 (BdJunction
uid 698,0
ps "OnConnectorStrategy"
shape (Circle
uid 699,0
va (VaSet
vasetType 1
)
xt "46600,50600,47400,51400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 683,0
va (VaSet
vasetType 3
)
xt "41000,51000,49250,51000"
pts [
"41000,51000"
"49250,51000"
]
)
start &124
end &116
sat 2
eat 32
st 0
sf 1
si 0
tg (WTG
uid 686,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 687,0
va (VaSet
)
xt "43000,49800,46800,51000"
st "logic0"
blo "43000,50800"
tm "WireNameMgr"
)
)
on &128
)
*159 (Wire
uid 688,0
shape (OrthoPolyLine
uid 689,0
va (VaSet
vasetType 3
)
xt "47000,50000,49250,51000"
pts [
"49250,50000"
"47000,50000"
"47000,51000"
]
)
start &117
end &157
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 690,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 691,0
va (VaSet
isHidden 1
)
xt "44250,48800,48050,50000"
st "logic0"
blo "44250,49800"
tm "WireNameMgr"
)
)
on &128
)
*160 (Wire
uid 694,0
shape (OrthoPolyLine
uid 695,0
va (VaSet
vasetType 3
)
xt "47000,51000,49250,52000"
pts [
"49250,52000"
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suid 25,0
usingSuid 1
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)
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optionalChildren [
*193 (RefLabelRowHdr
)
*194 (TitleRowHdr
)
*195 (FilterRowHdr
)
*196 (RefLabelColHdr
tm "RefLabelColHdrMgr"
)
*197 (RowExpandColHdr
tm "RowExpandColHdrMgr"
)
*198 (GroupColHdr
tm "GroupColHdrMgr"
)
*199 (NameColHdr
tm "BlockDiagramNameColHdrMgr"
)
*200 (ModeColHdr
tm "BlockDiagramModeColHdrMgr"
)
*201 (TypeColHdr
tm "BlockDiagramTypeColHdrMgr"
)
*202 (BoundsColHdr
tm "BlockDiagramBoundsColHdrMgr"
)
*203 (InitColHdr
tm "BlockDiagramInitColHdrMgr"
)
*204 (EolColHdr
tm "BlockDiagramEolColHdrMgr"
)
*205 (LeafLogPort
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m 4
decl (Decl
n "selSinCos"
t "std_ulogic"
o 1
suid 1,0
)
)
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)
*206 (LeafLogPort
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m 4
decl (Decl
n "selSinCosSynch"
t "std_ulogic"
o 2
suid 2,0
)
)
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)
*207 (LeafLogPort
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m 4
decl (Decl
n "resetSynch_N"
t "std_ulogic"
o 3
suid 3,0
)
)
uid 538,0
)
*208 (LeafLogPort
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decl (Decl
n "selSinCos_n"
t "std_ulogic"
o 4
suid 4,0
)
)
uid 540,0
)
*209 (LeafLogPort
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m 4
decl (Decl
n "resetSynch"
t "std_ulogic"
o 5
suid 5,0
)
)
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)
*210 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "ioIn"
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b "(ioNb-1 DOWNTO 0)"
o 6
suid 6,0
)
)
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)
*211 (LeafLogPort
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decl (Decl
n "clock"
t "std_ulogic"
o 7
suid 7,0
)
)
uid 546,0
)
*212 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "testOut"
t "std_ulogic_vector"
b "(1 TO testOutBitNb)"
o 8
suid 8,0
)
)
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)
*213 (LeafLogPort
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m 1
decl (Decl
n "spare"
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b "(1 TO 17)"
o 9
suid 9,0
)
)
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)
*214 (LeafLogPort
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m 1
decl (Decl
n "yOut"
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o 11
suid 11,0
)
)
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)
*215 (LeafLogPort
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decl (Decl
n "reset_N"
t "std_ulogic"
o 12
suid 12,0
)
)
uid 556,0
)
*216 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "rxdSynch"
t "std_ulogic"
o 13
suid 13,0
)
)
uid 558,0
)
*217 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LED1"
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o 15
suid 15,0
)
)
uid 562,0
)
*218 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "LED2"
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o 16
suid 16,0
)
)
uid 564,0
)
*219 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "xOut"
t "std_ulogic"
o 17
suid 17,0
)
)
uid 566,0
)
*220 (LeafLogPort
port (LogicalPort
m 4
decl (Decl
n "logic1"
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o 18
suid 18,0
)
)
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)
*221 (LeafLogPort
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m 4
decl (Decl
n "reset"
t "std_ulogic"
o 19
suid 19,0
)
)
uid 570,0
)
*222 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "clk_sys"
t "std_ulogic"
o 20
suid 21,0
)
)
uid 702,0
)
*223 (LeafLogPort
port (LogicalPort
lang 11
m 4
decl (Decl
n "logic0"
t "std_ulogic"
o 21
suid 23,0
)
)
uid 704,0
)
*224 (LeafLogPort
port (LogicalPort
decl (Decl
n "RxD"
t "std_ulogic"
o 10
suid 24,0
)
)
uid 757,0
)
*225 (LeafLogPort
port (LogicalPort
m 1
decl (Decl
n "TxD"
t "std_ulogic"
o 14
suid 25,0
)
)
uid 759,0
)
]
)
pdm (PhysicalDM
displayShortBounds 1
editShortBounds 1
uid 67,0
optionalChildren [
*226 (Sheet
sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
fontColor "0,0,0"
font "Tahoma,10,0"
)
cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
)
groupVa (MVa
cellColor "39936,56832,65280"
fontColor "0,0,0"
font "Tahoma,10,0"
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emptyMRCItem *227 (MRCItem
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dimension 20
)
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optionalChildren [
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)
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dimension 23
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)
*230 (MRCItem
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hidden 1
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)
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pos 0
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)
*232 (MRCItem
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dimension 20
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)
*233 (MRCItem
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dimension 20
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uid 541,0
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*235 (MRCItem
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dimension 20
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)
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dimension 20
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*238 (MRCItem
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dimension 20
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)
*239 (MRCItem
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dimension 20
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dimension 20
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*241 (MRCItem
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dimension 20
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*249 (MRCItem
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dimension 20
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*251 (MRCItem
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uid 760,0
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sheetCol (SheetCol
propVa (MVa
cellColor "0,49152,49152"
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uid 74,0
)
*253 (MRCItem
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)
*255 (MRCItem
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*259 (MRCItem
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fixedCol 4
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name "Ports"
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vaOverrides [
]
)
]
)
uid 53,0
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genericsCommonDM (CommonDM
ldm (LogicalDM
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*261 (RefLabelRowHdr
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*262 (TitleRowHdr
)
*263 (FilterRowHdr
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*264 (RefLabelColHdr
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)
*265 (RowExpandColHdr
tm "RowExpandColHdrMgr"
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*266 (GroupColHdr
tm "GroupColHdrMgr"
)
*267 (NameColHdr
tm "GenericNameColHdrMgr"
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*268 (TypeColHdr
tm "GenericTypeColHdrMgr"
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*269 (InitColHdr
tm "GenericValueColHdrMgr"
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*270 (PragmaColHdr
tm "GenericPragmaColHdrMgr"
)
*271 (EolColHdr
tm "GenericEolColHdrMgr"
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]
)
pdm (PhysicalDM
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editShortBounds 1
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optionalChildren [
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sheetRow (SheetRow
headerVa (MVa
cellColor "49152,49152,49152"
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cellVa (MVa
cellColor "65535,65535,65535"
fontColor "0,0,0"
font "Tahoma,10,0"
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groupVa (MVa
cellColor "39936,56832,65280"
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font "Tahoma,10,0"
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pos 0
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)
*275 (MRCItem
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)
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hidden 1
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uid 100,0
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]
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sheetCol (SheetCol
propVa (MVa
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optionalChildren [
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*278 (MRCItem
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uid 104,0
)
*280 (MRCItem
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uid 105,0
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)
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uid 107,0
)
*283 (MRCItem
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]
)
fixedCol 3
fixedRow 2
name "Ports"
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vaOverrides [
]
)
]
)
uid 82,0
type 1
)
activeModelName "BlockDiag"
)
