2024-02-27 10:23:54 +00:00
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-- VHDL Entity WaveformGenerator.lowpass.symbol
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--
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-- Created:
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2024-03-05 10:48:52 +00:00
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-- by - remi.heredero.UNKNOWN (WE2330808)
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-- at - 15:16:08 01.03.2024
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2024-02-27 10:23:54 +00:00
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--
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-- Generated by Mentor Graphics' HDL Designer(TM) 2019.2 (Build 5)
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--
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LIBRARY ieee;
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USE ieee.std_logic_1164.all;
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USE ieee.numeric_std.all;
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ENTITY lowpass IS
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GENERIC(
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signalBitNb : positive := 16;
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shiftBitNb : positive := 12
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);
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PORT(
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lowpassOut : OUT unsigned (signalBitNb-1 DOWNTO 0);
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clock : IN std_ulogic;
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reset : IN std_ulogic;
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lowpassIn : IN unsigned (signalBitNb-1 DOWNTO 0)
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);
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-- Declarations
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END lowpass ;
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