14 lines
278 B
VHDL
14 lines
278 B
VHDL
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ARCHITECTURE studentVersion OF triangleToPolygon IS
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signal mySignal : unsigned(bitNb downto 0);
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BEGIN
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convert: process(triangle)
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begin
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mySignal <= triangle + shift_left(triangle, 1);
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end process convert;
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polygon <= mySignal;
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END ARCHITECTURE studentVersion;
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