84 lines
2.8 KiB
VHDL
84 lines
2.8 KiB
VHDL
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-- filename: debouncer.vhd
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-- kind: vhdl file
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-- first created: 05.03.2012
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-- created by: zas
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--------------------------------------------------------------------------------
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-- History:
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-- v0.1 : zas 05.03.2012 -- Initial Version
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-- v0.2 : cof 22.01.2013 -- synchronization to clock
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-- -- direct reaction on both edges
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--------------------------------------------------------------------------------
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-- Description:
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-- Debounces a button on both edges.
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-- _ _ ____________________ _ _
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-- input ____/ \_/ \_/ \_/ \_/ \______
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-- _____________________________
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-- output _____/ \____________
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--
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--------------------------------------------------------------------------------
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ARCHITECTURE rtl OF debouncer IS
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signal debounceCounter : unsigned(counterBitNb-1 downto 0);
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signal inputSynch, inputDelayed, inputChanged : std_ulogic;
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BEGIN
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------------------------------------------------------------------------------
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-- Synchronize input to clock
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synchInput: process(reset, clock)
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begin
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if reset = '1' then
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inputSynch <= '0';
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elsif rising_edge(clock) then
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inputSynch <= input xor invertInput;
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end if;
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end process synchInput;
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------------------------------------------------------------------------------
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-- Find edge on input
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delayInput: process(reset, clock)
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begin
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if reset = '1' then
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inputDelayed <= '0';
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elsif rising_edge(clock) then
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inputDelayed <= inputSynch;
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end if;
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end process delayInput;
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inputChanged <= '1' when inputDelayed /= inputSynch
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else '0';
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------------------------------------------------------------------------------
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-- Debounce counter
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countDeadTime: process(reset, clock)
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begin
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if reset = '1' then
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debounceCounter <= (others => '0');
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elsif rising_edge(clock) then
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if debounceCounter = 0 then
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if inputChanged = '1' then
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debounceCounter <= debounceCounter - 1;
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end if;
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else
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debounceCounter <= debounceCounter - 1;
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end if;
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end if;
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end process countDeadTime;
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------------------------------------------------------------------------------
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-- Update output
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updateOutput: process(reset, clock)
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begin
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if reset = '1' then
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debounced <= '0';
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elsif rising_edge(clock) then
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if (inputChanged = '1') and (debounceCounter = 0) then
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debounced <= input;
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elsif debounceCounter = 1 then
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debounced <= input;
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end if;
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end if;
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end process updateOutput;
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END ARCHITECTURE rtl;
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