52 lines
1.1 KiB
VHDL
52 lines
1.1 KiB
VHDL
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LIBRARY std;
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USE std.textio.ALL;
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LIBRARY ieee;
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USE ieee.std_logic_textio.ALL;
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LIBRARY Common_test;
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USE Common_test.testutils.all;
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ARCHITECTURE test OF universalTester IS
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constant clockPeriod : time := 1.0/66E6 * 1 sec;
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signal sClock : std_uLogic := '1';
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signal sReset : std_uLogic ;
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signal testInfo : string(1 to 40) := (others => ' ');
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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sReset <= '1', '0' after 3.5*clockPeriod;
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rst <= sReset;
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sClock <= not sClock after clockPeriod/2;
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clk <= transport sClock after 0.9*clockPeriod;
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btns <= (others => '1'), (others=>'0') after 4.15 us;
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process
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-- Wait list
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-- 3 clk for beq
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-- 4 clk for others
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-- 5 clk for lw
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begin
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en <= '0';
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testInfo <= pad("Wait reset", testInfo'length);
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wait until rst = '0';
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while true loop
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en <= '1';
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testInfo <= pad("Running", testInfo'length);
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wait;
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end loop;
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end process;
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END ARCHITECTURE test;
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