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SEm-Labos/02-SplineInterpolator/SplineInterpolator/hdl/resizer_studentVersion.vhd

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VHDL
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ARCHITECTURE studentVersion OF resizer IS
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signal mySignal : unsigned(outputBitNb-1 downto 0);
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BEGIN
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INPUT_BIGGER: if inputBitNb >= outputBitNb generate
process(resizeIn)
begin
mySignal <= resize(shift_right(resizeIn, inputBitNb - outputBitNb), outputBitNb);
end process;
end generate INPUT_BIGGER;
OUTPUT_BIGGER: if inputBitNb <= outputBitNb generate
process(resizeIn)
begin
mySignal <= shift_left(resize(resizeIn, outputBitNb), outputBitNb - inputBitNb);
end process;
end generate OUTPUT_BIGGER;
resizeOut <= mySignal;
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END ARCHITECTURE studentVersion;