60 lines
2.1 KiB
VHDL
60 lines
2.1 KiB
VHDL
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ARCHITECTURE test OF nanoBlaze_tester IS
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constant clockFrequency: real := 100.0E6;
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constant clockPeriod: time := (1.0/clockFrequency) * 1 sec;
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signal clock_int: std_uLogic := '1';
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signal dataReg: std_ulogic_vector(dataOut'range);
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BEGIN
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------------------------------------------------------------------------------
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-- reset and clock
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reset <= '1', '0' after 2*clockPeriod;
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clock_int <= not clock_int after clockPeriod/2;
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clock <= transport clock_int after clockPeriod*9.0/10.0;
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------------------------------------------------------------------------------
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-- enable
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en <= '1';
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------------------------------------------------------------------------------
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-- data
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storeData: process(clock_int)
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begin
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if rising_edge(clock_int) then
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if writeStrobe = '1' then
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dataReg <= dataOut;
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end if;
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end if;
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end process storeData;
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dataIn <= not dataReg;
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------------------------------------------------------------------------------
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-- error checking
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checkBus: process(clock_int)
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begin
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if rising_edge(clock_int) then
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if writeStrobe = '1' then
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if (dataAddress = 0) and (unsigned(dataOut) = 0) then
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assert false
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report "Testbench reports error (output value 0 at address 0)"
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severity failure;
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end if;
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if (dataAddress = 0) and (unsigned(dataOut) = 1) then
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assert false
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report
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cr & cr &
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"--------------------------------------------------------------------------------" & cr &
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"Testbench reports successful end of simulation (output value 1 at address 0)" & cr &
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"--------------------------------------------------------------------------------" & cr &
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cr
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severity failure;
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end if;
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end if;
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end if;
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end process checkBus;
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END ARCHITECTURE test;
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