SEm-Labos/06-07-08-09-SystemOnChip/AhbLiteComponents_test/hds/uvm@ahb@agent@hw/struct.bd

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xt "100000,16000,100500,16000"
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sf 1
tg (WTG
uid 367,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "103000,15500,105900,16700"
st "hSel"
blo "103000,16500"
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decl (Decl
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declText (MLText
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va (VaSet
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xt "2000,24200,19000,25000"
st "hSel               : std_uLogic"
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fg "0,0,32768"
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xt "100500,11625,102000,12375"
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(Line
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ro 270
xt "100000,12000,100500,12000"
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sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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xt "103000,11500,107200,12700"
st "hTrans"
blo "103000,12500"
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decl (Decl
n "hTrans"
t "std_ulogic_vector"
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va (VaSet
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fg "0,0,32768"
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xt "100500,9625,102000,10375"
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(Line
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xt "100000,10000,100500,10000"
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sf 1
tg (WTG
uid 395,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "103000,9500,107600,10700"
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uid 403,0
decl (Decl
n "hWData"
t "std_ulogic_vector"
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uid 404,0
va (VaSet
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xt "2000,25800,35500,26600"
st "hWData             : std_ulogic_vector(ahbDataBitNb-1 DOWNTO 0)"
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xt "100500,13625,102000,14375"
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(Line
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xt "100000,14000,100500,14000"
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tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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xt "103000,13500,106900,14700"
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blo "103000,14500"
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o 12
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declText (MLText
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va (VaSet
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xt "2000,26600,19000,27400"
st "hWrite             : std_uLogic"
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decl (Decl
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t "string"
b "(1 TO ahbTransactionLength)"
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xt "2000,30200,34500,31000"
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xt "2000,31000,34500,31800"
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va (VaSet
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ro 270
xt "58000,21625,59500,22375"
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xt "59500,22000,60000,22000"
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sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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xt "53600,21500,57000,22700"
st "clock"
ju 2
blo "57000,22500"
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n "clock"
t "std_ulogic"
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declText (MLText
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va (VaSet
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xt "2000,17800,19000,18600"
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shape (CompositeShape
uid 517,0
va (VaSet
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fg "0,0,32768"
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ro 270
xt "100500,21625,102000,22375"
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(Line
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ro 270
xt "100000,22000,100500,22000"
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sf 1
tg (WTG
uid 520,0
ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "103000,21500,106000,22700"
st "hClk"
blo "103000,22500"
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decl (Decl
n "hClk"
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o 7
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declText (MLText
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va (VaSet
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xt "2000,22600,19000,23400"
st "hClk               : std_uLogic"
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va (VaSet
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fg "0,0,32768"
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ro 270
xt "100500,23625,102000,24375"
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(Line
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ro 270
xt "100000,24000,100500,24000"
pts [
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sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
f (Text
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va (VaSet
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xt "103000,23500,108400,24700"
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blo "103000,24500"
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decl (Decl
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declText (MLText
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va (VaSet
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xt "2000,23400,19000,24200"
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shape (CompositeShape
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va (VaSet
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fg "0,0,32768"
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ro 270
xt "58000,23625,59500,24375"
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xt "59500,24000,60000,24000"
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sf 1
tg (WTG
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ps "PortIoTextPlaceStrategy"
stg "STSignalDisplayStrategy"
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xt "53700,23500,57000,24700"
st "reset"
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blo "57000,24500"
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decl (Decl
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t "std_ulogic"
o 5
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va (VaSet
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xt "2000,21000,19000,21800"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "84000,7625,84750,8375"
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tg (CPTG
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stg "RightVerticalLayoutStrategy"
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xt "78500,7300,83000,8700"
st "hAddr"
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blo "83000,8500"
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xt "84000,9625,84750,10375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
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xt "77100,9300,83000,10700"
st "hWData"
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blo "83000,10500"
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thePort (LogicalPort
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decl (Decl
n "hWData"
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suid 2053,0
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xt "84000,13625,84750,14375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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xt "78000,13300,83000,14700"
st "hWrite"
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blo "83000,14500"
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)
thePort (LogicalPort
m 1
decl (Decl
n "hWrite"
t "std_uLogic"
o 11
suid 2055,0
)
)
)
*52 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "84000,11625,84750,12375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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xt "77900,11300,83000,12700"
st "hTrans"
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blo "83000,12500"
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thePort (LogicalPort
m 1
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 9
suid 2059,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
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xt "84000,17625,84750,18375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "77500,17300,83000,18700"
st "hReady"
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blo "83000,18500"
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)
thePort (LogicalPort
decl (Decl
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o 2
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ps "OnEdgeStrategy"
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ro 90
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xt "84000,21625,84750,22375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "79500,21300,83000,22700"
st "hClk"
ju 2
blo "83000,22500"
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)
thePort (LogicalPort
m 1
decl (Decl
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t "std_uLogic"
o 6
suid 2063,0
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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fg "0,65535,0"
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xt "84000,23625,84750,24375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
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va (VaSet
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xt "76200,23300,83000,24700"
st "hReset_n"
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blo "83000,24500"
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thePort (LogicalPort
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decl (Decl
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t "std_uLogic"
o 7
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "84000,15625,84750,16375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "79500,15300,83000,16700"
st "hSel"
ju 2
blo "83000,16500"
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)
thePort (LogicalPort
m 1
decl (Decl
n "hSel"
t "std_uLogic"
o 8
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*57 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
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xt "67250,21625,68000,22375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "69000,21300,72800,22700"
st "clock"
blo "69000,22500"
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)
thePort (LogicalPort
decl (Decl
n "clock"
t "std_uLogic"
o 1
suid 2068,0
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)
*58 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "67250,23625,68000,24375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "69000,23300,73100,24700"
st "reset"
blo "69000,24500"
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)
thePort (LogicalPort
decl (Decl
n "reset"
t "std_uLogic"
o 3
suid 2069,0
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*59 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 90
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "67250,7625,68000,8375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
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va (VaSet
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xt "69000,7300,81500,8700"
st "driverTransaction"
blo "69000,8500"
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)
thePort (LogicalPort
decl (Decl
n "driverTransaction"
t "string"
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suid 2071,0
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]
shape (Rectangle
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va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
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xt "68000,4000,84000,26000"
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oxt "47000,20000,63000,42000"
ttg (MlTextGroup
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va (VaSet
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xt "68100,25700,83000,26900"
st "AhbLiteComponents_test"
blo "68100,26700"
tm "BdLibraryNameMgr"
)
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va (VaSet
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xt "68100,26700,76700,27900"
st "uvmAhbDriver"
blo "68100,27700"
tm "CptNameMgr"
)
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uid 982,0
va (VaSet
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xt "68100,27700,71800,28900"
st "I_driv"
blo "68100,28700"
tm "InstanceNameMgr"
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ga (GenericAssociation
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ps "EdgeToEdgeStrategy"
matrix (Matrix
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text (MLText
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va (VaSet
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xt "68000,30000,68000,30000"
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header ""
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elements [
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viewicon (ZoomableIcon
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sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
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xt "68250,24250,69750,25750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
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viewiconposition 0
portVis (PortSigDisplay
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archFileType "UNKNOWN"
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "84000,37625,84750,38375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "78500,37300,83000,38700"
st "hAddr"
ju 2
blo "83000,38500"
)
)
thePort (LogicalPort
decl (Decl
n "hAddr"
t "unsigned"
b "( ahbAddressBitNb-1 DOWNTO 0 )"
o 4
suid 2051,0
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)
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
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fg "0,65535,0"
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xt "84000,39625,84750,40375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
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xt "77100,39300,83000,40700"
st "hWData"
ju 2
blo "83000,40500"
)
)
thePort (LogicalPort
decl (Decl
n "hWData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 9
suid 2053,0
)
)
)
*66 (CptPort
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ps "OnEdgeStrategy"
shape (Triangle
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ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
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xt "84000,47625,84750,48375"
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tg (CPTG
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ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
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va (VaSet
font "Verdana,12,0"
)
xt "77600,47300,83000,48700"
st "hRData"
ju 2
blo "83000,48500"
)
)
thePort (LogicalPort
decl (Decl
n "hRData"
t "std_ulogic_vector"
b "(ahbDataBitNb-1 DOWNTO 0)"
o 1
suid 2054,0
)
)
)
*67 (CptPort
uid 999,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1000,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,43625,84750,44375"
)
tg (CPTG
uid 1001,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1002,0
va (VaSet
font "Verdana,12,0"
)
xt "78000,43300,83000,44700"
st "hWrite"
ju 2
blo "83000,44500"
)
)
thePort (LogicalPort
decl (Decl
n "hWrite"
t "std_uLogic"
o 10
suid 2055,0
)
)
)
*68 (CptPort
uid 1003,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1004,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,41625,84750,42375"
)
tg (CPTG
uid 1005,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1006,0
va (VaSet
font "Verdana,12,0"
)
xt "77900,41300,83000,42700"
st "hTrans"
ju 2
blo "83000,42500"
)
)
thePort (LogicalPort
decl (Decl
n "hTrans"
t "std_ulogic_vector"
b "(ahbTransBitNb-1 DOWNTO 0)"
o 8
suid 2059,0
)
)
)
*69 (CptPort
uid 1007,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1008,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,49625,84750,50375"
)
tg (CPTG
uid 1009,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1010,0
va (VaSet
font "Verdana,12,0"
)
xt "77500,49300,83000,50700"
st "hReady"
ju 2
blo "83000,50500"
)
)
thePort (LogicalPort
decl (Decl
n "hReady"
t "std_uLogic"
o 2
suid 2061,0
)
)
)
*70 (CptPort
uid 1011,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1012,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,51625,84750,52375"
)
tg (CPTG
uid 1013,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1014,0
va (VaSet
font "Verdana,12,0"
)
xt "78300,51300,83000,52700"
st "hResp"
ju 2
blo "83000,52500"
)
)
thePort (LogicalPort
decl (Decl
n "hResp"
t "std_uLogic"
o 3
suid 2062,0
)
)
)
*71 (CptPort
uid 1015,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1016,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,55625,84750,56375"
)
tg (CPTG
uid 1017,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1018,0
va (VaSet
font "Verdana,12,0"
)
xt "79500,55300,83000,56700"
st "hClk"
ju 2
blo "83000,56500"
)
)
thePort (LogicalPort
decl (Decl
n "hClk"
t "std_uLogic"
o 5
suid 2063,0
)
)
)
*72 (CptPort
uid 1019,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1020,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,57625,84750,58375"
)
tg (CPTG
uid 1021,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1022,0
va (VaSet
font "Verdana,12,0"
)
xt "76200,57300,83000,58700"
st "hReset_n"
ju 2
blo "83000,58500"
)
)
thePort (LogicalPort
decl (Decl
n "hReset_n"
t "std_uLogic"
o 6
suid 2064,0
)
)
)
*73 (CptPort
uid 1023,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1024,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "84000,45625,84750,46375"
)
tg (CPTG
uid 1025,0
ps "CptPortTextPlaceStrategy"
stg "RightVerticalLayoutStrategy"
f (Text
uid 1026,0
va (VaSet
font "Verdana,12,0"
)
xt "79500,45300,83000,46700"
st "hSel"
ju 2
blo "83000,46500"
)
)
thePort (LogicalPort
decl (Decl
n "hSel"
t "std_uLogic"
o 7
suid 2066,0
)
)
)
*74 (CptPort
uid 1027,0
ps "OnEdgeStrategy"
shape (Triangle
uid 1028,0
ro 270
va (VaSet
vasetType 1
fg "0,65535,0"
)
xt "67250,37625,68000,38375"
)
tg (CPTG
uid 1029,0
ps "CptPortTextPlaceStrategy"
stg "VerticalLayoutStrategy"
f (Text
uid 1030,0
va (VaSet
font "Verdana,12,0"
)
xt "69000,37300,82700,38700"
st "monitorTransaction"
blo "69000,38500"
)
)
thePort (LogicalPort
m 1
decl (Decl
n "monitorTransaction"
t "string"
o 11
suid 2071,0
)
)
)
]
shape (Rectangle
uid 1032,0
va (VaSet
vasetType 1
fg "0,65535,0"
lineColor "0,32896,0"
lineWidth 2
)
xt "68000,34000,84000,60000"
)
oxt "47000,16000,63000,42000"
ttg (MlTextGroup
uid 1033,0
ps "CenterOffsetStrategy"
stg "VerticalLayoutStrategy"
textVec [
*75 (Text
uid 1034,0
va (VaSet
)
xt "68100,59700,83000,60900"
st "AhbLiteComponents_test"
blo "68100,60700"
tm "BdLibraryNameMgr"
)
*76 (Text
uid 1035,0
va (VaSet
)
xt "68100,60700,77400,61900"
st "uvmAhbMonitor"
blo "68100,61700"
tm "CptNameMgr"
)
*77 (Text
uid 1036,0
va (VaSet
)
xt "68100,61700,72000,62900"
st "I_mon"
blo "68100,62700"
tm "InstanceNameMgr"
)
]
)
ga (GenericAssociation
uid 1037,0
ps "EdgeToEdgeStrategy"
matrix (Matrix
uid 1038,0
text (MLText
uid 1039,0
va (VaSet
font "Courier New,8,0"
)
xt "68000,64000,68000,64000"
)
header ""
)
elements [
]
)
viewicon (ZoomableIcon
uid 1040,0
sl 0
va (VaSet
vasetType 1
fg "49152,49152,49152"
)
xt "68250,58250,69750,59750"
iconName "VhdlFileViewIcon.png"
iconMaskName "VhdlFileViewIcon.msk"
ftype 10
)
viewiconposition 0
portVis (PortSigDisplay
sTC 0
sT 1
)
archFileType "UNKNOWN"
)
*78 (Wire
uid 313,0
optionalChildren [
*79 (BdJunction
uid 423,0
ps "OnConnectorStrategy"
shape (Circle
uid 424,0
va (VaSet
vasetType 1
)
xt "87600,7600,88400,8400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 314,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,8000,100000,8000"
pts [
"84750,8000"
"100000,8000"
]
)
start &49
end &22
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 317,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 318,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,6600,100500,8000"
st "hAddr"
blo "96000,7800"
tm "WireNameMgr"
)
)
on &23
)
*80 (Wire
uid 327,0
shape (OrthoPolyLine
uid 328,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,48000,100000,48000"
pts [
"100000,48000"
"84750,48000"
]
)
start &24
end &66
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 331,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 332,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,46600,101400,48000"
st "hRData"
blo "96000,47800"
tm "WireNameMgr"
)
)
on &25
)
*81 (Wire
uid 341,0
optionalChildren [
*82 (BdJunction
uid 453,0
ps "OnConnectorStrategy"
shape (Circle
uid 454,0
va (VaSet
vasetType 1
)
xt "97600,17600,98400,18400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 342,0
va (VaSet
vasetType 3
)
xt "84750,18000,100000,18000"
pts [
"100000,18000"
"84750,18000"
]
)
start &26
end &53
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 345,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 346,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,16600,101500,18000"
st "hReady"
blo "96000,17800"
tm "WireNameMgr"
)
)
on &27
)
*83 (Wire
uid 355,0
shape (OrthoPolyLine
uid 356,0
va (VaSet
vasetType 3
)
xt "84750,52000,100000,52000"
pts [
"100000,52000"
"84750,52000"
]
)
start &28
end &70
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 359,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 360,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,50600,100700,52000"
st "hResp"
blo "96000,51800"
tm "WireNameMgr"
)
)
on &29
)
*84 (Wire
uid 369,0
optionalChildren [
*85 (BdJunction
uid 447,0
ps "OnConnectorStrategy"
shape (Circle
uid 448,0
va (VaSet
vasetType 1
)
xt "95600,15600,96400,16400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 370,0
va (VaSet
vasetType 3
)
xt "84750,16000,100000,16000"
pts [
"84750,16000"
"100000,16000"
]
)
start &56
end &30
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 373,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 374,0
va (VaSet
font "Verdana,12,0"
)
xt "97000,14600,100500,16000"
st "hSel"
blo "97000,15800"
tm "WireNameMgr"
)
)
on &31
)
*86 (Wire
uid 383,0
optionalChildren [
*87 (BdJunction
uid 435,0
ps "OnConnectorStrategy"
shape (Circle
uid 436,0
va (VaSet
vasetType 1
)
xt "91600,11600,92400,12400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 384,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,12000,100000,12000"
pts [
"84750,12000"
"100000,12000"
]
)
start &52
end &32
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 387,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 388,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,10600,101100,12000"
st "hTrans"
blo "96000,11800"
tm "WireNameMgr"
)
)
on &33
)
*88 (Wire
uid 397,0
optionalChildren [
*89 (BdJunction
uid 429,0
ps "OnConnectorStrategy"
shape (Circle
uid 430,0
va (VaSet
vasetType 1
)
xt "89600,9600,90400,10400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 398,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,10000,100000,10000"
pts [
"84750,10000"
"100000,10000"
]
)
start &50
end &34
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 401,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 402,0
va (VaSet
font "Verdana,12,0"
)
xt "95000,8600,100900,10000"
st "hWData"
blo "95000,9800"
tm "WireNameMgr"
)
)
on &35
)
*90 (Wire
uid 411,0
optionalChildren [
*91 (BdJunction
uid 441,0
ps "OnConnectorStrategy"
shape (Circle
uid 442,0
va (VaSet
vasetType 1
)
xt "93600,13600,94400,14400"
radius 400
)
)
]
shape (OrthoPolyLine
uid 412,0
va (VaSet
vasetType 3
)
xt "84750,14000,100000,14000"
pts [
"84750,14000"
"100000,14000"
]
)
start &51
end &36
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 415,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 416,0
va (VaSet
font "Verdana,12,0"
)
xt "96000,12600,101000,14000"
st "hWrite"
blo "96000,13800"
tm "WireNameMgr"
)
)
on &37
)
*92 (Wire
uid 419,0
shape (OrthoPolyLine
uid 420,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,8000,88000,38000"
pts [
"88000,8000"
"88000,38000"
"84750,38000"
]
)
start &79
end &64
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 421,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 422,0
va (VaSet
)
xt "86750,37000,90450,38200"
st "hAddr"
blo "86750,38000"
tm "WireNameMgr"
)
)
on &23
)
*93 (Wire
uid 425,0
shape (OrthoPolyLine
uid 426,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,10000,90000,40000"
pts [
"90000,10000"
"90000,40000"
"84750,40000"
]
)
start &89
end &65
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 427,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 428,0
va (VaSet
)
xt "86750,39000,91350,40200"
st "hWData"
blo "86750,40000"
tm "WireNameMgr"
)
)
on &35
)
*94 (Wire
uid 431,0
shape (OrthoPolyLine
uid 432,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "84750,12000,92000,42000"
pts [
"92000,12000"
"92000,42000"
"84750,42000"
]
)
start &87
end &68
sat 32
eat 32
sty 1
stc 0
st 0
sf 1
si 0
tg (WTG
uid 433,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 434,0
va (VaSet
)
xt "86750,41000,90950,42200"
st "hTrans"
blo "86750,42000"
tm "WireNameMgr"
)
)
on &33
)
*95 (Wire
uid 437,0
shape (OrthoPolyLine
uid 438,0
va (VaSet
vasetType 3
)
xt "84750,14000,94000,44000"
pts [
"94000,14000"
"94000,44000"
"84750,44000"
]
)
start &91
end &67
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 439,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 440,0
va (VaSet
)
xt "86750,43000,90650,44200"
st "hWrite"
blo "86750,44000"
tm "WireNameMgr"
)
)
on &37
)
*96 (Wire
uid 443,0
shape (OrthoPolyLine
uid 444,0
va (VaSet
vasetType 3
)
xt "84750,16000,96000,46000"
pts [
"96000,16000"
"96000,46000"
"84750,46000"
]
)
start &85
end &73
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 445,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 446,0
va (VaSet
)
xt "86750,45000,89650,46200"
st "hSel"
blo "86750,46000"
tm "WireNameMgr"
)
)
on &31
)
*97 (Wire
uid 449,0
shape (OrthoPolyLine
uid 450,0
va (VaSet
vasetType 3
)
xt "84750,18000,98000,50000"
pts [
"98000,18000"
"98000,50000"
"84750,50000"
]
)
start &82
end &69
sat 32
eat 32
stc 0
st 0
sf 1
si 0
tg (WTG
uid 451,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 452,0
va (VaSet
)
xt "86750,49000,91150,50200"
st "hReady"
blo "86750,50000"
tm "WireNameMgr"
)
)
on &27
)
*98 (Wire
uid 457,0
shape (OrthoPolyLine
uid 458,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,8000,67250,8000"
pts [
"52750,8000"
"67250,8000"
]
)
start &13
end &59
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 459,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 460,0
va (VaSet
font "Verdana,12,0"
)
xt "54000,6600,66500,8000"
st "driverTransaction"
blo "54000,7800"
tm "WireNameMgr"
)
)
on &38
)
*99 (Wire
uid 463,0
shape (OrthoPolyLine
uid 464,0
va (VaSet
vasetType 3
lineWidth 2
)
xt "52750,38000,67250,38000"
pts [
"52750,38000"
"67250,38000"
]
)
start &18
end &74
sat 32
eat 32
sty 1
stc 0
sf 1
si 0
tg (WTG
uid 465,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 466,0
va (VaSet
font "Verdana,12,0"
)
xt "54000,36600,67700,38000"
st "monitorTransaction"
blo "54000,37800"
tm "WireNameMgr"
)
)
on &39
)
*100 (Wire
uid 508,0
shape (OrthoPolyLine
uid 509,0
va (VaSet
vasetType 3
)
xt "60000,22000,67250,22000"
pts [
"60000,22000"
"67250,22000"
]
)
start &40
end &57
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 512,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 513,0
va (VaSet
font "Verdana,12,0"
)
xt "60000,20600,63800,22000"
st "clock"
blo "60000,21800"
tm "WireNameMgr"
)
)
on &41
)
*101 (Wire
uid 522,0
shape (OrthoPolyLine
uid 523,0
va (VaSet
vasetType 3
)
xt "84750,22000,100000,22000"
pts [
"84750,22000"
"100000,22000"
]
)
start &54
end &42
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 526,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 527,0
va (VaSet
font "Verdana,12,0"
)
xt "97000,20600,100500,22000"
st "hClk"
blo "97000,21800"
tm "WireNameMgr"
)
)
on &43
)
*102 (Wire
uid 536,0
shape (OrthoPolyLine
uid 537,0
va (VaSet
vasetType 3
)
xt "84750,24000,100000,24000"
pts [
"84750,24000"
"100000,24000"
]
)
start &55
end &44
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 540,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 541,0
va (VaSet
font "Verdana,12,0"
)
xt "95000,22600,101800,24000"
st "hReset_n"
blo "95000,23800"
tm "WireNameMgr"
)
)
on &45
)
*103 (Wire
uid 550,0
shape (OrthoPolyLine
uid 551,0
va (VaSet
vasetType 3
)
xt "60000,24000,67250,24000"
pts [
"60000,24000"
"67250,24000"
]
)
start &46
end &58
sat 32
eat 32
st 0
sf 1
si 0
tg (WTG
uid 554,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 555,0
va (VaSet
font "Verdana,12,0"
)
xt "60000,22600,64100,24000"
st "reset"
blo "60000,23800"
tm "WireNameMgr"
)
)
on &47
)
*104 (Wire
uid 558,0
shape (OrthoPolyLine
uid 559,0
va (VaSet
vasetType 3
)
xt "84750,56000,92000,56000"
pts [
"84750,56000"
"92000,56000"
]
)
start &71
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 564,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 565,0
va (VaSet
font "Verdana,12,0"
)
xt "89000,54600,92500,56000"
st "hClk"
blo "89000,55800"
tm "WireNameMgr"
)
)
on &43
)
*105 (Wire
uid 566,0
shape (OrthoPolyLine
uid 567,0
va (VaSet
vasetType 3
)
xt "84750,58000,92000,58000"
pts [
"84750,58000"
"92000,58000"
]
)
start &72
sat 32
eat 16
st 0
sf 1
si 0
tg (WTG
uid 572,0
ps "ConnStartEndStrategy"
stg "STSignalDisplayStrategy"
f (Text
uid 573,0
va (VaSet
font "Verdana,12,0"
)
xt "87000,56600,93800,58000"
st "hReset_n"
blo "87000,57800"
tm "WireNameMgr"
)
)
on &45
)
]
bg "65535,65535,65535"
grid (Grid
origin "0,0"
isVisible 0
isActive 1
xSpacing 1000
xySpacing 1000
xShown 1
yShown 1
color "26368,26368,26368"
)
packageList *106 (PackageList
uid 41,0
stg "VerticalLayoutStrategy"
textVec [
*107 (Text
uid 42,0
va (VaSet
font "arial,8,1"
)
xt "0,0,5400,1000"
st "Package List"
blo "0,800"
)
*108 (MLText
uid 43,0
va (VaSet
)
xt "0,1000,17500,7000"
st "LIBRARY ieee;
  USE ieee.std_logic_1164.all;
  USE ieee.NUMERIC_STD.all;
LIBRARY AhbLite;
  USE AhbLite.ahbLite.all;"
tm "PackageList"
)
]
)
compDirBlock (MlTextGroup
uid 44,0
stg "VerticalLayoutStrategy"
textVec [
*109 (Text
uid 45,0
va (VaSet
isHidden 1
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